Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23501

1

T1

1

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3603

1

T1

1

T6

49

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21154

1

T1

1

T2

10

T3

20

auto[1]

5950

1

T1

1

T6

57

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T194	20		T193	14		T304	10
values[0]	25	1			T110	1		T305	1		T293	6
values[1]	687	1			T1	2		T47	13		T110	1
values[2]	419	1			T39	4		T47	5		T149	3
values[3]	608	1			T14	24		T95	22		T98	26
values[4]	692	1			T6	8		T146	3		T44	1
values[5]	3127	1			T6	27		T8	1		T10	2
values[6]	903	1			T6	22		T15	15		T58	9
values[7]	771	1			T99	18		T149	4		T108	22
values[8]	537	1			T12	11		T146	11		T46	11
values[9]	1370	1			T5	18		T13	15		T14	11
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	732	1			T1	2		T47	13		T110	2
values[1]	527	1			T39	4		T47	5		T147	12
values[2]	620	1			T14	24		T44	1		T95	22
values[3]	3112	1			T6	35		T10	2		T11	19
values[4]	752	1			T8	1		T15	15		T97	21
values[5]	891	1			T6	22		T58	9		T44	22
values[6]	730	1			T99	18		T149	4		T156	14
values[7]	715	1			T12	11		T13	15		T146	11
values[8]	984	1			T5	18		T14	11		T15	36
values[9]	98	1			T98	9		T149	10		T142	1
minimum	17943	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T47	13		T110	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T167	1		T226	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T47	5		T149	1		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	3		T147	12		T70	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	9		T98	13		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	15		T44	1		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1679	1			T6	6		T10	2		T11	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	13		T58	3		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	8		T97	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T143	1		T113	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	22		T46	9		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T6	12		T58	9		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T108	12		T195	1		T144	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T99	9		T149	1		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T146	1		T70	1		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T13	15		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T5	11		T15	19		T46	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	11		T52	1		T98	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T98	7		T157	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T149	1		T142	1		T221	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17784	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T306	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T17	1		T253	16		T54	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T167	17		T226	15		T53	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T149	2		T107	17		T151	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T39	1		T70	17		T143	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T98	13		T222	4		T229	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T95	9		T42	2		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T6	2		T146	2		T141	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	14		T58	4		T195	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	7		T97	10		T113	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T143	7		T113	10		T184	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T46	8		T170	1		T239	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	10		T52	16		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T108	10		T195	5		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T99	9		T149	3		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T146	10		T70	1		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	10		T46	10		T167	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	7		T15	17		T46	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T52	4		T98	11		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T98	2		T153	13		T300	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T149	9		T221	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T306	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T194	11		T193	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T304	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T110	1		T293	6		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T305	1		T307	1		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T47	13		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T226	23		T53	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T47	5		T149	1		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	3		T143	1		T144	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T14	9		T98	13		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	15		T95	13		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	6		T146	1		T70	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	1		T232	1		T151	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1636	1			T10	2		T11	19		T59	40
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	13		T8	1		T58	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	8		T44	11		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T6	12		T58	9		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T108	12		T195	1		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T99	9		T149	1		T109	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T146	1		T70	1		T156	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T46	1		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	395	1			T5	11		T15	19		T46	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T13	15		T14	11		T52	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T194	9		T193	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T304	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T181	1		T308	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	1		T253	16		T54	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T226	15		T53	5		T152	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T149	2		T107	17		T159	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T39	1		T143	2		T167	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T98	13		T229	15		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T95	9		T70	17		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	2		T146	2		T70	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T151	9		T152	13		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T141	5		T39	1		T96	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	14		T58	4		T195	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	7		T46	8		T97	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	10		T52	16		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T108	10		T195	5		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T99	9		T149	3		T109	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T146	10		T70	1		T112	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	10		T46	10		T43	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T5	7		T15	17		T46	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T52	4		T98	11		T149	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T47	1		T110	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T167	18		T226	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T47	1		T149	3		T107	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	4		T147	1		T70	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	1		T98	14		T222	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	1		T44	1		T95	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T6	3		T10	2		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	15		T58	5		T195	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	8		T97	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	1		T143	8		T113	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T44	2		T46	9		T170	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	11		T58	1		T52	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T108	11		T195	6		T144	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T99	10		T149	4		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T146	11		T70	2		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	11		T13	1		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T5	8		T15	18		T46	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	1		T52	5		T98	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T98	3		T157	1		T153	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T149	10		T142	1		T221	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T306	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	12		T144	12		T17	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T226	21		T53	5		T152	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T47	4		T151	14		T159	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T147	11		T70	18		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T14	8		T98	12		T229	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	14		T95	12		T42	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T6	5		T11	16		T59	37
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	12		T58	2		T228	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	7		T97	10		T113	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T113	8		T184	3		T33	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T44	20		T46	8		T239	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	11		T58	8		T147	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T108	11		T144	12		T247	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T99	8		T156	13		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T156	11		T113	11		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	14		T43	3		T34	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	10		T15	18		T46	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	10		T98	14		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T98	6		T309	2		T299	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T221	13		T276	5		T260	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T293	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T306	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T194	10		T193	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T304	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T110	1		T293	1		T181	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T305	1		T307	1		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T47	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T226	17		T53	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T47	1		T149	3		T107	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	4		T143	3		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	1		T98	14		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T95	10		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	3		T146	3		T70	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T44	1		T232	1		T151	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T10	2		T11	3		T59	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	15		T8	1		T58	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	8		T44	1		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	11		T58	1		T52	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T108	11		T195	6		T224	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T99	10		T149	4		T109	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T146	11		T70	2		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	11		T46	11		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T5	8		T15	18		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T13	1		T14	1		T52	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T194	10		T193	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T293	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	12		T144	12		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T226	21		T53	5		T152	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T47	4		T159	6		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T144	6		T219	8		T204	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T14	8		T98	12		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	14		T95	12		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	5		T70	12		T31	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T151	6		T152	3		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T11	16		T59	37		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	12		T58	2		T184	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	7		T44	10		T46	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	11		T58	8		T147	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T108	11		T247	19		T268	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T99	8		T109	14		T184	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T156	11		T170	12		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T156	13		T43	5		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T5	10		T15	18		T46	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T13	14		T14	10		T98	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16