Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23401

1

T1

1

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3703

1

T1

1

T14

35

T15

51

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20846

1

T1

2

T2

10

T3

20

auto[1]

6258

1

T6

27

T8

1

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	378	1			T146	3		T39	4		T70	36
values[0]	24	1			T122	1		T216	23		-	-
values[1]	729	1			T6	35		T95	22		T97	21
values[2]	548	1			T8	1		T12	11		T14	11
values[3]	507	1			T44	1		T149	3		T142	1
values[4]	2940	1			T10	2		T11	19		T13	15
values[5]	897	1			T46	22		T98	9		T99	18
values[6]	612	1			T14	9		T15	36		T39	5
values[7]	857	1			T1	1		T6	22		T46	17
values[8]	721	1			T5	18		T14	15		T52	22
values[9]	970	1			T1	1		T58	16		T44	22
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	773	1			T6	27		T8	1		T146	11
values[1]	531	1			T12	11		T14	11		T156	14
values[2]	466	1			T15	15		T44	1		T149	3
values[3]	3122	1			T10	2		T11	19		T13	15
values[4]	748	1			T39	5		T46	22		T98	9
values[5]	693	1			T1	1		T6	22		T14	9
values[6]	798	1			T46	17		T98	26		T149	4
values[7]	789	1			T5	18		T14	15		T52	22
values[8]	955	1			T1	1		T146	3		T58	16
values[9]	142	1			T39	4		T70	36		T144	21
minimum	18087	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	13		T8	1		T46	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T146	1		T95	13		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T156	14		T113	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	11		T142	1		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T143	1		T113	3		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	8		T44	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T10	2		T11	19		T13	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T47	13		T149	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	4		T46	10		T98	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T147	12		T145	13		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	12		T143	1		T195	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T14	9		T15	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T98	15		T149	1		T43	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	9		T40	1		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	11		T52	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	15		T52	1		T144	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	1		T146	1		T58	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T58	3		T44	11		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T144	13		T247	1		T310	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T39	3		T70	19		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17807	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T226	13		T18	12		T311	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	14		T46	10		T97	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T146	10		T95	9		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	10		T113	10		T145	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T220	8		T155	1		T221	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T143	7		T113	13		T222	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	7		T149	2		T184	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T141	5		T96	22		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T149	9		T17	1		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	1		T46	12		T98	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T145	13		T167	1		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	10		T143	13		T195	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	17		T69	12		T70	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T98	11		T149	3		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T46	8		T40	1		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	7		T52	4		T218	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T52	16		T31	18		T157	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	2		T70	12		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T58	4		T143	2		T108	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T144	8		T312	8		T308	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T39	1		T70	17		T155	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	2		T9	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T226	7		T18	7		T311	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	1		T40	1		T144	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T39	3		T70	19		T108	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T122	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T216	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	19		T97	11		T41	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T95	13		T156	14		T226	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	1		T12	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	11		T146	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T143	1		T113	3		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	1		T149	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T10	2		T11	19		T13	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	8		T47	13		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T46	10		T98	7		T99	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T147	12		T40	1		T145	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	4		T143	1		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	9		T15	19		T69	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	12		T98	15		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T46	9		T70	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	11		T52	1		T43	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	15		T52	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	1		T58	9		T44	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T58	3		T44	11		T47	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T146	2		T40	1		T144	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T39	1		T70	17		T108	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T216	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	16		T97	10		T159	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T95	9		T226	15		T157	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	10		T46	10		T98	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T146	10		T43	1		T174	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T143	7		T113	13		T222	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T149	2		T184	3		T150	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T141	5		T96	22		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	7		T149	9		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T46	12		T98	2		T99	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T145	13		T17	1		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	1		T143	13		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	17		T69	12		T195	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	10		T98	11		T149	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T46	8		T70	1		T112	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	7		T52	4		T43	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T52	16		T143	2		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T70	12		T170	1		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T58	4		T112	6		T224	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	15		T8	1		T46	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T146	11		T95	10		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	11		T156	1		T113	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	1		T142	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T143	8		T113	14		T222	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	8		T44	1		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T10	2		T11	3		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T47	1		T149	10		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	3		T46	13		T98	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	1		T145	14		T167	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	11		T143	14		T195	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T14	1		T15	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T98	12		T149	4		T43	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T46	9		T40	2		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	8		T52	5		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	1		T52	17		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	1		T146	3		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T58	5		T44	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T144	9		T247	1		T310	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T39	4		T70	18		T155	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17956	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T226	8		T18	10		T311	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	12		T97	10		T98	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T95	12		T156	13		T226	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T156	13		T113	8		T184	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	10		T144	12		T33	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T113	2		T53	17		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	7		T184	3		T56	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T11	16		T13	14		T59	37
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T47	12		T17	1		T160	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	2		T46	9		T98	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T147	11		T145	12		T253	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	11		T228	6		T152	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	8		T15	18		T69	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T98	14		T43	3		T34	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	8		T109	14		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	10		T218	12		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	14		T144	6		T31	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T58	8		T44	10		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T58	2		T44	10		T47	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T144	12		T310	14		T312	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T70	18		T236	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T6	5		T159	13		T313	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T226	12		T18	9		T314	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	3		T40	2		T144	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T39	4		T70	18		T108	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T122	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T216	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	18		T97	11		T41	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T95	10		T156	1		T226	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	1		T12	11		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	1		T146	11		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T143	8		T113	14		T222	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T44	1		T149	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T10	2		T11	3		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	8		T47	1		T149	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T46	13		T98	3		T99	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T147	1		T40	1		T145	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	3		T143	14		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T15	18		T69	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	11		T98	12		T149	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T46	9		T70	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	8		T52	5		T43	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T52	17		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T58	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T58	5		T44	1		T47	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T144	12		T154	11		T315	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T70	18		T108	11		T113	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T216	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	17		T97	10		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T95	12		T156	13		T226	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T98	12		T156	24		T113	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	10		T33	14		T172	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T113	2		T229	9		T53	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T144	12		T184	3		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T11	16		T13	14		T59	37
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	7		T47	12		T160	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	9		T98	6		T99	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T147	11		T145	12		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T39	2		T40	2		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	8		T15	18		T69	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	11		T98	14		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	8		T167	10		T184	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	10		T43	3		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	14		T109	14		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T58	8		T44	10		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T58	2		T44	10		T47	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16