Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23503

1

T1

2

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3601

1

T6

35

T8

1

T14

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21137

1

T1

2

T2

10

T3

20

auto[1]

5967

1

T5

18

T6

49

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	335	1			T15	15		T58	7		T47	13
values[0]	30	1			T219	9		T252	13		T250	1
values[1]	732	1			T1	1		T14	15		T46	22
values[2]	716	1			T13	15		T14	20		T95	22
values[3]	903	1			T6	27		T8	1		T15	36
values[4]	736	1			T1	1		T44	11		T149	13
values[5]	625	1			T5	18		T6	22		T146	11
values[6]	509	1			T39	5		T46	11		T98	9
values[7]	613	1			T39	4		T44	1		T143	14
values[8]	689	1			T6	8		T97	21		T185	1
values[9]	3295	1			T10	2		T11	19		T12	11
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	664	1			T14	9		T99	18		T147	12
values[1]	861	1			T13	15		T14	11		T52	5
values[2]	710	1			T6	27		T15	36		T146	3
values[3]	712	1			T1	1		T8	1		T149	13
values[4]	615	1			T5	18		T6	22		T146	11
values[5]	467	1			T39	5		T98	9		T69	25
values[6]	3023	1			T10	2		T11	19		T59	40
values[7]	675	1			T6	8		T12	11		T97	21
values[8]	931	1			T15	15		T58	7		T46	17
values[9]	202	1			T58	9		T167	18		T54	8
minimum	18244	1			T1	1		T2	10		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	9		T99	9		T156	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T147	12		T40	1		T53	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	15		T52	1		T95	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T14	11		T147	12		T70	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T146	1		T44	11		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	13		T15	19		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T149	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	1		T149	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	11		T6	12		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T44	11		T47	5		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	4		T70	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T98	7		T69	13		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T10	2		T11	19		T59	40
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	3		T44	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	1		T97	11		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	6		T110	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T47	13		T108	1		T113	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T15	8		T58	3		T46	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T58	9		T54	4		T172	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T167	1		T316	1		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17835	1			T1	1		T2	10		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T46	10		T98	13		T107	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T99	9		T145	1		T167	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T53	17		T55	2		T240	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T52	4		T95	9		T98	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T70	29		T143	2		T109	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T146	2		T149	3		T112	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	14		T15	17		T52	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T149	9		T170	1		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T149	2		T40	1		T184	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	7		T6	10		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T184	14		T247	13		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	1		T70	1		T167	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T98	2		T69	12		T170	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T141	5		T96	22		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T39	1		T143	13		T253	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	10		T97	10		T195	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T6	2		T150	14		T239	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T108	1		T113	23		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	7		T58	4		T46	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T54	4		T118	1		T318	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T167	17		T317	11		T124	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T46	12		T98	13		T107	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T47	13		T54	4		T159	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	8		T58	3		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T219	9		T250	1		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T252	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T14	15		T99	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T46	10		T98	13		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	15		T14	9		T95	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T14	11		T147	24		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T146	1		T52	1		T98	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T6	13		T8	1		T15	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T44	11		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T149	1		T156	12		T184	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	11		T6	12		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T44	11		T47	5		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T39	4		T46	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T98	7		T69	13		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T200	1		T43	7		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	3		T44	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T97	11		T185	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	6		T217	1		T239	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1731	1			T10	2		T11	19		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T46	9		T110	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T54	4		T159	2		T161	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	7		T58	4		T143	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T182	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T252	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T99	9		T145	1		T218	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T46	12		T98	13		T107	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T95	9		T167	9		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T70	12		T43	2		T240	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T146	2		T52	4		T98	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T6	14		T15	17		T52	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T149	9		T170	12		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T149	2		T184	18		T53	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	7		T6	10		T146	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T40	1		T184	14		T227	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T39	1		T46	10		T70	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T98	2		T69	12		T170	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T43	2		T150	9		T226	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T39	1		T143	13		T253	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T97	10		T40	1		T112	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T6	2		T239	4		T152	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T12	10		T141	5		T96	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T46	8		T194	9		T31	35
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	1		T99	10		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T147	1		T40	1		T53	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T52	5		T95	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T14	1		T147	1		T70	31
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T146	3		T44	1		T149	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	15		T15	18		T52	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T149	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	1		T149	3		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	8		T6	11		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	1		T47	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T39	3		T70	2		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T98	3		T69	13		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T10	2		T11	3		T59	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	4		T44	1		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	11		T97	11		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T6	3		T110	1		T150	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T47	1		T108	2		T113	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T15	8		T58	5		T46	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T58	1		T54	8		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T167	18		T316	1		T317	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18013	1			T1	1		T2	10		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T46	13		T98	14		T107	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T14	8		T99	8		T156	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T147	11		T53	17		T55	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	14		T95	12		T98	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T14	10		T147	11		T70	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T44	10		T41	1		T170	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	12		T15	18		T156	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	2		T226	12		T202	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T184	8		T227	14		T208	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	10		T6	11		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T44	10		T47	4		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	2		T17	1		T226	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T98	6		T69	12		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T11	16		T59	37		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T230	10		T253	17		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T97	10		T33	14		T254	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	5		T239	2		T152	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T47	12		T113	10		T33	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	7		T58	2		T46	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T58	8		T172	13		T118	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T124	9		T186	12		T313	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T14	14		T219	8		T319	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T46	9		T98	12		T113	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T47	1		T54	8		T159	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	8		T58	5		T143	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T219	1		T250	1		T182	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T252	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	1		T14	1		T99	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T46	13		T98	14		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	1		T14	1		T95	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	1		T147	2		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T146	3		T52	5		T98	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T6	15		T8	1		T15	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T44	1		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T149	3		T156	1		T184	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	8		T6	11		T146	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T44	1		T47	1		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	3		T46	11		T70	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T98	3		T69	13		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T200	1		T43	6		T150	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	4		T44	1		T143	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T97	11		T185	1		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	3		T217	1		T239	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T10	2		T11	3		T12	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	9		T110	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T47	12		T159	6		T320	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T15	7		T58	2		T18	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T219	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	14		T99	8		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	9		T98	12		T113	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	14		T14	8		T95	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	10		T147	22		T70	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T98	14		T147	13		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T6	12		T15	18		T70	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T44	10		T170	12		T144	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T156	11		T184	8		T53	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	10		T6	11		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	10		T47	4		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T39	2		T40	2		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T98	6		T69	12		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T43	3		T226	9		T228	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T230	10		T253	17		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T97	10		T255	2		T243	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	5		T239	2		T152	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T11	16		T58	8		T59	37
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T46	8		T194	10		T31	32

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16