Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23818

1

T1

2

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3286

1

T5

18

T6

8

T12

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20408

1

T1

1

T2

10

T3

20

auto[1]

6696

1

T1

1

T6

22

T9

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	551	1			T1	1		T9	3		T60	4
values[0]	71	1			T110	1		T227	31		T238	28
values[1]	720	1			T39	4		T52	5		T97	21
values[2]	3121	1			T10	2		T11	19		T13	15
values[3]	537	1			T6	22		T146	3		T44	1
values[4]	623	1			T12	11		T14	11		T44	11
values[5]	751	1			T58	7		T95	22		T98	9
values[6]	782	1			T8	1		T146	11		T39	5
values[7]	798	1			T98	26		T142	1		T143	14
values[8]	634	1			T14	15		T46	33		T149	3
values[9]	1003	1			T1	1		T5	18		T6	35
minimum	17513	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	612	1			T13	15		T15	36		T39	4
values[1]	3110	1			T10	2		T11	19		T15	15
values[2]	653	1			T6	22		T146	3		T149	4
values[3]	656	1			T12	11		T14	11		T44	11
values[4]	715	1			T44	11		T98	9		T99	18
values[5]	719	1			T8	1		T146	11		T58	7
values[6]	870	1			T14	15		T98	26		T142	1
values[7]	559	1			T5	18		T46	33		T47	18
values[8]	807	1			T1	1		T6	8		T14	9
values[9]	159	1			T1	1		T6	27		T143	8
minimum	18244	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	19		T97	11		T185	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	15		T39	3		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T10	2		T11	19		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T224	1		T232	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	12		T146	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	4		T108	1		T41	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	11		T44	11		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T46	9		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T70	19		T43	4		T194	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T44	11		T98	7		T99	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	1		T146	1		T58	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	4		T143	2		T226	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T98	15		T113	3		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	15		T142	1		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T46	10		T147	12		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	11		T46	1		T47	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T14	9		T69	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	6		T52	1		T98	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T1	1		T6	13		T184	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T143	1		T18	2		T280	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17847	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T110	1		T31	1		T296	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	17		T97	10		T145	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T39	1		T52	4		T184	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T15	7		T141	5		T96	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T224	4		T55	5		T240	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	10		T146	2		T149	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T40	3		T108	1		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T95	9		T149	9		T220	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	10		T46	8		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T70	17		T43	2		T194	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T98	2		T99	9		T70	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T146	10		T58	4		T70	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T39	1		T143	15		T226	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T98	11		T113	13		T218	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T112	4		T113	10		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T46	12		T167	1		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	7		T46	10		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T69	12		T112	6		T195	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	2		T52	16		T98	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T6	14		T184	15		T233	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T143	7		T18	10		T280	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T31	1		T296	10		T242	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T1	1		T9	3		T60	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T52	1		T147	12		T31	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T110	1		T227	15		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T238	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T97	11		T145	13		T226	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T39	3		T52	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T10	2		T11	19		T15	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	15		T184	4		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	12		T146	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T40	4		T108	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	11		T44	11		T149	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	1		T46	9		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T58	3		T95	13		T70	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T98	7		T70	1		T41	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	1		T146	1		T70	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	4		T44	11		T99	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T98	15		T109	15		T113	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	1		T143	1		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	10		T185	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	15		T46	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T6	13		T14	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T5	11		T6	6		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17369	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T184	15		T103	9		T304	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T52	16		T31	17		T280	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T227	16		T238	1		T246	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T238	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T97	10		T145	13		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	1		T52	4		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T15	24		T141	5		T96	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T184	3		T224	4		T55	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	10		T146	2		T112	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T40	3		T108	1		T222	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T149	12		T40	1		T254	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	10		T46	8		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T58	4		T95	9		T70	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T98	2		T70	1		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T146	10		T70	12		T107	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T39	1		T99	9		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T98	11		T109	14		T113	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T143	13		T112	4		T227	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T46	12		T42	2		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	10		T149	2		T113	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	14		T69	12		T112	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	7		T6	2		T98	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	18		T97	11		T185	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	1		T39	4		T52	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T10	2		T11	3		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T224	5		T232	1		T55	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	11		T146	3		T149	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	5		T108	2		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	1		T44	1		T95	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	11		T46	9		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T70	18		T43	4		T194	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T44	1		T98	3		T99	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	1		T146	11		T58	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T39	3		T143	17		T226	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T98	12		T113	14		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	1		T142	1		T112	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T46	13		T147	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	8		T46	11		T47	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T14	1		T69	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	3		T52	17		T98	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T1	1		T6	15		T184	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T143	8		T18	12		T280	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18015	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T110	1		T31	2		T296	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	18		T97	10		T145	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	14		T184	3		T55	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T11	16		T15	7		T58	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T240	8		T223	15		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	11		T156	13		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	2		T41	1		T29	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	10		T44	10		T95	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	8		T170	12		T239	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T70	18		T43	2		T194	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	10		T98	6		T99	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T58	2		T70	12		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	2		T226	9		T202	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T98	14		T113	2		T218	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	14		T113	8		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T46	9		T147	11		T42	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	10		T47	16		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	8		T69	12		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	5		T98	12		T147	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T6	12		T184	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T280	9		T244	1		T245	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T227	14		T152	3		T284	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T296	16		T242	9		T178	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	452	1			T1	1		T9	3		T60	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T52	17		T147	1		T31	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T110	1		T227	17		T238	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T238	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T97	11		T145	14		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	4		T52	5		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T10	2		T11	3		T15	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	1		T184	4		T224	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	11		T146	3		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T40	5		T108	2		T222	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	1		T44	1		T149	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	11		T46	9		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T58	5		T95	10		T70	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T98	3		T70	2		T41	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T8	1		T146	11		T70	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	3		T44	1		T99	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T98	12		T109	15		T113	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T142	1		T143	14		T112	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T46	13		T185	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T46	11		T149	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T1	1		T6	15		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	8		T6	3		T47	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17513	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T184	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T147	11		T31	19		T280	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T227	14		T246	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T238	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T97	10		T145	12		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	2		T241	11		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T11	16		T15	25		T58	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	14		T184	3		T240	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	11		T144	12		T263	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T40	2		T230	10		T178	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	10		T44	10		T156	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T46	8		T41	1		T29	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T58	2		T95	12		T70	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T98	6		T41	1		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T70	12		T156	11		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	2		T44	10		T99	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T98	14		T109	14		T113	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T227	9		T159	6		T247	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T46	9		T42	3		T160	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	14		T113	8		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	12		T14	8		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	10		T6	5		T47	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16