Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T13	1		T15	18		T97	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	4		T52	5		T31	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T10	2		T11	3		T15	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	1		T224	5		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	11		T146	3		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	3		T108	2		T112	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	11		T44	1		T149	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	1		T46	9		T149	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T70	20		T41	2		T43	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	1		T95	10		T98	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T8	1		T146	11		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T58	5		T39	3		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T113	11		T42	4		T17	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T142	1		T112	5		T113	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	1		T46	13		T47	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	8		T14	1		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T52	17		T147	1		T69	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	3		T98	14		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T1	1		T6	15		T184	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T1	1		T143	8		T18	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T13	14		T15	18		T97	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T152	3		T55	2		T240	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T11	16		T15	7		T58	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T144	6		T223	15		T241	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	11		T156	13		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T40	2		T242	8		T178	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T44	10		T220	11		T243	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	10		T46	8		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T70	18		T41	1		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T44	10		T95	12		T98	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T98	14		T70	12		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T58	2		T39	2		T227	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T113	8		T42	3		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T113	2		T218	12		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	8		T46	9		T47	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	10		T14	14		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	13		T69	12		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	5		T98	12		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T6	12		T184	5		T172	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T244	1		T234	10		T245	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T9	3		T60	4		T61	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T110	1		T227	17		T231	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T235	1		T236	6		T237	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T97	11		T110	1		T145	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T52	5		T31	2		T152	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T10	2		T11	3		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	4		T144	1		T224	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	11		T146	3		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T46	9		T40	3		T108	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	11		T44	1		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	1		T149	4		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T70	20		T41	2		T194	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T58	5		T95	10		T98	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T8	1		T146	11		T70	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	3		T44	1		T99	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T98	12		T156	1		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T143	14		T112	5		T113	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	13		T142	1		T185	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	1		T46	11		T149	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T1	1		T6	15		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	1		T5	8		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17513	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T227	14		T238	11		T246	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T236	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T97	10		T145	12		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T152	3		T55	2		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T11	16		T13	14		T15	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T144	6		T223	15		T241	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	11		T144	12		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T46	8		T40	2		T178	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T44	10		T156	13		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	10		T239	2		T159	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T70	18		T41	1		T194	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T58	2		T95	12		T98	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T70	12		T43	2		T31	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T39	2		T44	10		T99	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T98	14		T156	11		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T113	2		T218	12		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T46	9		T113	8		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	14		T167	10		T229	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	12		T14	8		T47	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	10		T6	5		T98	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16