Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23606

1

T1

2

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3498

1

T6

8

T8

1

T14

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21203

1

T1

2

T2

10

T3

20

auto[1]

5901

1

T5

18

T6

22

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T54	8		-	-		-	-
values[0]	26	1			T40	1		T219	9		T179	1
values[1]	709	1			T1	1		T14	15		T46	22
values[2]	728	1			T13	15		T14	20		T95	22
values[3]	951	1			T6	27		T15	36		T146	3
values[4]	693	1			T1	1		T8	1		T44	22
values[5]	621	1			T5	18		T6	22		T47	5
values[6]	503	1			T146	11		T39	5		T46	11
values[7]	628	1			T39	4		T143	14		T185	1
values[8]	630	1			T6	8		T44	1		T97	21
values[9]	3686	1			T10	2		T11	19		T12	11
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1003	1			T1	1		T14	35		T46	22
values[1]	829	1			T13	15		T52	5		T95	22
values[2]	669	1			T15	36		T146	3		T44	11
values[3]	791	1			T1	1		T6	27		T8	1
values[4]	580	1			T5	18		T6	22		T146	11
values[5]	531	1			T39	5		T98	9		T69	25
values[6]	2926	1			T10	2		T11	19		T59	40
values[7]	698	1			T6	8		T12	11		T185	1
values[8]	820	1			T58	7		T46	17		T47	13
values[9]	326	1			T15	15		T58	9		T167	18
minimum	17931	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T14	15		T98	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T14	20		T46	10		T147	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	15		T52	1		T95	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T147	12		T70	32		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T146	1		T44	11		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	19		T52	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T6	13		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T156	12		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	11		T6	12		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	11		T47	5		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	4		T70	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T98	7		T69	13		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T10	2		T11	19		T59	40
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	3		T44	1		T97	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	1		T185	1		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	6		T108	1		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T47	13		T113	12		T195	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T58	3		T46	9		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T58	9		T54	4		T172	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	8		T167	1		T152	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17787	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T98	13		T99	9		T145	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T46	12		T107	17		T112	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T52	4		T95	9		T98	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T70	29		T143	2		T109	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	2		T112	4		T170	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	17		T52	16		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	14		T149	9		T170	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	1		T184	14		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	7		T6	10		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T184	3		T247	13		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	1		T70	1		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T98	2		T69	12		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T141	5		T96	22		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T39	1		T97	10		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	10		T40	1		T195	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T6	2		T108	1		T150	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T113	23		T195	6		T222	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T58	4		T46	8		T143	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T54	4		T223	14		T249	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T15	7		T167	17		T152	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T54	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T219	9		T250	1		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T40	1		T179	1		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T14	15		T98	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	10		T107	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	15		T95	13		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	20		T147	24		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	13		T146	1		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T15	19		T52	1		T70	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T44	11		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T44	11		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	11		T6	12		T108	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T47	5		T40	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T146	1		T39	4		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T98	7		T69	13		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T200	1		T43	7		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T39	3		T143	1		T185	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T40	2		T112	1		T33	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	6		T44	1		T97	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1817	1			T10	2		T11	19		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T15	8		T58	3		T46	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T54	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T252	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T98	13		T99	9		T145	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	12		T107	17		T112	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T95	9		T224	4		T56	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T70	12		T167	9		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	14		T146	2		T52	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T15	17		T52	16		T70	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T149	9		T170	12		T184	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T149	2		T184	3		T227	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	7		T6	10		T108	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T40	1		T184	14		T153	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T146	10		T39	1		T46	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T98	2		T69	12		T170	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	2		T150	9		T239	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T39	1		T143	13		T253	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	1		T112	10		T157	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T6	2		T97	10		T152	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T12	10		T141	5		T96	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T15	7		T58	4		T46	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T1	1		T14	1		T98	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T14	2		T46	13		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T52	5		T95	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T147	1		T70	31		T143	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T146	3		T44	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	18		T52	17		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T6	15		T149	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	1		T156	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	8		T6	11		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T44	1		T47	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	3		T70	2		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T98	3		T69	13		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T10	2		T11	3		T59	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T39	4		T44	1		T97	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T12	11		T185	1		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T6	3		T108	2		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	1		T113	25		T195	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T58	5		T46	9		T143	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T58	1		T54	8		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	8		T167	18		T152	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	14		T98	12		T99	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T14	18		T46	9		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	14		T95	12		T98	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T147	11		T70	30		T109	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	10		T41	1		T170	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	18		T229	16		T162	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	12		T144	6		T184	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T156	11		T184	10		T29	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	10		T6	11		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	10		T47	4		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T39	2		T17	1		T226	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T98	6		T69	12		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T11	16		T59	37		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T97	10		T230	10		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T33	14		T239	2		T254	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	5		T152	3		T159	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T47	12		T113	10		T33	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T58	2		T46	8		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T58	8		T172	13		T223	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T15	7		T152	12		T124	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T219	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T54	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T219	1		T250	1		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T40	1		T179	1		T252	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T14	1		T98	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T46	13		T107	18		T112	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T95	10		T41	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	2		T147	2		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	15		T146	3		T52	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T15	18		T52	17		T70	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T44	1		T149	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T44	1		T149	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	8		T6	11		T108	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	1		T40	2		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T146	11		T39	3		T46	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T98	3		T69	13		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T200	1		T43	6		T150	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	4		T143	14		T185	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T40	3		T112	11		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	3		T44	1		T97	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T10	2		T11	3		T12	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T15	8		T58	5		T46	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T219	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T14	14		T98	12		T99	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T46	9		T113	11		T42	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	14		T95	12		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	18		T147	22		T70	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	12		T98	14		T147	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T15	18		T70	18		T109	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	10		T170	12		T144	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	10		T156	11		T184	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	10		T6	11		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T47	4		T184	10		T247	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T39	2		T40	2		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T98	6		T69	12		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T43	3		T239	2		T226	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T41	1		T253	17		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T33	7		T255	2		T243	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	5		T97	10		T230	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T11	16		T58	8		T59	37
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T15	7		T58	2		T46	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16