Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23606

1

T2

10

T3

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3498

1

T1

2

T6

49

T14

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20917

1

T2

10

T3

20

T4

20

auto[1]

6187

1

T1

2

T6

35

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	103	1			T112	7		T158	1		T204	17
values[1]	500	1			T44	1		T70	27		T40	1
values[2]	2912	1			T10	2		T11	19		T12	11
values[3]	555	1			T5	18		T39	5		T44	11
values[4]	716	1			T1	1		T14	15		T58	9
values[5]	928	1			T6	27		T13	15		T15	15
values[6]	684	1			T6	8		T14	11		T98	9
values[7]	680	1			T1	1		T6	22		T8	1
values[8]	635	1			T146	11		T46	22		T98	26
values[9]	1470	1			T15	36		T146	3		T58	7
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	675	1			T12	11		T44	1		T70	27
values[1]	3009	1			T5	18		T10	2		T11	19
values[2]	532	1			T1	1		T39	5		T47	5
values[3]	806	1			T14	15		T15	15		T58	9
values[4]	858	1			T6	35		T13	15		T95	22
values[5]	603	1			T1	1		T14	11		T98	9
values[6]	766	1			T6	22		T8	1		T14	9
values[7]	694	1			T52	17		T98	26		T149	10
values[8]	1005	1			T15	36		T146	3		T46	22
values[9]	228	1			T58	7		T47	13		T69	25
minimum	17928	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T70	1		T112	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T44	1		T70	13		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T5	11		T10	2		T11	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T147	12		T149	1		T156	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	4		T47	5		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T98	13		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	8		T58	9		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	15		T46	9		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	6		T13	15		T95	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	13		T147	14		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	11		T98	7		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	1		T142	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	1		T14	9		T44	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	12		T146	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T52	1		T98	15		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T143	1		T43	1		T229	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T146	1		T46	10		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T15	19		T97	11		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T58	3		T47	13		T69	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T108	12		T228	7		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T195	1		T100	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	10		T70	1		T112	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T70	12		T43	2		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T5	7		T141	5		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T149	3		T170	1		T226	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	1		T149	2		T233	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T98	13		T40	1		T194	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	7		T39	1		T52	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	8		T112	4		T167	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	2		T95	9		T99	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	14		T170	1		T184	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T98	2		T40	2		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T109	14		T224	6		T159	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T70	17		T108	1		T227	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	10		T146	10		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T52	16		T98	11		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	13		T43	1		T229	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	2		T46	12		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	17		T97	10		T113	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T58	4		T69	12		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T108	10		T228	9		T246	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T195	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T112	1		T204	11		T256	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T158	1		T257	11		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T70	1		T40	1		T167	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T44	1		T70	13		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T10	2		T11	19		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T147	12		T149	1		T41	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	11		T39	4		T44	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T98	13		T156	26		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T58	9		T39	3		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	1		T14	15		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	15		T15	8		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	13		T147	14		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	6		T14	11		T98	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T185	1		T109	15		T31	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T14	9		T44	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	1		T6	12		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	10		T98	15		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T146	1		T143	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T146	1		T58	3		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	453	1			T15	19		T97	11		T108	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T112	6		T204	6		T256	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T257	13		T249	5		T258	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T70	1		T167	9		T18	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T70	12		T195	2		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T12	10		T141	5		T46	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T149	3		T170	1		T171	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	7		T39	1		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T98	13		T40	1		T194	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	1		T149	2		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T46	8		T112	4		T167	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	7		T52	4		T95	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	14		T170	1		T184	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	2		T98	2		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T109	14		T31	17		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T70	17		T108	1		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	10		T161	15		T248	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T46	12		T98	11		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T146	10		T143	13		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T146	2		T58	4		T52	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T15	17		T97	10		T108	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	11		T70	2		T112	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T44	1		T70	13		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T5	8		T10	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	1		T149	4		T156	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	3		T47	1		T149	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	1		T98	14		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	8		T58	1		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	1		T46	9		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	3		T13	1		T95	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	15		T147	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	1		T98	3		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T142	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	1		T14	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	11		T146	11		T150	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T52	17		T98	12		T149	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T143	14		T43	2		T229	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T146	3		T46	13		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T15	18		T97	11		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T58	5		T47	1		T69	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T108	11		T228	10		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T195	3		T100	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T113	2		T167	10		T33	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T70	12		T43	2		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T5	10		T11	16		T59	37
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T147	11		T156	24		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T39	2		T47	4		T219	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T98	12		T194	10		T159	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	7		T58	8		T42	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	14		T46	8		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	5		T13	14		T95	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	12		T147	13		T184	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	10		T98	6		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T109	14		T159	6		T172	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	8		T44	10		T70	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T6	11		T220	2		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T98	14		T144	6		T240	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T229	9		T223	18		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	9		T239	2		T226	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T15	18		T97	10		T113	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T58	2		T47	12		T69	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T108	11		T228	6		T259	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T112	7		T204	7		T256	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T158	1		T257	14		T249	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T70	2		T40	1		T167	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	1		T70	13		T195	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T10	2		T11	3		T12	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T147	1		T149	4		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	8		T39	3		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T98	14		T156	2		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T58	1		T39	4		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T14	1		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T15	8		T52	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	15		T147	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	3		T14	1		T98	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T185	1		T109	15		T31	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	1		T14	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T6	11		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T46	13		T98	12		T149	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	11		T143	14		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	376	1			T146	3		T58	5		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	454	1			T15	18		T97	11		T108	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T204	10		T256	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T257	10		T258	5		T260	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T167	10		T33	14		T18	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T70	12		T43	2		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T11	16		T59	37		T51	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T147	11		T41	1		T261	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	10		T39	2		T44	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T98	12		T156	24		T194	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T58	8		T42	3		T253	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	14		T46	8		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	14		T15	7		T95	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	12		T147	13		T184	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	5		T14	10		T98	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T109	14		T31	19		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	8		T44	10		T70	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	11		T248	10		T262	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	9		T98	14		T263	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T229	9		T223	18		T186	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T58	2		T47	12		T69	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T15	18		T97	10		T108	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16