Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21033

1

T1

1

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

6071

1

T1

1

T6

27

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21242

1

T1

2

T2

10

T3

20

auto[1]

5862

1

T6

35

T8

1

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T54	8		T231	8		T179	1
values[0]	90	1			T15	36		T113	19		T226	20
values[1]	663	1			T146	3		T47	5		T147	12
values[2]	775	1			T14	9		T98	26		T70	25
values[3]	944	1			T1	1		T6	27		T15	15
values[4]	722	1			T1	1		T146	11		T44	11
values[5]	766	1			T6	22		T95	22		T99	18
values[6]	763	1			T12	11		T14	11		T39	5
values[7]	608	1			T8	1		T39	4		T47	13
values[8]	519	1			T5	18		T58	9		T147	12
values[9]	3316	1			T6	8		T10	2		T11	19
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1013	1			T14	9		T15	36		T146	3
values[1]	3013	1			T10	2		T11	19		T15	15
values[2]	989	1			T1	1		T6	27		T44	11
values[3]	673	1			T1	1		T146	11		T98	26
values[4]	737	1			T6	22		T95	22		T99	18
values[5]	615	1			T12	11		T14	11		T39	5
values[6]	669	1			T39	4		T47	13		T70	2
values[7]	677	1			T5	18		T8	1		T58	9
values[8]	653	1			T13	15		T14	15		T46	28
values[9]	131	1			T6	8		T40	2		T184	25
minimum	17934	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T15	19		T146	1		T47	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T14	9		T98	15		T69	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T58	3		T185	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1663	1			T10	2		T11	19		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	1		T98	7		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T6	13		T44	11		T97	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T146	1		T98	13		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T113	12		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	12		T95	13		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T99	9		T147	14		T70	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T39	4		T46	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	11		T44	11		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	3		T47	13		T34	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T70	1		T167	1		T29	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	11		T52	1		T147	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T58	9		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T46	9		T52	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	15		T14	15		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T6	6		T204	11		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T40	1		T184	11		T265	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T252	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T15	17		T146	2		T149	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T98	11		T69	12		T109	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T58	4		T145	1		T167	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1056	1			T15	7		T141	5		T96	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T98	2		T149	9		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	14		T97	10		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T146	10		T98	13		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T113	11		T170	1		T167	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	10		T95	9		T195	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T99	9		T70	17		T239	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	10		T39	1		T46	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T107	17		T31	1		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	1		T34	15		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T70	1		T167	1		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	7		T52	4		T108	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T43	1		T17	3		T157	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T46	8		T52	16		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	10		T143	2		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T6	2		T204	6		T264	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T40	1		T184	14		T103	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T252	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T54	4		T231	1		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T15	19		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T113	9		T226	13		T160	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T146	1		T47	5		T147	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T69	13		T156	12		T109	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	3		T224	1		T152	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	9		T98	15		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T1	1		T58	3		T98	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T6	13		T15	8		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T146	1		T98	13		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T44	11		T97	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	12		T95	13		T195	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T99	9		T147	14		T70	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T39	4		T46	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	11		T44	11		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	3		T47	13		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	1		T107	1		T29	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	11		T147	12		T156	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T58	9		T70	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	6		T46	9		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1726	1			T10	2		T11	19		T13	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T54	4		T231	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T15	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T113	10		T226	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	2		T149	3		T143	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T69	12		T109	14		T184	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	2		T224	6		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T98	11		T70	12		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T58	4		T98	2		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	14		T15	7		T112	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	10		T98	13		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T97	10		T113	11		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	10		T95	9		T195	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T99	9		T70	17		T170	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	10		T39	1		T46	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T31	1		T239	4		T253	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	1		T34	15		T226	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T107	17		T29	10		T159	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T5	7		T223	14		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T70	1		T167	1		T222	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	2		T46	8		T52	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1132	1			T141	5		T46	10		T96	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T15	18		T146	3		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	1		T98	12		T69	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T58	5		T185	1		T145	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1404	1			T10	2		T11	3		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T98	3		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	15		T44	1		T97	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	11		T98	14		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T113	12		T170	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	11		T95	10		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T99	10		T147	1		T70	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	11		T39	3		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	1		T44	1		T107	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	4		T47	1		T34	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T70	2		T167	2		T29	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	8		T52	5		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	1		T58	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	9		T52	17		T149	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T14	1		T46	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T6	3		T204	7		T264	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T40	2		T184	15		T265	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T252	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	18		T47	4		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T14	8		T98	14		T69	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T58	2		T167	10		T152	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1315	1			T11	16		T15	7		T59	37
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T98	6		T43	2		T31	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	12		T44	10		T97	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T98	12		T144	12		T145	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T113	11		T33	14		T227	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	11		T95	12		T156	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T99	8		T147	13		T70	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	2		T46	9		T19	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	10		T44	10		T144	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T47	12		T34	11		T226	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	13		T33	7		T253	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	10		T147	11		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T58	8		T17	2		T254	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T46	8		T113	2		T20	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	14		T14	14		T218	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T6	5		T204	10		T266	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T184	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T54	8		T231	8		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T15	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T113	11		T226	8		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T146	3		T47	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T69	13		T156	1		T109	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	3		T224	7		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	1		T98	12		T70	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T58	5		T98	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	15		T15	8		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T146	11		T98	14		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	1		T44	1		T97	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	11		T95	10		T195	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T99	10		T147	1		T70	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	11		T39	3		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	1		T44	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	4		T47	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T107	18		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T5	8		T147	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T58	1		T70	2		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	3		T46	9		T52	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1491	1			T10	2		T11	3		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T15	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T113	8		T226	12		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T47	4		T147	11		T151	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T69	12		T156	11		T109	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T40	2		T152	3		T219	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	8		T98	14		T70	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T58	2		T98	6		T167	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	12		T15	7		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T98	12		T144	12		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T44	10		T97	10		T113	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T6	11		T95	12		T229	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T99	8		T147	13		T70	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	2		T46	9		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	10		T44	10		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T47	12		T34	11		T226	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	13		T33	7		T159	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	10		T147	11		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T58	8		T254	17		T263	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	5		T46	8		T108	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1367	1			T11	16		T13	14		T14	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16