Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23870

1

T1

2

T2

10

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3234

1

T6

22

T13

15

T14

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21045

1

T1

1

T2

10

T3

20

auto[1]

6059

1

T1

1

T5

18

T6

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	364	1			T70	36		T40	2		T112	7
values[0]	1	1			T171	1		-	-		-	-
values[1]	655	1			T6	22		T14	11		T146	3
values[2]	591	1			T58	7		T47	13		T156	14
values[3]	560	1			T1	1		T39	5		T98	9
values[4]	620	1			T5	18		T14	9		T46	17
values[5]	3059	1			T1	1		T10	2		T11	19
values[6]	959	1			T6	27		T13	15		T15	36
values[7]	729	1			T6	8		T14	15		T58	9
values[8]	668	1			T12	11		T44	11		T47	5
values[9]	977	1			T8	1		T39	4		T52	5
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	506	1			T6	22		T14	11		T97	21
values[1]	531	1			T58	7		T47	13		T98	9
values[2]	658	1			T1	1		T39	5		T149	10
values[3]	2984	1			T5	18		T10	2		T11	19
values[4]	837	1			T1	1		T6	27		T13	15
values[5]	818	1			T95	22		T70	2		T156	14
values[6]	731	1			T6	8		T12	11		T14	15
values[7]	645	1			T44	11		T47	5		T185	1
values[8]	1040	1			T8	1		T39	4		T52	5
values[9]	159	1			T147	12		T112	7		T247	33
minimum	18195	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	11		T97	11		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	12		T149	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T58	3		T98	7		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	13		T142	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T39	4		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T69	13		T70	13		T195	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T5	11		T10	2		T11	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T46	9		T108	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	1		T6	13		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	15		T15	19		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T70	1		T156	14		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T95	13		T185	1		T33	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	6		T12	1		T58	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	15		T46	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T47	5		T110	1		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T44	11		T185	1		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	1		T39	3		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T147	26		T70	19		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T147	12		T208	13		T267	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T112	1		T247	20		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17859	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T146	1		T143	1		T145	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T97	10		T149	2		T108	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T6	10		T149	3		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T58	4		T98	2		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T40	2		T112	10		T184	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	1		T149	9		T143	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T69	12		T70	12		T195	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T5	7		T141	5		T52	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T46	8		T195	4		T170	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	14		T15	7		T98	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	17		T146	10		T46	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T70	1		T108	1		T195	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T95	9		T226	19		T56	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	2		T12	10		T53	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T46	10		T170	1		T167	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	2		T17	1		T31	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T112	4		T223	14		T231	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T39	1		T52	4		T113	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T70	17		T143	7		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T208	11		T269	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T112	6		T247	13		T268	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T146	2		T143	13		T145	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T208	13		T270	15		T267	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T70	19		T40	1		T112	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T171	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	11		T97	11		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	12		T146	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T58	3		T156	14		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T47	13		T142	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T39	4		T98	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T69	13		T70	13		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	11		T14	9		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T46	9		T108	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T1	1		T10	2		T11	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T44	1		T46	10		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T6	13		T98	15		T99	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	15		T15	19		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	6		T58	9		T44	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	15		T46	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T12	1		T47	5		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T44	11		T185	1		T223	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	1		T39	3		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T147	26		T143	1		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T208	11		T270	14		T114	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T70	17		T40	1		T112	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T97	10		T149	2		T108	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	10		T146	2		T149	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T58	4		T17	3		T159	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T40	2		T112	10		T184	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T39	1		T98	2		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T69	12		T70	12		T195	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	7		T52	16		T98	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T46	8		T195	4		T170	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T15	7		T141	5		T96	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	12		T145	13		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	14		T98	11		T99	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	17		T146	10		T95	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	2		T70	1		T108	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T46	10		T170	1		T167	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	10		T43	2		T31	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T223	14		T231	7		T18	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T39	1		T52	4		T113	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T143	7		T107	17		T112	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	1		T97	11		T149	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	11		T149	4		T40	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T58	5		T98	3		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	1		T142	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T39	3		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T69	13		T70	13		T195	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T5	8		T10	2		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	9		T108	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	1		T6	15		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	1		T15	18		T146	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T70	2		T156	1		T108	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T95	10		T185	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	3		T12	11		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T46	11		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T47	1		T110	1		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T44	1		T185	1		T112	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	1		T39	4		T52	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T147	2		T70	18		T143	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T147	1		T208	12		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T112	7		T247	14		T268	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18017	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T146	3		T143	14		T145	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	10		T97	10		T108	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T6	11		T113	11		T170	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T58	2		T98	6		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T47	12		T40	2		T184	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T39	2		T41	1		T167	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T69	12		T70	12		T218	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T5	10		T11	16		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T46	8		T145	12		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	12		T15	7		T98	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	14		T15	18		T46	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T156	13		T144	12		T239	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T95	12		T33	7		T226	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	5		T58	8		T44	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	14		T184	10		T53	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	4		T43	3		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	10		T223	15		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T113	8		T41	1		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T147	24		T70	18		T113	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T147	11		T208	12		T267	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T247	19		T271	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T228	6		T202	12		T24	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T184	5		T272	11		T273	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T208	12		T270	15		T267	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T70	18		T40	2		T112	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T171	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	1		T97	11		T149	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	11		T146	3		T149	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T58	5		T156	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T47	1		T142	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T39	3		T98	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T69	13		T70	13		T195	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	8		T14	1		T52	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	9		T108	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T1	1		T10	2		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	1		T46	13		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T6	15		T98	12		T99	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T15	18		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	3		T58	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T46	11		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	11		T47	1		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T44	1		T185	1		T223	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	1		T39	4		T52	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T147	2		T143	8		T107	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T208	12		T270	14		T267	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T70	18		T247	19		T274	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	10		T97	10		T108	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	11		T113	11		T170	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T58	2		T156	13		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	12		T40	2		T184	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	2		T98	6		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T69	12		T70	12		T218	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	10		T14	8		T98	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T46	8		T159	8		T154	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T11	16		T15	7		T59	37
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	9		T145	12		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	12		T98	14		T99	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	14		T15	18		T95	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	5		T58	8		T44	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	14		T184	10		T53	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T47	4		T43	3		T31	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T44	10		T223	15		T18	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T147	11		T113	8		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T147	24		T113	2		T144	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16