Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23554

1

T2

10

T3

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3550

1

T1

2

T5

18

T6

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21058

1

T1

1

T2

10

T3

20

auto[1]

6046

1

T1

1

T5

18

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T275	20		-	-		-	-
values[0]	33	1			T276	6		T277	11		T22	2
values[1]	718	1			T1	2		T6	27		T14	11
values[2]	656	1			T58	9		T44	11		T70	36
values[3]	999	1			T6	8		T146	11		T39	4
values[4]	645	1			T8	1		T39	5		T69	25
values[5]	697	1			T58	7		T98	26		T149	10
values[6]	599	1			T5	18		T13	15		T44	1
values[7]	628	1			T12	11		T14	9		T15	36
values[8]	3116	1			T10	2		T11	19		T59	40
values[9]	1072	1			T6	22		T14	15		T15	15
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T1	2		T6	27		T14	11
values[1]	785	1			T58	9		T44	11		T70	36
values[2]	729	1			T6	8		T146	11		T39	4
values[3]	898	1			T8	1		T39	5		T98	26
values[4]	556	1			T58	7		T149	10		T156	12
values[5]	566	1			T5	18		T13	15		T15	36
values[6]	3185	1			T10	2		T11	19		T12	11
values[7]	524	1			T146	3		T47	13		T147	12
values[8]	777	1			T6	22		T46	33		T98	9
values[9]	229	1			T14	15		T15	15		T149	3
minimum	17968	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T147	12		T110	1		T226	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T1	2		T6	13		T14	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T58	9		T44	11		T70	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T40	1		T170	13		T144	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T52	2		T70	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	6		T146	1		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T69	13		T156	14		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T8	1		T39	4		T98	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T58	3		T142	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T149	1		T156	12		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	19		T44	12		T95	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	11		T13	15		T98	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T10	2		T11	19		T59	40
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	1		T14	9		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T149	1		T200	1		T33	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T146	1		T47	13		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	12		T46	1		T98	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	10		T70	13		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T14	15		T15	8		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T195	1		T145	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T145	13		T278	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T226	11		T248	10		T162	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	14		T46	8		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T70	17		T40	2		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	1		T170	11		T144	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T52	20		T70	1		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	2		T146	10		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T69	12		T107	17		T108	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T39	1		T98	11		T195	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T58	4		T170	1		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T149	9		T17	1		T18	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	17		T95	9		T97	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	7		T98	13		T143	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T141	5		T96	22		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	10		T43	1		T31	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T149	3		T239	4		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T146	2		T108	1		T184	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	10		T46	10		T98	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	12		T70	12		T109	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T15	7		T149	2		T161	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T195	2		T279	14		T280	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T145	13		T278	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T275	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T22	2		T281	1		T282	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T276	6		T277	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T147	12		T110	1		T226	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	2		T6	13		T14	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T58	9		T44	11		T70	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	2		T170	13		T144	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T52	2		T70	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	6		T146	1		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T69	13		T156	14		T113	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	1		T39	4		T17	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T58	3		T142	1		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T98	15		T149	1		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T44	1		T95	13		T97	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	11		T13	15		T147	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	19		T44	11		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T14	9		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1675	1			T10	2		T11	19		T59	40
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	13		T40	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T6	12		T14	15		T15	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T46	10		T147	12		T70	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T275	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T282	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T277	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T226	11		T248	10		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	14		T46	8		T145	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T70	17		T224	6		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	2		T170	11		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T52	20		T70	1		T143	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	2		T146	10		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T69	12		T113	13		T195	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T39	1		T17	1		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T58	4		T107	17		T108	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T98	11		T149	9		T195	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T95	9		T97	10		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	7		T143	2		T218	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	17		T43	2		T34	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	10		T146	2		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T141	5		T96	22		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T108	1		T184	17		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	10		T15	7		T46	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T46	12		T70	12		T109	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T147	1		T110	1		T226	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	2		T6	15		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T58	1		T44	1		T70	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T40	2		T170	12		T144	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T52	22		T70	2		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	3		T146	11		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T69	13		T156	1		T107	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T8	1		T39	3		T98	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T58	5		T142	1		T170	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T149	10		T156	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	18		T44	2		T95	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	8		T13	1		T98	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T10	2		T11	3		T59	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	11		T14	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T149	4		T200	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T146	3		T47	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	11		T46	11		T98	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	13		T70	13		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T14	1		T15	8		T149	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T195	3		T145	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T145	14		T278	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	11		T226	7		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	12		T14	10		T46	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T58	8		T44	10		T70	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T170	12		T144	18		T43	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T167	10		T194	10		T31	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	5		T113	11		T253	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T69	12		T156	13		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	2		T98	14		T184	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T58	2		T219	8		T223	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T156	11		T17	1		T33	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	18		T44	10		T95	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	10		T13	14		T98	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T11	16		T59	37		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	8		T156	13		T31	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	7		T239	2		T53	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T47	12		T147	11		T184	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	11		T98	6		T99	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	9		T70	12		T109	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T14	14		T15	7		T283	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T223	3		T280	9		T284	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T145	12		T278	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T275	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T22	2		T281	1		T282	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T276	1		T277	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T147	1		T110	1		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	2		T6	15		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T58	1		T44	1		T70	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	4		T170	12		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T52	22		T70	2		T143	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	3		T146	11		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T69	13		T156	1		T113	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	1		T39	3		T17	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T58	5		T142	1		T107	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T98	12		T149	10		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	1		T95	10		T97	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	8		T13	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	18		T44	1		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	11		T14	1		T146	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T10	2		T11	3		T59	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T47	1		T40	1		T108	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T6	11		T14	1		T15	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T46	13		T147	1		T70	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T275	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T276	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	11		T226	7		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	12		T14	10		T46	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T58	8		T44	10		T70	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T170	12		T144	18		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T40	2		T167	10		T42	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	5		T113	11		T43	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T69	12		T156	13		T113	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T39	2		T17	1		T227	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T58	2		T108	11		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T98	14		T156	11		T184	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T95	12		T97	10		T29	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	10		T13	14		T147	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	18		T44	10		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	8		T98	12		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T11	16		T59	37		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T47	12		T184	13		T53	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	11		T14	14		T15	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	9		T147	11		T70	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16