Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23498

1

T2

10

T3

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3606

1

T1

2

T5

18

T6

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20996

1

T1

1

T2

10

T3

20

auto[1]

6108

1

T1

1

T5

18

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	260	1			T14	15		T15	15		T46	11
values[0]	6	1			T276	6		-	-		-	-
values[1]	733	1			T1	2		T6	27		T14	11
values[2]	643	1			T58	9		T44	11		T70	36
values[3]	1019	1			T6	8		T146	11		T39	4
values[4]	647	1			T8	1		T39	5		T69	25
values[5]	698	1			T58	7		T98	26		T149	10
values[6]	577	1			T5	18		T13	15		T44	1
values[7]	690	1			T12	11		T14	9		T15	36
values[8]	3029	1			T10	2		T11	19		T146	3
values[9]	881	1			T6	22		T46	22		T98	9
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	823	1			T1	2		T6	27		T14	11
values[1]	767	1			T58	9		T44	11		T70	36
values[2]	725	1			T6	8		T146	11		T39	4
values[3]	885	1			T8	1		T39	5		T98	26
values[4]	514	1			T58	7		T97	21		T149	10
values[5]	636	1			T5	18		T13	15		T15	36
values[6]	3127	1			T10	2		T11	19		T12	11
values[7]	556	1			T146	3		T47	13		T147	12
values[8]	847	1			T6	22		T14	15		T46	33
values[9]	150	1			T15	15		T112	7		T17	8
minimum	18074	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T147	12		T110	1		T226	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T1	2		T6	13		T14	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T58	9		T44	11		T70	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	1		T113	12		T170	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T52	2		T70	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	6		T146	1		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T69	13		T156	14		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T8	1		T39	4		T98	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T58	3		T97	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	1		T156	12		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	19		T44	12		T95	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	11		T13	15		T98	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T10	2		T11	19		T59	40
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T14	9		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T149	1		T200	1		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T146	1		T47	13		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	12		T14	15		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T46	10		T70	13		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T15	8		T161	1		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T112	1		T17	5		T223	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17794	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T46	9		T47	5		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T226	11		T248	10		T162	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	14		T40	1		T167	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T70	17		T40	2		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T40	1		T113	11		T170	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T52	20		T70	1		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	2		T146	10		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T69	12		T107	17		T195	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T39	1		T98	11		T195	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T58	4		T97	10		T108	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T149	9		T17	1		T18	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	17		T95	9		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	7		T98	13		T143	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T141	5		T96	22		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	10		T31	17		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T149	3		T224	4		T53	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T146	2		T108	1		T184	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	10		T46	10		T98	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	12		T70	12		T109	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T15	7		T161	12		T286	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T112	6		T17	3		T279	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	1		T41	1		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T46	8		T145	14		T153	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T14	15		T15	8		T46	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T108	1		T112	1		T223	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T276	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T147	12		T110	1		T226	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	2		T6	13		T14	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T58	9		T44	11		T70	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	2		T170	13		T144	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T52	2		T143	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T6	6		T146	1		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T69	13		T70	1		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	1		T39	4		T195	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T58	3		T142	1		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T98	15		T149	1		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T44	1		T95	13		T97	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	11		T13	15		T147	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	19		T44	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	1		T14	9		T98	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T10	2		T11	19		T59	40
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	1		T47	13		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	12		T98	7		T99	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	10		T147	12		T70	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T15	7		T46	10		T161	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T112	6		T231	12		T279	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T226	11		T248	10		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	14		T46	8		T145	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T70	17		T224	6		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	2		T170	11		T167	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T52	20		T143	7		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	2		T146	10		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T69	12		T70	1		T113	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	1		T195	4		T227	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T58	4		T107	17		T108	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T98	11		T149	9		T184	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T95	9		T97	10		T112	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	7		T218	12		T150	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	17		T143	13		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	10		T98	13		T143	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T141	5		T96	22		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	2		T108	1		T184	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	10		T98	2		T99	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T46	12		T70	12		T109	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T147	1		T110	1		T226	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	2		T6	15		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T58	1		T44	1		T70	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	2		T113	12		T170	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T52	22		T70	2		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	3		T146	11		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T69	13		T156	1		T107	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T8	1		T39	3		T98	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T58	5		T97	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T149	10		T156	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	18		T44	2		T95	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	8		T13	1		T98	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T10	2		T11	3		T59	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	11		T14	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T149	4		T200	1		T224	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T146	3		T47	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	11		T14	1		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T46	13		T70	13		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T15	8		T161	13		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T112	7		T17	6		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17947	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T46	9		T47	1		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T147	11		T226	7		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T6	12		T14	10		T144	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T58	8		T44	10		T70	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T113	11		T170	12		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T113	2		T167	10		T194	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	5		T253	17		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T69	12		T156	13		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T39	2		T98	14		T184	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T58	2		T97	10		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T156	11		T17	1		T18	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	18		T44	10		T95	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	10		T13	14		T98	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T11	16		T59	37		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	8		T156	13		T31	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T53	5		T159	13		T263	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T47	12		T147	11		T184	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	11		T14	14		T98	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T46	9		T70	12		T109	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T15	7		T283	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T17	2		T223	3		T284	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T287	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T46	8		T47	4		T145	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T14	1		T15	8		T46	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T108	1		T112	7		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T147	1		T110	1		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	2		T6	15		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T58	1		T44	1		T70	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	4		T170	12		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T52	22		T143	8		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	3		T146	11		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T69	13		T70	2		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	1		T39	3		T195	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T58	5		T142	1		T107	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T98	12		T149	10		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T44	1		T95	10		T97	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	8		T13	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T15	18		T44	1		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	11		T14	1		T98	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T10	2		T11	3		T59	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T146	3		T47	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	11		T98	3		T99	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T46	13		T147	1		T70	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T14	14		T15	7		T178	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T223	3		T284	21		T238	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T276	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T147	11		T226	7		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	12		T14	10		T46	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T58	8		T44	10		T70	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T170	12		T144	6		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	2		T167	10		T42	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	5		T113	11		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T69	12		T156	13		T113	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	2		T227	9		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T58	2		T108	11		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T98	14		T156	11		T184	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T95	12		T97	10		T226	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	10		T13	14		T147	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	18		T44	10		T29	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	8		T98	12		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T11	16		T59	37		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	12		T184	3		T53	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	11		T98	6		T99	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	9		T147	11		T70	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16