Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27104

1

T1

2

T2

10

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23560

1

T2

10

T3

20

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3544

1

T1

2

T6

49

T14

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20939

1

T2

10

T3

20

T4

20

auto[1]

6165

1

T1

2

T6

35

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23069

1

T1

2

T2

10

T3

20

auto[1]

4035

1

T5

7

T6

26

T9

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	372	1			T69	25		T40	1		T108	1
values[0]	14	1			T260	14		-	-		-	-
values[1]	607	1			T44	1		T70	27		T112	7
values[2]	2860	1			T10	2		T11	19		T12	11
values[3]	582	1			T5	18		T58	9		T39	5
values[4]	665	1			T1	1		T14	15		T15	15
values[5]	974	1			T6	27		T13	15		T52	5
values[6]	729	1			T6	8		T14	11		T98	9
values[7]	632	1			T1	1		T6	22		T8	1
values[8]	645	1			T146	11		T98	26		T149	10
values[9]	1103	1			T15	36		T146	3		T58	7
minimum	17921	1			T2	10		T3	20		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	608	1			T12	11		T70	25		T113	16
values[1]	2883	1			T5	18		T10	2		T11	19
values[2]	601	1			T39	5		T46	17		T47	5
values[3]	786	1			T1	1		T13	15		T14	15
values[4]	859	1			T6	35		T95	22		T99	18
values[5]	611	1			T1	1		T14	11		T98	9
values[6]	748	1			T6	22		T8	1		T14	9
values[7]	683	1			T52	17		T98	26		T149	10
values[8]	1097	1			T15	36		T146	3		T46	22
values[9]	143	1			T58	7		T47	13		T69	25
minimum	18085	1			T2	10		T3	20		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

4224

1

T5

10

T6

28

T11

16

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T113	3		T167	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T70	13		T17	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T5	11		T10	2		T11	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T147	12		T149	1		T156	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	4		T47	5		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T46	9		T98	13		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	15		T15	8		T58	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T14	15		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	6		T95	13		T99	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T6	13		T147	14		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	11		T98	7		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T142	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	1		T14	9		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	12		T53	1		T227	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T52	1		T98	15		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T143	1		T43	1		T229	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T146	1		T46	10		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T15	19		T97	11		T108	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T58	3		T47	13		T69	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T43	7		T228	7		T259	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17829	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T44	1		T195	1		T43	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	10		T113	13		T167	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T70	12		T17	3		T150	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T5	7		T141	5		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T149	3		T170	1		T171	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	1		T113	11		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T46	8		T98	13		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	7		T39	1		T52	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T112	4		T167	17		T218	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	2		T95	9		T99	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	14		T170	1		T184	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T98	2		T40	2		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T109	14		T150	9		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T146	10		T70	17		T108	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	10		T227	16		T153	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T52	16		T98	11		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T143	13		T43	1		T229	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T146	2		T46	12		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T15	17		T97	10		T108	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T58	4		T69	12		T288	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T43	2		T228	9		T182	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T70	1		T112	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T195	2		T43	2		T157	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T69	13		T40	1		T145	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T108	1		T33	8		T226	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T260	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T70	1		T112	1		T167	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T44	1		T70	13		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T10	2		T11	19		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T147	12		T149	1		T41	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	11		T58	9		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T98	13		T156	26		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	8		T39	3		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	1		T14	15		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	15		T52	1		T95	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T6	13		T147	14		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	6		T14	11		T98	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T185	1		T109	15		T31	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T14	9		T44	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T6	12		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T146	1		T98	15		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T143	1		T43	1		T229	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T146	1		T58	3		T46	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T15	19		T97	11		T108	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17777	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T69	12		T145	13		T55	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T226	8		T228	9		T18	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T70	1		T112	6		T167	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T70	12		T195	2		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T12	10		T141	5		T46	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T149	3		T170	1		T171	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	7		T39	1		T113	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T98	13		T40	1		T194	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	7		T39	1		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	8		T112	4		T167	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T52	4		T95	9		T99	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	14		T170	1		T184	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	2		T98	2		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T109	14		T31	17		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T70	17		T108	1		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	10		T227	16		T161	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T146	10		T98	11		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T143	13		T43	1		T229	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T146	2		T58	4		T46	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T15	17		T97	10		T108	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T41	1		T167	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	11		T113	14		T167	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T70	13		T17	6		T150	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T5	8		T10	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T147	1		T149	4		T156	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	3		T47	1		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	9		T98	14		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	1		T15	8		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T14	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	3		T95	10		T99	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T6	15		T147	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T98	3		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T142	1		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T14	1		T146	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	11		T53	1		T227	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T52	17		T98	12		T149	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T143	14		T43	2		T229	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T146	3		T46	13		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T15	18		T97	11		T108	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T58	5		T47	1		T69	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T43	6		T228	10		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17976	1			T2	10		T3	20		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T44	1		T195	3		T43	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T113	2		T167	10		T204	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T70	12		T17	2		T229	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T5	10		T11	16		T59	37
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T147	11		T156	24		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T39	2		T47	4		T113	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	8		T98	12		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	14		T15	7		T58	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	14		T147	11		T156	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	5		T95	12		T99	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	12		T147	13		T184	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	10		T98	6		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T109	14		T159	6		T220	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	8		T44	10		T70	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	11		T227	14		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T98	14		T144	6		T240	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T229	9		T223	18		T186	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	9		T145	12		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T15	18		T97	10		T108	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T58	2		T47	12		T69	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T43	3		T228	6		T259	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T33	14		T18	9		T289	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T43	2		T157	12		T202	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T69	13		T40	1		T145	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T108	1		T33	1		T226	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T260	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T70	2		T112	7		T167	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T44	1		T70	13		T195	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T10	2		T11	3		T12	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T147	1		T149	4		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	8		T58	1		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T98	14		T156	2		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	8		T39	4		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T14	1		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T52	5		T95	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T6	15		T147	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	3		T14	1		T98	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T185	1		T109	15		T31	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	1		T14	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T6	11		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T146	11		T98	12		T149	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T143	14		T43	2		T229	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T146	3		T58	5		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T15	18		T97	11		T108	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17921	1			T2	10		T3	20		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T69	12		T145	12		T55	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T33	7		T226	9		T228	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T260	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T167	10		T33	14		T204	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T70	12		T43	2		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T11	16		T59	37		T51	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T147	11		T41	1		T261	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	10		T58	8		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T98	12		T156	24		T194	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T15	7		T42	3		T253	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	14		T46	8		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	14		T95	12		T99	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	12		T147	13		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	5		T14	10		T98	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T109	14		T31	19		T159	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	8		T44	10		T70	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	11		T227	14		T248	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T98	14		T144	6		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T229	9		T223	18		T186	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T58	2		T46	9		T47	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T15	18		T97	10		T108	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22880

1

T1

2

T2

10

T3

20

auto[1]

auto[0]

4224

1

T5

10

T6

28

T11

16