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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.64 99.07 96.67 100.00 100.00 98.83 98.33 90.59


Total test records in report: 918
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T298 /workspace/coverage/default/39.adc_ctrl_filters_polled.3990132476 Jul 30 07:18:28 PM PDT 24 Jul 30 07:23:02 PM PDT 24 485160110725 ps
T795 /workspace/coverage/default/18.adc_ctrl_poweron_counter.1849370101 Jul 30 07:12:17 PM PDT 24 Jul 30 07:12:25 PM PDT 24 5143088634 ps
T796 /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.583979889 Jul 30 07:20:30 PM PDT 24 Jul 30 07:38:24 PM PDT 24 491047390576 ps
T74 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3363779567 Jul 30 07:21:40 PM PDT 24 Jul 30 07:21:42 PM PDT 24 509872959 ps
T75 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3634070605 Jul 30 07:21:45 PM PDT 24 Jul 30 07:21:48 PM PDT 24 818244740 ps
T76 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3118896871 Jul 30 07:21:09 PM PDT 24 Jul 30 07:21:10 PM PDT 24 633624418 ps
T65 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3034684579 Jul 30 07:21:07 PM PDT 24 Jul 30 07:21:35 PM PDT 24 23876685659 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3418208063 Jul 30 07:21:03 PM PDT 24 Jul 30 07:21:06 PM PDT 24 960830452 ps
T86 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2619065746 Jul 30 07:22:08 PM PDT 24 Jul 30 07:22:10 PM PDT 24 663592699 ps
T138 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4062577465 Jul 30 07:22:17 PM PDT 24 Jul 30 07:22:19 PM PDT 24 489773965 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.147216433 Jul 30 07:21:16 PM PDT 24 Jul 30 07:21:21 PM PDT 24 4516864416 ps
T87 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2874283973 Jul 30 07:21:28 PM PDT 24 Jul 30 07:21:30 PM PDT 24 440384120 ps
T126 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2455774428 Jul 30 07:21:39 PM PDT 24 Jul 30 07:21:41 PM PDT 24 876968423 ps
T797 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.92146924 Jul 30 07:22:20 PM PDT 24 Jul 30 07:22:21 PM PDT 24 393632679 ps
T798 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4289261308 Jul 30 07:22:11 PM PDT 24 Jul 30 07:22:12 PM PDT 24 441410984 ps
T799 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3728772884 Jul 30 07:21:44 PM PDT 24 Jul 30 07:21:45 PM PDT 24 501461974 ps
T66 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1463068791 Jul 30 07:21:03 PM PDT 24 Jul 30 07:21:15 PM PDT 24 27127428751 ps
T800 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2181376140 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 419309280 ps
T801 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1822542232 Jul 30 07:22:07 PM PDT 24 Jul 30 07:22:08 PM PDT 24 374125669 ps
T81 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3429144037 Jul 30 07:21:49 PM PDT 24 Jul 30 07:21:52 PM PDT 24 453031720 ps
T802 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1706981280 Jul 30 07:22:19 PM PDT 24 Jul 30 07:22:20 PM PDT 24 370107416 ps
T68 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1372665769 Jul 30 07:22:04 PM PDT 24 Jul 30 07:22:10 PM PDT 24 2228187867 ps
T127 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2218247185 Jul 30 07:22:04 PM PDT 24 Jul 30 07:22:06 PM PDT 24 349138100 ps
T803 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3360938423 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:29 PM PDT 24 502018877 ps
T804 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4157502039 Jul 30 07:22:28 PM PDT 24 Jul 30 07:22:29 PM PDT 24 329745466 ps
T72 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2870438739 Jul 30 07:21:32 PM PDT 24 Jul 30 07:21:39 PM PDT 24 4718193139 ps
T128 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2880491617 Jul 30 07:22:16 PM PDT 24 Jul 30 07:22:17 PM PDT 24 345112299 ps
T129 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1173508818 Jul 30 07:21:21 PM PDT 24 Jul 30 07:21:23 PM PDT 24 461404515 ps
T805 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.831613484 Jul 30 07:21:02 PM PDT 24 Jul 30 07:21:03 PM PDT 24 382691608 ps
T139 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1344296930 Jul 30 07:21:50 PM PDT 24 Jul 30 07:21:51 PM PDT 24 2781492742 ps
T83 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.165395554 Jul 30 07:22:04 PM PDT 24 Jul 30 07:22:06 PM PDT 24 415452096 ps
T806 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3465685574 Jul 30 07:22:23 PM PDT 24 Jul 30 07:22:24 PM PDT 24 480756749 ps
T807 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1809109476 Jul 30 07:21:56 PM PDT 24 Jul 30 07:21:57 PM PDT 24 319576360 ps
T808 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4094783893 Jul 30 07:22:23 PM PDT 24 Jul 30 07:22:24 PM PDT 24 536063960 ps
T809 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.686199083 Jul 30 07:22:23 PM PDT 24 Jul 30 07:22:24 PM PDT 24 469802576 ps
T810 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3242419610 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 313849087 ps
T811 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.290313184 Jul 30 07:21:40 PM PDT 24 Jul 30 07:21:41 PM PDT 24 431346414 ps
T67 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1762064107 Jul 30 07:21:24 PM PDT 24 Jul 30 07:21:27 PM PDT 24 4381918247 ps
T140 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.432092642 Jul 30 07:21:06 PM PDT 24 Jul 30 07:21:07 PM PDT 24 575312990 ps
T90 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3659491601 Jul 30 07:22:00 PM PDT 24 Jul 30 07:22:02 PM PDT 24 562438606 ps
T91 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1905159943 Jul 30 07:21:40 PM PDT 24 Jul 30 07:21:41 PM PDT 24 512172496 ps
T130 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1630469861 Jul 30 07:22:19 PM PDT 24 Jul 30 07:22:20 PM PDT 24 464254131 ps
T73 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1514732219 Jul 30 07:22:00 PM PDT 24 Jul 30 07:22:05 PM PDT 24 4676689931 ps
T131 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1864380032 Jul 30 07:21:39 PM PDT 24 Jul 30 07:21:41 PM PDT 24 397043323 ps
T80 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.313636372 Jul 30 07:21:29 PM PDT 24 Jul 30 07:21:33 PM PDT 24 4618120133 ps
T812 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3298404648 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 493302188 ps
T82 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3298273610 Jul 30 07:21:41 PM PDT 24 Jul 30 07:21:42 PM PDT 24 1133247300 ps
T813 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.241744675 Jul 30 07:22:30 PM PDT 24 Jul 30 07:22:31 PM PDT 24 329757979 ps
T85 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4108810523 Jul 30 07:21:55 PM PDT 24 Jul 30 07:21:58 PM PDT 24 559307157 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1175721979 Jul 30 07:22:17 PM PDT 24 Jul 30 07:22:18 PM PDT 24 478059941 ps
T815 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1864663727 Jul 30 07:22:23 PM PDT 24 Jul 30 07:22:25 PM PDT 24 403491989 ps
T816 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2785729239 Jul 30 07:22:22 PM PDT 24 Jul 30 07:22:23 PM PDT 24 386700456 ps
T817 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2607056486 Jul 30 07:22:04 PM PDT 24 Jul 30 07:22:06 PM PDT 24 527123223 ps
T132 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2056014139 Jul 30 07:21:38 PM PDT 24 Jul 30 07:21:40 PM PDT 24 353969111 ps
T133 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.438367825 Jul 30 07:21:49 PM PDT 24 Jul 30 07:21:51 PM PDT 24 476262529 ps
T88 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3349574972 Jul 30 07:21:21 PM PDT 24 Jul 30 07:21:24 PM PDT 24 560720039 ps
T89 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4032202743 Jul 30 07:21:16 PM PDT 24 Jul 30 07:21:19 PM PDT 24 575999264 ps
T818 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3340343006 Jul 30 07:21:55 PM PDT 24 Jul 30 07:21:58 PM PDT 24 2266614804 ps
T77 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.222908487 Jul 30 07:20:55 PM PDT 24 Jul 30 07:21:17 PM PDT 24 8561302524 ps
T819 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.663177804 Jul 30 07:21:57 PM PDT 24 Jul 30 07:21:59 PM PDT 24 410327308 ps
T820 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2068774670 Jul 30 07:21:39 PM PDT 24 Jul 30 07:21:55 PM PDT 24 4055864607 ps
T821 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4051278648 Jul 30 07:22:21 PM PDT 24 Jul 30 07:22:22 PM PDT 24 553633688 ps
T78 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3155681548 Jul 30 07:22:09 PM PDT 24 Jul 30 07:22:32 PM PDT 24 9021380477 ps
T822 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2669956913 Jul 30 07:22:22 PM PDT 24 Jul 30 07:22:23 PM PDT 24 549591632 ps
T823 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1877733558 Jul 30 07:21:10 PM PDT 24 Jul 30 07:21:27 PM PDT 24 4227318246 ps
T824 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3441887584 Jul 30 07:22:20 PM PDT 24 Jul 30 07:22:21 PM PDT 24 449856814 ps
T825 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.612415460 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 469482899 ps
T826 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2601826247 Jul 30 07:21:39 PM PDT 24 Jul 30 07:21:41 PM PDT 24 998191528 ps
T827 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3464042721 Jul 30 07:22:06 PM PDT 24 Jul 30 07:22:09 PM PDT 24 2585882206 ps
T828 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2188538892 Jul 30 07:21:48 PM PDT 24 Jul 30 07:21:50 PM PDT 24 416361285 ps
T829 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.492727410 Jul 30 07:21:56 PM PDT 24 Jul 30 07:22:00 PM PDT 24 4590837827 ps
T321 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1393191838 Jul 30 07:21:41 PM PDT 24 Jul 30 07:22:00 PM PDT 24 8698424679 ps
T830 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3588613382 Jul 30 07:22:19 PM PDT 24 Jul 30 07:22:27 PM PDT 24 5274189539 ps
T322 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4181147182 Jul 30 07:21:40 PM PDT 24 Jul 30 07:21:46 PM PDT 24 4247608427 ps
T831 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1889405314 Jul 30 07:22:32 PM PDT 24 Jul 30 07:22:33 PM PDT 24 443654503 ps
T832 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3095658529 Jul 30 07:22:12 PM PDT 24 Jul 30 07:22:14 PM PDT 24 406734412 ps
T134 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3855390880 Jul 30 07:22:13 PM PDT 24 Jul 30 07:22:14 PM PDT 24 548601866 ps
T135 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.176306134 Jul 30 07:21:10 PM PDT 24 Jul 30 07:21:13 PM PDT 24 1361203236 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3244477526 Jul 30 07:21:43 PM PDT 24 Jul 30 07:21:50 PM PDT 24 4247816937 ps
T834 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4282262753 Jul 30 07:22:07 PM PDT 24 Jul 30 07:22:09 PM PDT 24 343165874 ps
T835 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2664554376 Jul 30 07:22:16 PM PDT 24 Jul 30 07:22:24 PM PDT 24 4034919237 ps
T836 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3928602820 Jul 30 07:22:12 PM PDT 24 Jul 30 07:22:19 PM PDT 24 4490640198 ps
T837 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.20189911 Jul 30 07:20:57 PM PDT 24 Jul 30 07:20:58 PM PDT 24 760981485 ps
T136 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3244747292 Jul 30 07:21:15 PM PDT 24 Jul 30 07:21:16 PM PDT 24 672695560 ps
T838 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3181970908 Jul 30 07:21:37 PM PDT 24 Jul 30 07:21:39 PM PDT 24 578560540 ps
T839 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3825699310 Jul 30 07:21:52 PM PDT 24 Jul 30 07:21:53 PM PDT 24 370988186 ps
T840 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2765877312 Jul 30 07:22:23 PM PDT 24 Jul 30 07:22:25 PM PDT 24 479005364 ps
T841 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.947165308 Jul 30 07:21:41 PM PDT 24 Jul 30 07:21:43 PM PDT 24 2591771714 ps
T842 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.642634144 Jul 30 07:22:26 PM PDT 24 Jul 30 07:22:27 PM PDT 24 303595641 ps
T843 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1815482119 Jul 30 07:22:33 PM PDT 24 Jul 30 07:22:34 PM PDT 24 563682321 ps
T844 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3211800187 Jul 30 07:22:00 PM PDT 24 Jul 30 07:22:02 PM PDT 24 346134964 ps
T845 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2879751581 Jul 30 07:21:03 PM PDT 24 Jul 30 07:21:07 PM PDT 24 4685384597 ps
T846 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1303551994 Jul 30 07:22:15 PM PDT 24 Jul 30 07:22:17 PM PDT 24 684923492 ps
T847 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2447910227 Jul 30 07:22:06 PM PDT 24 Jul 30 07:22:08 PM PDT 24 665046200 ps
T848 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4080020434 Jul 30 07:22:01 PM PDT 24 Jul 30 07:22:03 PM PDT 24 366502686 ps
T849 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4197036900 Jul 30 07:21:12 PM PDT 24 Jul 30 07:21:13 PM PDT 24 339917773 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.927113798 Jul 30 07:21:01 PM PDT 24 Jul 30 07:21:09 PM PDT 24 9013198208 ps
T851 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3627363170 Jul 30 07:22:16 PM PDT 24 Jul 30 07:22:21 PM PDT 24 5053288982 ps
T852 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3975805406 Jul 30 07:22:17 PM PDT 24 Jul 30 07:22:30 PM PDT 24 5085259977 ps
T853 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2250888993 Jul 30 07:21:17 PM PDT 24 Jul 30 07:21:20 PM PDT 24 557284076 ps
T854 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3010215106 Jul 30 07:22:22 PM PDT 24 Jul 30 07:22:23 PM PDT 24 488114963 ps
T137 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4117770961 Jul 30 07:21:04 PM PDT 24 Jul 30 07:21:09 PM PDT 24 954453940 ps
T855 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2920353283 Jul 30 07:22:12 PM PDT 24 Jul 30 07:22:14 PM PDT 24 545095473 ps
T856 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3070937693 Jul 30 07:21:38 PM PDT 24 Jul 30 07:21:48 PM PDT 24 14680433220 ps
T857 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3792854429 Jul 30 07:22:16 PM PDT 24 Jul 30 07:22:33 PM PDT 24 4337844904 ps
T858 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.259019924 Jul 30 07:21:51 PM PDT 24 Jul 30 07:21:53 PM PDT 24 431507310 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3171145334 Jul 30 07:21:52 PM PDT 24 Jul 30 07:21:53 PM PDT 24 436787973 ps
T860 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2727849760 Jul 30 07:21:47 PM PDT 24 Jul 30 07:21:58 PM PDT 24 8057274664 ps
T861 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4159152988 Jul 30 07:21:24 PM PDT 24 Jul 30 07:21:28 PM PDT 24 1191781624 ps
T862 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.713112604 Jul 30 07:21:43 PM PDT 24 Jul 30 07:21:55 PM PDT 24 4816862207 ps
T863 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.596890857 Jul 30 07:21:12 PM PDT 24 Jul 30 07:21:32 PM PDT 24 26496895002 ps
T864 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3192798708 Jul 30 07:21:22 PM PDT 24 Jul 30 07:21:29 PM PDT 24 8474187804 ps
T323 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3390204546 Jul 30 07:21:55 PM PDT 24 Jul 30 07:22:16 PM PDT 24 8192668811 ps
T865 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1409121874 Jul 30 07:21:46 PM PDT 24 Jul 30 07:21:48 PM PDT 24 348539946 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1313737044 Jul 30 07:21:38 PM PDT 24 Jul 30 07:21:40 PM PDT 24 4137101251 ps
T867 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1927301208 Jul 30 07:20:55 PM PDT 24 Jul 30 07:20:56 PM PDT 24 498835791 ps
T868 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3891151255 Jul 30 07:22:17 PM PDT 24 Jul 30 07:22:19 PM PDT 24 491311092 ps
T869 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2086929436 Jul 30 07:21:49 PM PDT 24 Jul 30 07:21:50 PM PDT 24 403556382 ps
T870 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2612701064 Jul 30 07:20:55 PM PDT 24 Jul 30 07:20:58 PM PDT 24 433053541 ps
T871 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.141400151 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 481478998 ps
T872 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.926734412 Jul 30 07:21:21 PM PDT 24 Jul 30 07:21:23 PM PDT 24 287333833 ps
T873 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.891865209 Jul 30 07:21:52 PM PDT 24 Jul 30 07:21:54 PM PDT 24 491164568 ps
T874 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3079464653 Jul 30 07:21:27 PM PDT 24 Jul 30 07:21:37 PM PDT 24 4316333669 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.196454389 Jul 30 07:22:20 PM PDT 24 Jul 30 07:22:21 PM PDT 24 430854234 ps
T876 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3515775281 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 361618361 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.346096809 Jul 30 07:21:43 PM PDT 24 Jul 30 07:21:44 PM PDT 24 532660736 ps
T878 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.434013747 Jul 30 07:21:13 PM PDT 24 Jul 30 07:21:15 PM PDT 24 439103467 ps
T879 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1032062109 Jul 30 07:21:28 PM PDT 24 Jul 30 07:21:30 PM PDT 24 429993512 ps
T880 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.655931163 Jul 30 07:22:17 PM PDT 24 Jul 30 07:22:18 PM PDT 24 551499181 ps
T881 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.300829035 Jul 30 07:21:02 PM PDT 24 Jul 30 07:21:04 PM PDT 24 494201410 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3448776923 Jul 30 07:21:04 PM PDT 24 Jul 30 07:21:05 PM PDT 24 565105663 ps
T883 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3294043390 Jul 30 07:21:57 PM PDT 24 Jul 30 07:21:59 PM PDT 24 416718930 ps
T884 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1226171647 Jul 30 07:21:21 PM PDT 24 Jul 30 07:21:23 PM PDT 24 651639648 ps
T885 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2723793955 Jul 30 07:20:58 PM PDT 24 Jul 30 07:21:00 PM PDT 24 495747226 ps
T886 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1925449378 Jul 30 07:21:38 PM PDT 24 Jul 30 07:21:41 PM PDT 24 569149072 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3995495917 Jul 30 07:22:00 PM PDT 24 Jul 30 07:22:05 PM PDT 24 1841645911 ps
T888 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1364571587 Jul 30 07:21:56 PM PDT 24 Jul 30 07:21:58 PM PDT 24 513172795 ps
T889 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.477015707 Jul 30 07:21:44 PM PDT 24 Jul 30 07:21:45 PM PDT 24 461848404 ps
T890 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1384933644 Jul 30 07:21:37 PM PDT 24 Jul 30 07:21:40 PM PDT 24 950899376 ps
T92 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3835376744 Jul 30 07:22:04 PM PDT 24 Jul 30 07:22:08 PM PDT 24 4322834840 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.450456069 Jul 30 07:21:26 PM PDT 24 Jul 30 07:23:16 PM PDT 24 50980241112 ps
T892 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2669143774 Jul 30 07:21:52 PM PDT 24 Jul 30 07:22:03 PM PDT 24 4413878444 ps
T893 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1830266560 Jul 30 07:22:32 PM PDT 24 Jul 30 07:22:34 PM PDT 24 469833662 ps
T894 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1999259134 Jul 30 07:21:49 PM PDT 24 Jul 30 07:21:52 PM PDT 24 2314808958 ps
T895 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3349300994 Jul 30 07:21:47 PM PDT 24 Jul 30 07:21:48 PM PDT 24 452843002 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3330034935 Jul 30 07:22:17 PM PDT 24 Jul 30 07:22:19 PM PDT 24 485101519 ps
T897 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2866746650 Jul 30 07:22:16 PM PDT 24 Jul 30 07:22:17 PM PDT 24 398168072 ps
T898 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4031658153 Jul 30 07:22:15 PM PDT 24 Jul 30 07:22:26 PM PDT 24 4691105762 ps
T899 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2625787604 Jul 30 07:21:55 PM PDT 24 Jul 30 07:22:01 PM PDT 24 2063710591 ps
T900 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3258954927 Jul 30 07:21:58 PM PDT 24 Jul 30 07:22:00 PM PDT 24 386124009 ps
T901 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1765155230 Jul 30 07:22:19 PM PDT 24 Jul 30 07:22:23 PM PDT 24 4218325377 ps
T902 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.366154377 Jul 30 07:22:15 PM PDT 24 Jul 30 07:22:29 PM PDT 24 4046285637 ps
T903 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2859265857 Jul 30 07:22:14 PM PDT 24 Jul 30 07:22:15 PM PDT 24 674596695 ps
T904 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1232509636 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 312892929 ps
T905 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2745188027 Jul 30 07:22:27 PM PDT 24 Jul 30 07:22:28 PM PDT 24 510655757 ps
T906 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3374570014 Jul 30 07:22:19 PM PDT 24 Jul 30 07:22:22 PM PDT 24 1024731699 ps
T907 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.148784662 Jul 30 07:22:31 PM PDT 24 Jul 30 07:22:32 PM PDT 24 327569491 ps
T908 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3147323055 Jul 30 07:21:58 PM PDT 24 Jul 30 07:22:01 PM PDT 24 465929166 ps
T909 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1398271430 Jul 30 07:21:40 PM PDT 24 Jul 30 07:21:41 PM PDT 24 444682951 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2849319692 Jul 30 07:21:28 PM PDT 24 Jul 30 07:21:29 PM PDT 24 550899789 ps
T911 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3235917369 Jul 30 07:22:26 PM PDT 24 Jul 30 07:22:27 PM PDT 24 331460835 ps
T912 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1636812782 Jul 30 07:21:58 PM PDT 24 Jul 30 07:22:00 PM PDT 24 457444332 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1034538944 Jul 30 07:21:23 PM PDT 24 Jul 30 07:21:24 PM PDT 24 903012998 ps
T914 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.146702695 Jul 30 07:22:32 PM PDT 24 Jul 30 07:22:34 PM PDT 24 518143581 ps
T915 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1072656304 Jul 30 07:22:06 PM PDT 24 Jul 30 07:22:07 PM PDT 24 472218681 ps
T916 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.508591577 Jul 30 07:22:26 PM PDT 24 Jul 30 07:22:28 PM PDT 24 294496776 ps
T917 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.814771299 Jul 30 07:22:18 PM PDT 24 Jul 30 07:22:19 PM PDT 24 689617305 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2365150521 Jul 30 07:21:45 PM PDT 24 Jul 30 07:21:46 PM PDT 24 391410122 ps

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1758776273
Short name T6
Test name
Test status
Simulation time 525199094000 ps
CPU time 1196.61 seconds
Started Jul 30 07:10:32 PM PDT 24
Finished Jul 30 07:30:29 PM PDT 24
Peak memory 201488 kb
Host smart-3a2f99ce-0eeb-4e66-a999-01b19573bbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758776273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1758776273
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3360031862
Short name T9
Test name
Test status
Simulation time 187971045326 ps
CPU time 601.02 seconds
Started Jul 30 07:08:21 PM PDT 24
Finished Jul 30 07:18:23 PM PDT 24
Peak memory 201812 kb
Host smart-df69159c-ed6b-4908-a80b-de4c48e28183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360031862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3360031862
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2302638180
Short name T40
Test name
Test status
Simulation time 4177897039330 ps
CPU time 756.13 seconds
Started Jul 30 07:09:45 PM PDT 24
Finished Jul 30 07:22:22 PM PDT 24
Peak memory 218320 kb
Host smart-b6bfab6e-01bd-4fd0-9195-577091a91613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302638180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2302638180
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3704802633
Short name T18
Test name
Test status
Simulation time 1056222998927 ps
CPU time 534.05 seconds
Started Jul 30 07:11:07 PM PDT 24
Finished Jul 30 07:20:01 PM PDT 24
Peak memory 210272 kb
Host smart-2de12d7d-b1f8-41e9-af17-d817bb14b0ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704802633 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3704802633
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2455538571
Short name T39
Test name
Test status
Simulation time 61898604770 ps
CPU time 157.69 seconds
Started Jul 30 07:06:55 PM PDT 24
Finished Jul 30 07:09:33 PM PDT 24
Peak memory 210224 kb
Host smart-da07e6ef-4ab3-45b0-93e8-d3e42d8acb9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455538571 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2455538571
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1827618884
Short name T43
Test name
Test status
Simulation time 655219958324 ps
CPU time 248.89 seconds
Started Jul 30 07:06:33 PM PDT 24
Finished Jul 30 07:10:42 PM PDT 24
Peak memory 217364 kb
Host smart-8427cd52-b5d0-4474-818d-bbfc975ae0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827618884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1827618884
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1464111003
Short name T46
Test name
Test status
Simulation time 620526582804 ps
CPU time 1075.7 seconds
Started Jul 30 07:12:21 PM PDT 24
Finished Jul 30 07:30:17 PM PDT 24
Peak memory 201712 kb
Host smart-20e5693b-9d6a-40bc-ab71-2afbf311e015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464111003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1464111003
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.639900956
Short name T144
Test name
Test status
Simulation time 535620373783 ps
CPU time 199.21 seconds
Started Jul 30 07:11:41 PM PDT 24
Finished Jul 30 07:15:00 PM PDT 24
Peak memory 201440 kb
Host smart-06353d34-9e3b-40ca-8289-91f672c8ed53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639900956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.639900956
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3884193873
Short name T15
Test name
Test status
Simulation time 345233105932 ps
CPU time 202.53 seconds
Started Jul 30 07:07:37 PM PDT 24
Finished Jul 30 07:10:59 PM PDT 24
Peak memory 201552 kb
Host smart-c6f1355a-dbbc-447b-8492-9582b32aa22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884193873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3884193873
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3405857202
Short name T147
Test name
Test status
Simulation time 539108950500 ps
CPU time 560.83 seconds
Started Jul 30 07:10:23 PM PDT 24
Finished Jul 30 07:19:44 PM PDT 24
Peak memory 201440 kb
Host smart-f0d5e055-f52a-4e01-962a-4d8581e553f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405857202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3405857202
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4199157888
Short name T159
Test name
Test status
Simulation time 529872205719 ps
CPU time 1220.63 seconds
Started Jul 30 07:05:56 PM PDT 24
Finished Jul 30 07:26:17 PM PDT 24
Peak memory 201420 kb
Host smart-83068904-9b52-4ee2-a987-12a3adc11b04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199157888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4199157888
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2115849940
Short name T79
Test name
Test status
Simulation time 7728960725 ps
CPU time 14.64 seconds
Started Jul 30 07:06:36 PM PDT 24
Finished Jul 30 07:06:51 PM PDT 24
Peak memory 218256 kb
Host smart-6346333f-d94f-4f97-93f2-32a4aa861678
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115849940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2115849940
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2052716565
Short name T113
Test name
Test status
Simulation time 520187649811 ps
CPU time 1076.57 seconds
Started Jul 30 07:06:29 PM PDT 24
Finished Jul 30 07:24:26 PM PDT 24
Peak memory 201504 kb
Host smart-3967150c-e86c-42a9-9c50-501bc56631ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052716565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2052716565
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3369063940
Short name T98
Test name
Test status
Simulation time 566015124978 ps
CPU time 348.09 seconds
Started Jul 30 07:17:57 PM PDT 24
Finished Jul 30 07:23:45 PM PDT 24
Peak memory 201448 kb
Host smart-fd0f01a3-6089-493f-bcb0-2d90a574703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369063940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3369063940
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2218247185
Short name T127
Test name
Test status
Simulation time 349138100 ps
CPU time 1.61 seconds
Started Jul 30 07:22:04 PM PDT 24
Finished Jul 30 07:22:06 PM PDT 24
Peak memory 201336 kb
Host smart-2e910168-456c-4ab5-a5e8-a69b95c9137a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218247185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2218247185
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3833832815
Short name T108
Test name
Test status
Simulation time 523783744664 ps
CPU time 75.88 seconds
Started Jul 30 07:19:03 PM PDT 24
Finished Jul 30 07:20:19 PM PDT 24
Peak memory 201452 kb
Host smart-af0bf569-47eb-4e5c-9522-cd98c636df05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833832815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3833832815
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3634070605
Short name T75
Test name
Test status
Simulation time 818244740 ps
CPU time 2.81 seconds
Started Jul 30 07:21:45 PM PDT 24
Finished Jul 30 07:21:48 PM PDT 24
Peak memory 201656 kb
Host smart-cf09802e-48f9-43e0-9481-9e6d10d0f3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634070605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3634070605
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.161150018
Short name T184
Test name
Test status
Simulation time 513742651664 ps
CPU time 365.33 seconds
Started Jul 30 07:11:26 PM PDT 24
Finished Jul 30 07:17:31 PM PDT 24
Peak memory 201416 kb
Host smart-51333fed-e779-4ef5-a309-ef3ec75fe0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161150018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.161150018
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3535827149
Short name T70
Test name
Test status
Simulation time 528954602358 ps
CPU time 274.03 seconds
Started Jul 30 07:18:48 PM PDT 24
Finished Jul 30 07:23:22 PM PDT 24
Peak memory 201432 kb
Host smart-0fc26584-1cc0-4597-9a7a-8aad68d8b432
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535827149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3535827149
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2408862376
Short name T11
Test name
Test status
Simulation time 611463483251 ps
CPU time 1419.35 seconds
Started Jul 30 07:19:30 PM PDT 24
Finished Jul 30 07:43:09 PM PDT 24
Peak memory 201488 kb
Host smart-44ff34fc-eb3e-4539-9aac-1d0408ed39b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408862376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2408862376
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3795420988
Short name T31
Test name
Test status
Simulation time 522648335755 ps
CPU time 110.21 seconds
Started Jul 30 07:18:07 PM PDT 24
Finished Jul 30 07:19:57 PM PDT 24
Peak memory 201576 kb
Host smart-006a8ec0-8f2b-4363-9ff1-2bca14f9606f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795420988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3795420988
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2653792000
Short name T226
Test name
Test status
Simulation time 514428142064 ps
CPU time 623.1 seconds
Started Jul 30 07:18:21 PM PDT 24
Finished Jul 30 07:28:44 PM PDT 24
Peak memory 201436 kb
Host smart-33d56944-5d4f-43e1-bd43-ca66c75ce926
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653792000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2653792000
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3361772775
Short name T223
Test name
Test status
Simulation time 332943119540 ps
CPU time 389.09 seconds
Started Jul 30 07:20:34 PM PDT 24
Finished Jul 30 07:27:03 PM PDT 24
Peak memory 201464 kb
Host smart-eff57791-99f6-48c9-8b35-9ebb4f38b6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361772775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3361772775
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3496401252
Short name T238
Test name
Test status
Simulation time 640200710957 ps
CPU time 395.04 seconds
Started Jul 30 07:15:49 PM PDT 24
Finished Jul 30 07:22:24 PM PDT 24
Peak memory 201460 kb
Host smart-a8a5e45c-f02e-4d13-b077-34350703c6b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496401252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3496401252
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.222908487
Short name T77
Test name
Test status
Simulation time 8561302524 ps
CPU time 22.17 seconds
Started Jul 30 07:20:55 PM PDT 24
Finished Jul 30 07:21:17 PM PDT 24
Peak memory 201604 kb
Host smart-d9f97d8a-2412-4288-8db9-50b02b0470a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222908487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.222908487
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2052776052
Short name T257
Test name
Test status
Simulation time 342120117845 ps
CPU time 197.6 seconds
Started Jul 30 07:07:17 PM PDT 24
Finished Jul 30 07:10:35 PM PDT 24
Peak memory 201452 kb
Host smart-78a15fbc-09fe-4d1f-b493-1e5fdad39daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052776052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2052776052
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.166518834
Short name T276
Test name
Test status
Simulation time 173432356667 ps
CPU time 378.49 seconds
Started Jul 30 07:16:46 PM PDT 24
Finished Jul 30 07:23:04 PM PDT 24
Peak memory 201432 kb
Host smart-0fc4399d-e03b-42e5-9b8e-8c12bd49d2e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166518834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.166518834
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3602620909
Short name T363
Test name
Test status
Simulation time 456493724 ps
CPU time 1.64 seconds
Started Jul 30 07:11:30 PM PDT 24
Finished Jul 30 07:11:31 PM PDT 24
Peak memory 201240 kb
Host smart-8a7b97a0-198b-4816-b5a1-f38f1f62efe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602620909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3602620909
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4187881728
Short name T58
Test name
Test status
Simulation time 322730268276 ps
CPU time 737.68 seconds
Started Jul 30 07:06:32 PM PDT 24
Finished Jul 30 07:18:50 PM PDT 24
Peak memory 201508 kb
Host smart-2c83e5f2-6b15-4f36-9de3-1434a0bfb102
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187881728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4187881728
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2799555493
Short name T155
Test name
Test status
Simulation time 542617713961 ps
CPU time 107.22 seconds
Started Jul 30 07:17:03 PM PDT 24
Finished Jul 30 07:18:50 PM PDT 24
Peak memory 201480 kb
Host smart-f84c2afe-a12d-429a-8371-a000a95b70b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799555493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2799555493
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1682960203
Short name T55
Test name
Test status
Simulation time 343801755303 ps
CPU time 73.31 seconds
Started Jul 30 07:20:56 PM PDT 24
Finished Jul 30 07:22:10 PM PDT 24
Peak memory 210216 kb
Host smart-49a768b6-1f57-4b53-b401-322f00eeb5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682960203 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1682960203
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2064002527
Short name T231
Test name
Test status
Simulation time 497405866683 ps
CPU time 333.43 seconds
Started Jul 30 07:20:07 PM PDT 24
Finished Jul 30 07:25:40 PM PDT 24
Peak memory 201444 kb
Host smart-96d2df76-849a-4953-9ef7-4213c286d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064002527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2064002527
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1013138861
Short name T112
Test name
Test status
Simulation time 501114769317 ps
CPU time 1196.21 seconds
Started Jul 30 07:06:21 PM PDT 24
Finished Jul 30 07:26:17 PM PDT 24
Peak memory 201436 kb
Host smart-c0830436-3d8c-404b-97d8-2794580ce928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013138861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1013138861
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3170889339
Short name T216
Test name
Test status
Simulation time 160922451848 ps
CPU time 73.18 seconds
Started Jul 30 07:17:40 PM PDT 24
Finished Jul 30 07:18:53 PM PDT 24
Peak memory 201488 kb
Host smart-c405c88b-5be5-4cec-a54f-d9cc5a5bbaee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170889339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3170889339
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1431314993
Short name T219
Test name
Test status
Simulation time 249100323719 ps
CPU time 131.22 seconds
Started Jul 30 07:09:33 PM PDT 24
Finished Jul 30 07:11:44 PM PDT 24
Peak memory 201420 kb
Host smart-c381f0ea-92d5-4b98-b514-cfbce42bb3cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431314993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1431314993
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.327430554
Short name T208
Test name
Test status
Simulation time 627994196145 ps
CPU time 465.66 seconds
Started Jul 30 07:18:00 PM PDT 24
Finished Jul 30 07:25:46 PM PDT 24
Peak memory 201832 kb
Host smart-dfe98c5e-c5f2-4db2-a572-34b132b5bc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327430554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
327430554
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3095658529
Short name T832
Test name
Test status
Simulation time 406734412 ps
CPU time 2.14 seconds
Started Jul 30 07:22:12 PM PDT 24
Finished Jul 30 07:22:14 PM PDT 24
Peak memory 201612 kb
Host smart-3338091a-d1fc-4c54-9431-65edf1a47c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095658529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3095658529
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1373175464
Short name T252
Test name
Test status
Simulation time 377989219307 ps
CPU time 66.67 seconds
Started Jul 30 07:12:35 PM PDT 24
Finished Jul 30 07:13:42 PM PDT 24
Peak memory 201448 kb
Host smart-884e524a-2c6b-45f3-b057-4a81c2aa053a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373175464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1373175464
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.726622896
Short name T275
Test name
Test status
Simulation time 612856009196 ps
CPU time 1593.13 seconds
Started Jul 30 07:15:42 PM PDT 24
Finished Jul 30 07:42:15 PM PDT 24
Peak memory 218268 kb
Host smart-379afdfb-377a-4e9b-ac1e-eb487c3cf929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726622896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
726622896
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4250309419
Short name T193
Test name
Test status
Simulation time 522968009184 ps
CPU time 301.72 seconds
Started Jul 30 07:06:50 PM PDT 24
Finished Jul 30 07:11:52 PM PDT 24
Peak memory 201460 kb
Host smart-5f81290a-5980-4623-b1ad-0ae4bec3fa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250309419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4250309419
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.4184419975
Short name T273
Test name
Test status
Simulation time 546970148548 ps
CPU time 1331.24 seconds
Started Jul 30 07:10:55 PM PDT 24
Finished Jul 30 07:33:07 PM PDT 24
Peak memory 201468 kb
Host smart-0e87708d-7788-484d-adc9-68ad777ade4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184419975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.4184419975
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.514723356
Short name T110
Test name
Test status
Simulation time 499524884745 ps
CPU time 269.19 seconds
Started Jul 30 07:12:09 PM PDT 24
Finished Jul 30 07:16:38 PM PDT 24
Peak memory 201448 kb
Host smart-fad43c12-4708-4f4f-8ed7-9cf52b4f9534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514723356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.514723356
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2792169608
Short name T306
Test name
Test status
Simulation time 496552972364 ps
CPU time 102.04 seconds
Started Jul 30 07:12:56 PM PDT 24
Finished Jul 30 07:14:38 PM PDT 24
Peak memory 201444 kb
Host smart-b5aac0d0-67f3-4240-bf0b-53dcb37198c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792169608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2792169608
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2691698766
Short name T195
Test name
Test status
Simulation time 496199024690 ps
CPU time 1091.97 seconds
Started Jul 30 07:18:03 PM PDT 24
Finished Jul 30 07:36:15 PM PDT 24
Peak memory 201444 kb
Host smart-2586c9f3-04a8-4923-894b-9a2da62714eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691698766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2691698766
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.935707543
Short name T202
Test name
Test status
Simulation time 353814641133 ps
CPU time 750.92 seconds
Started Jul 30 07:19:14 PM PDT 24
Finished Jul 30 07:31:45 PM PDT 24
Peak memory 201876 kb
Host smart-db2b1f26-a62b-4fa8-9510-cf5863ddcdf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935707543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
935707543
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3711660498
Short name T236
Test name
Test status
Simulation time 63906030578 ps
CPU time 59.09 seconds
Started Jul 30 07:19:22 PM PDT 24
Finished Jul 30 07:20:21 PM PDT 24
Peak memory 210208 kb
Host smart-a38b4d99-bafc-46b7-af43-55ee9d180e91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711660498 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3711660498
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4028170008
Short name T212
Test name
Test status
Simulation time 295039570839 ps
CPU time 1007.21 seconds
Started Jul 30 07:19:37 PM PDT 24
Finished Jul 30 07:36:24 PM PDT 24
Peak memory 213100 kb
Host smart-995c449a-4fb6-4d6a-aa77-2557bec5cb3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028170008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4028170008
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.795393375
Short name T260
Test name
Test status
Simulation time 182836514879 ps
CPU time 98.67 seconds
Started Jul 30 07:11:19 PM PDT 24
Finished Jul 30 07:12:58 PM PDT 24
Peak memory 201460 kb
Host smart-403c3b86-b6e4-4b09-bb44-eefb86be8b93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795393375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.795393375
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2817128409
Short name T278
Test name
Test status
Simulation time 194929300879 ps
CPU time 450.37 seconds
Started Jul 30 07:06:55 PM PDT 24
Finished Jul 30 07:14:25 PM PDT 24
Peak memory 201452 kb
Host smart-fc88d484-b787-4c83-89ae-a61b31871daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817128409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2817128409
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1120550611
Short name T299
Test name
Test status
Simulation time 332784936168 ps
CPU time 191.47 seconds
Started Jul 30 07:13:29 PM PDT 24
Finished Jul 30 07:16:41 PM PDT 24
Peak memory 201428 kb
Host smart-c677afda-0b92-4014-b166-e331e8152391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120550611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1120550611
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3812878020
Short name T122
Test name
Test status
Simulation time 489399580742 ps
CPU time 264.68 seconds
Started Jul 30 07:14:13 PM PDT 24
Finished Jul 30 07:18:38 PM PDT 24
Peak memory 201428 kb
Host smart-20258c8f-676a-456a-bcd9-686e34286d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812878020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3812878020
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4115912195
Short name T54
Test name
Test status
Simulation time 143049273754 ps
CPU time 85.54 seconds
Started Jul 30 07:15:53 PM PDT 24
Finished Jul 30 07:17:18 PM PDT 24
Peak memory 209744 kb
Host smart-7504c1fa-1bf1-46c7-a210-c79c20989d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115912195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4115912195
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3990132476
Short name T298
Test name
Test status
Simulation time 485160110725 ps
CPU time 274.56 seconds
Started Jul 30 07:18:28 PM PDT 24
Finished Jul 30 07:23:02 PM PDT 24
Peak memory 201440 kb
Host smart-c599a9a0-1dcb-4af3-a09b-64f5d8477b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990132476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3990132476
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1463068791
Short name T66
Test name
Test status
Simulation time 27127428751 ps
CPU time 11.97 seconds
Started Jul 30 07:21:03 PM PDT 24
Finished Jul 30 07:21:15 PM PDT 24
Peak memory 201588 kb
Host smart-daf87823-e5f1-47cb-825d-8a909c1dfeb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463068791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1463068791
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.343837088
Short name T186
Test name
Test status
Simulation time 515194514669 ps
CPU time 112.18 seconds
Started Jul 30 07:06:50 PM PDT 24
Finished Jul 30 07:08:42 PM PDT 24
Peak memory 201480 kb
Host smart-b8dd6b53-4d9f-4e8c-8cf0-5d88d4d9b0d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343837088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.343837088
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.278851955
Short name T482
Test name
Test status
Simulation time 166499965720 ps
CPU time 52.71 seconds
Started Jul 30 07:14:37 PM PDT 24
Finished Jul 30 07:15:29 PM PDT 24
Peak memory 201452 kb
Host smart-dc3e51de-3484-487b-8987-c94f97b4d5ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278851955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.278851955
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1791150612
Short name T171
Test name
Test status
Simulation time 327107895186 ps
CPU time 681.49 seconds
Started Jul 30 07:17:31 PM PDT 24
Finished Jul 30 07:28:53 PM PDT 24
Peak memory 201508 kb
Host smart-1d0a2842-bd91-4ef4-bea4-fb9abc90616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791150612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1791150612
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1599505469
Short name T304
Test name
Test status
Simulation time 489248661767 ps
CPU time 531.86 seconds
Started Jul 30 07:18:52 PM PDT 24
Finished Jul 30 07:27:44 PM PDT 24
Peak memory 201492 kb
Host smart-895368d8-504a-494c-829e-53bea2288fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599505469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1599505469
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2640931004
Short name T22
Test name
Test status
Simulation time 434896930588 ps
CPU time 718.12 seconds
Started Jul 30 07:08:15 PM PDT 24
Finished Jul 30 07:20:13 PM PDT 24
Peak memory 210144 kb
Host smart-e34145eb-7572-4313-959e-d45532273ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640931004 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2640931004
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4181147182
Short name T322
Test name
Test status
Simulation time 4247608427 ps
CPU time 6.33 seconds
Started Jul 30 07:21:40 PM PDT 24
Finished Jul 30 07:21:46 PM PDT 24
Peak memory 201544 kb
Host smart-ab0271e5-4d38-433c-9003-adcd246100a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181147182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4181147182
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2437723295
Short name T293
Test name
Test status
Simulation time 517982207421 ps
CPU time 1209.13 seconds
Started Jul 30 07:09:50 PM PDT 24
Finished Jul 30 07:30:00 PM PDT 24
Peak memory 201500 kb
Host smart-576518c8-708b-41a9-84a1-80bb3bbcda05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437723295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2437723295
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.4200239342
Short name T297
Test name
Test status
Simulation time 660137991967 ps
CPU time 1240.79 seconds
Started Jul 30 07:12:14 PM PDT 24
Finished Jul 30 07:32:55 PM PDT 24
Peak memory 201376 kb
Host smart-55789a6c-e38e-40ac-b958-4712cab680f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200239342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.4200239342
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1687276426
Short name T53
Test name
Test status
Simulation time 579028065901 ps
CPU time 305.56 seconds
Started Jul 30 07:17:11 PM PDT 24
Finished Jul 30 07:22:17 PM PDT 24
Peak memory 210092 kb
Host smart-c32f49b9-65e8-4593-a4bb-8e02aa5892c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687276426 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1687276426
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1831448552
Short name T245
Test name
Test status
Simulation time 493771635672 ps
CPU time 1144.62 seconds
Started Jul 30 07:19:33 PM PDT 24
Finished Jul 30 07:38:38 PM PDT 24
Peak memory 201428 kb
Host smart-81b76aac-c1b5-4517-8c72-958c04bf3659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831448552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1831448552
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1695022246
Short name T243
Test name
Test status
Simulation time 219452203398 ps
CPU time 475.58 seconds
Started Jul 30 07:08:26 PM PDT 24
Finished Jul 30 07:16:21 PM PDT 24
Peak memory 201480 kb
Host smart-161f89d6-5935-46b0-ad85-155588f58ea7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695022246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1695022246
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4034726057
Short name T325
Test name
Test status
Simulation time 124098780382 ps
CPU time 477.57 seconds
Started Jul 30 07:06:04 PM PDT 24
Finished Jul 30 07:14:01 PM PDT 24
Peak memory 201892 kb
Host smart-0c3cf377-a56e-4d07-b60b-c89460228e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034726057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4034726057
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.4203867681
Short name T63
Test name
Test status
Simulation time 121962402254 ps
CPU time 445.9 seconds
Started Jul 30 07:06:30 PM PDT 24
Finished Jul 30 07:13:56 PM PDT 24
Peak memory 201828 kb
Host smart-147e3243-5f63-45fb-b5f9-ef7236bbd599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203867681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.4203867681
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4149624805
Short name T247
Test name
Test status
Simulation time 369107441276 ps
CPU time 700.65 seconds
Started Jul 30 07:06:35 PM PDT 24
Finished Jul 30 07:18:16 PM PDT 24
Peak memory 201576 kb
Host smart-d8a912fe-4a44-431b-960a-61dc116b90dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149624805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4149624805
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3031567257
Short name T227
Test name
Test status
Simulation time 321222606590 ps
CPU time 90.2 seconds
Started Jul 30 07:10:33 PM PDT 24
Finished Jul 30 07:12:03 PM PDT 24
Peak memory 201504 kb
Host smart-ad8e329e-4fbf-4888-a9b2-744f6fdfa228
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031567257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3031567257
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1253837575
Short name T24
Test name
Test status
Simulation time 179073884249 ps
CPU time 167.93 seconds
Started Jul 30 07:10:43 PM PDT 24
Finished Jul 30 07:13:31 PM PDT 24
Peak memory 210148 kb
Host smart-8d0a6118-59f3-40e9-a3d1-3ed61fc3b55a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253837575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1253837575
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3239860971
Short name T326
Test name
Test status
Simulation time 87769247677 ps
CPU time 481.75 seconds
Started Jul 30 07:11:47 PM PDT 24
Finished Jul 30 07:19:49 PM PDT 24
Peak memory 201876 kb
Host smart-bad3d5e4-658e-42b9-96da-450875e785e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239860971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3239860971
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2777079470
Short name T287
Test name
Test status
Simulation time 174749452349 ps
CPU time 348.76 seconds
Started Jul 30 07:12:24 PM PDT 24
Finished Jul 30 07:18:13 PM PDT 24
Peak memory 201376 kb
Host smart-92487d74-41c3-4089-84a5-395fb341c950
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777079470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2777079470
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2391357714
Short name T213
Test name
Test status
Simulation time 108936956488 ps
CPU time 467.39 seconds
Started Jul 30 07:13:01 PM PDT 24
Finished Jul 30 07:20:49 PM PDT 24
Peak memory 201840 kb
Host smart-dd4135b0-2d20-46c0-b43b-5b129ef8cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391357714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2391357714
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1508303033
Short name T181
Test name
Test status
Simulation time 494203038381 ps
CPU time 53.65 seconds
Started Jul 30 07:13:32 PM PDT 24
Finished Jul 30 07:14:25 PM PDT 24
Peak memory 201568 kb
Host smart-91368a33-b160-48a8-8e2f-e09fada3b09c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508303033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1508303033
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3387936253
Short name T204
Test name
Test status
Simulation time 1266222533836 ps
CPU time 1169.88 seconds
Started Jul 30 07:15:08 PM PDT 24
Finished Jul 30 07:34:38 PM PDT 24
Peak memory 212480 kb
Host smart-fff73af8-34d6-4c09-9db0-61ea9cfabd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387936253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3387936253
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2822755185
Short name T143
Test name
Test status
Simulation time 491042913114 ps
CPU time 312.35 seconds
Started Jul 30 07:15:46 PM PDT 24
Finished Jul 30 07:20:58 PM PDT 24
Peak memory 201468 kb
Host smart-c58f9d15-9c14-435c-bd0d-478276a9ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822755185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2822755185
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2133929860
Short name T149
Test name
Test status
Simulation time 492469923914 ps
CPU time 656.56 seconds
Started Jul 30 07:17:48 PM PDT 24
Finished Jul 30 07:28:44 PM PDT 24
Peak memory 201456 kb
Host smart-d4210f35-e4ba-4a49-a1b0-636f5e8b8d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133929860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2133929860
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3864796493
Short name T182
Test name
Test status
Simulation time 490459663668 ps
CPU time 169.97 seconds
Started Jul 30 07:18:42 PM PDT 24
Finished Jul 30 07:21:32 PM PDT 24
Peak memory 201432 kb
Host smart-4a0bbabe-b131-417d-8b5c-0f392a755de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864796493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3864796493
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2355916230
Short name T292
Test name
Test status
Simulation time 163115734772 ps
CPU time 174.33 seconds
Started Jul 30 07:19:44 PM PDT 24
Finished Jul 30 07:22:38 PM PDT 24
Peak memory 201492 kb
Host smart-cc6038af-f324-4ced-a4cf-2cb6018c7ae9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355916230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2355916230
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.369645207
Short name T282
Test name
Test status
Simulation time 161933911023 ps
CPU time 51.53 seconds
Started Jul 30 07:08:25 PM PDT 24
Finished Jul 30 07:09:17 PM PDT 24
Peak memory 201464 kb
Host smart-e8cfdf8c-7d80-4c5a-a12a-2fca9911df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369645207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.369645207
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.269684469
Short name T277
Test name
Test status
Simulation time 194152764717 ps
CPU time 67.55 seconds
Started Jul 30 07:09:09 PM PDT 24
Finished Jul 30 07:10:17 PM PDT 24
Peak memory 201512 kb
Host smart-699c87fe-b353-4bb5-b5f6-34fd88090217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269684469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.269684469
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4117770961
Short name T137
Test name
Test status
Simulation time 954453940 ps
CPU time 4.14 seconds
Started Jul 30 07:21:04 PM PDT 24
Finished Jul 30 07:21:09 PM PDT 24
Peak memory 201588 kb
Host smart-3fd2ea49-7990-47a9-91db-e98d19c9edcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117770961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.4117770961
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.20189911
Short name T837
Test name
Test status
Simulation time 760981485 ps
CPU time 1.33 seconds
Started Jul 30 07:20:57 PM PDT 24
Finished Jul 30 07:20:58 PM PDT 24
Peak memory 201348 kb
Host smart-60f50b80-449a-414d-8d51-97ab33990374
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20189911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_res
et.20189911
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3448776923
Short name T882
Test name
Test status
Simulation time 565105663 ps
CPU time 1.03 seconds
Started Jul 30 07:21:04 PM PDT 24
Finished Jul 30 07:21:05 PM PDT 24
Peak memory 201508 kb
Host smart-efffed18-3418-49e5-be38-9d2ce6f73a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448776923 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3448776923
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2723793955
Short name T885
Test name
Test status
Simulation time 495747226 ps
CPU time 1.87 seconds
Started Jul 30 07:20:58 PM PDT 24
Finished Jul 30 07:21:00 PM PDT 24
Peak memory 201348 kb
Host smart-1b4c93cc-1b8d-447e-a40f-dc471ce11e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723793955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2723793955
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1927301208
Short name T867
Test name
Test status
Simulation time 498835791 ps
CPU time 0.87 seconds
Started Jul 30 07:20:55 PM PDT 24
Finished Jul 30 07:20:56 PM PDT 24
Peak memory 201280 kb
Host smart-316050bc-19b4-4ffe-a540-6245ec438dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927301208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1927301208
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2879751581
Short name T845
Test name
Test status
Simulation time 4685384597 ps
CPU time 4.44 seconds
Started Jul 30 07:21:03 PM PDT 24
Finished Jul 30 07:21:07 PM PDT 24
Peak memory 201624 kb
Host smart-a8f784a5-6b63-4a1e-8cf1-2535f12695b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879751581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2879751581
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2612701064
Short name T870
Test name
Test status
Simulation time 433053541 ps
CPU time 2.7 seconds
Started Jul 30 07:20:55 PM PDT 24
Finished Jul 30 07:20:58 PM PDT 24
Peak memory 218192 kb
Host smart-981cc284-3749-4d24-a664-c34f2f1e02ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612701064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2612701064
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.176306134
Short name T135
Test name
Test status
Simulation time 1361203236 ps
CPU time 2.54 seconds
Started Jul 30 07:21:10 PM PDT 24
Finished Jul 30 07:21:13 PM PDT 24
Peak memory 201588 kb
Host smart-327da8bb-3604-4daa-9230-f61aa3337ac9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176306134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.176306134
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3034684579
Short name T65
Test name
Test status
Simulation time 23876685659 ps
CPU time 27.91 seconds
Started Jul 30 07:21:07 PM PDT 24
Finished Jul 30 07:21:35 PM PDT 24
Peak memory 201588 kb
Host smart-0d3abaa5-f849-4ad1-a3a8-269cd6d3710b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034684579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3034684579
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3418208063
Short name T125
Test name
Test status
Simulation time 960830452 ps
CPU time 3.04 seconds
Started Jul 30 07:21:03 PM PDT 24
Finished Jul 30 07:21:06 PM PDT 24
Peak memory 201372 kb
Host smart-97dae11e-e7bc-47d9-a123-39b535afaba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418208063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3418208063
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3118896871
Short name T76
Test name
Test status
Simulation time 633624418 ps
CPU time 1.29 seconds
Started Jul 30 07:21:09 PM PDT 24
Finished Jul 30 07:21:10 PM PDT 24
Peak memory 201456 kb
Host smart-0334cd49-9770-4cf2-b9a0-4deb0216cc01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118896871 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3118896871
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.432092642
Short name T140
Test name
Test status
Simulation time 575312990 ps
CPU time 1.02 seconds
Started Jul 30 07:21:06 PM PDT 24
Finished Jul 30 07:21:07 PM PDT 24
Peak memory 201412 kb
Host smart-71b0d9ea-abb0-4cae-8a53-e33a6dc09d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432092642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.432092642
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.831613484
Short name T805
Test name
Test status
Simulation time 382691608 ps
CPU time 0.81 seconds
Started Jul 30 07:21:02 PM PDT 24
Finished Jul 30 07:21:03 PM PDT 24
Peak memory 201344 kb
Host smart-66c18dee-70fe-4509-ba80-3e2ac52ea2db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831613484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.831613484
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1877733558
Short name T823
Test name
Test status
Simulation time 4227318246 ps
CPU time 16.48 seconds
Started Jul 30 07:21:10 PM PDT 24
Finished Jul 30 07:21:27 PM PDT 24
Peak memory 201644 kb
Host smart-34cb59ac-fdcd-46c6-a819-dfbcd9049c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877733558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1877733558
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.300829035
Short name T881
Test name
Test status
Simulation time 494201410 ps
CPU time 1.96 seconds
Started Jul 30 07:21:02 PM PDT 24
Finished Jul 30 07:21:04 PM PDT 24
Peak memory 201652 kb
Host smart-cc642253-0578-459a-b48a-6f1be1d7bd61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300829035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.300829035
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.927113798
Short name T850
Test name
Test status
Simulation time 9013198208 ps
CPU time 7.14 seconds
Started Jul 30 07:21:01 PM PDT 24
Finished Jul 30 07:21:09 PM PDT 24
Peak memory 201628 kb
Host smart-801ded17-8bdd-4927-a4de-aad062ab8539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927113798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.927113798
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1809109476
Short name T807
Test name
Test status
Simulation time 319576360 ps
CPU time 1.54 seconds
Started Jul 30 07:21:56 PM PDT 24
Finished Jul 30 07:21:57 PM PDT 24
Peak memory 201544 kb
Host smart-d5febc34-c8e2-458e-9612-9a84df2a69bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809109476 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1809109476
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3825699310
Short name T839
Test name
Test status
Simulation time 370988186 ps
CPU time 0.79 seconds
Started Jul 30 07:21:52 PM PDT 24
Finished Jul 30 07:21:53 PM PDT 24
Peak memory 201404 kb
Host smart-f8459517-7c5d-4a3f-9de6-2b607e423014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825699310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3825699310
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3171145334
Short name T859
Test name
Test status
Simulation time 436787973 ps
CPU time 0.89 seconds
Started Jul 30 07:21:52 PM PDT 24
Finished Jul 30 07:21:53 PM PDT 24
Peak memory 201344 kb
Host smart-660eadb8-a1d1-478c-966d-b6885e5d325d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171145334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3171145334
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3340343006
Short name T818
Test name
Test status
Simulation time 2266614804 ps
CPU time 2.83 seconds
Started Jul 30 07:21:55 PM PDT 24
Finished Jul 30 07:21:58 PM PDT 24
Peak memory 201468 kb
Host smart-cd17e2c3-d0e8-4a5c-8dfd-d9cf694887a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340343006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3340343006
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.259019924
Short name T858
Test name
Test status
Simulation time 431507310 ps
CPU time 2.47 seconds
Started Jul 30 07:21:51 PM PDT 24
Finished Jul 30 07:21:53 PM PDT 24
Peak memory 201680 kb
Host smart-92621c95-123a-4f0b-998e-256595136f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259019924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.259019924
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2669143774
Short name T892
Test name
Test status
Simulation time 4413878444 ps
CPU time 10.85 seconds
Started Jul 30 07:21:52 PM PDT 24
Finished Jul 30 07:22:03 PM PDT 24
Peak memory 201588 kb
Host smart-e20aea8c-0201-4c43-8481-ce809277cffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669143774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2669143774
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1364571587
Short name T888
Test name
Test status
Simulation time 513172795 ps
CPU time 1.46 seconds
Started Jul 30 07:21:56 PM PDT 24
Finished Jul 30 07:21:58 PM PDT 24
Peak memory 209856 kb
Host smart-8909b307-619c-46e9-8674-d29d47785281
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364571587 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1364571587
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3294043390
Short name T883
Test name
Test status
Simulation time 416718930 ps
CPU time 1.73 seconds
Started Jul 30 07:21:57 PM PDT 24
Finished Jul 30 07:21:59 PM PDT 24
Peak memory 201352 kb
Host smart-f435f933-f35e-447a-8e3d-5ef0cd5048fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294043390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3294043390
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1636812782
Short name T912
Test name
Test status
Simulation time 457444332 ps
CPU time 1.53 seconds
Started Jul 30 07:21:58 PM PDT 24
Finished Jul 30 07:22:00 PM PDT 24
Peak memory 201352 kb
Host smart-795cec85-fb9e-4d1e-b119-9cb9abfbecf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636812782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1636812782
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2625787604
Short name T899
Test name
Test status
Simulation time 2063710591 ps
CPU time 5.47 seconds
Started Jul 30 07:21:55 PM PDT 24
Finished Jul 30 07:22:01 PM PDT 24
Peak memory 201352 kb
Host smart-6ee113e3-4205-4245-a403-ec7f5392c9b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625787604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2625787604
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.663177804
Short name T819
Test name
Test status
Simulation time 410327308 ps
CPU time 2.15 seconds
Started Jul 30 07:21:57 PM PDT 24
Finished Jul 30 07:21:59 PM PDT 24
Peak memory 201604 kb
Host smart-c3432059-ea2e-433f-bfe3-8a381eefa04c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663177804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.663177804
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3390204546
Short name T323
Test name
Test status
Simulation time 8192668811 ps
CPU time 20.22 seconds
Started Jul 30 07:21:55 PM PDT 24
Finished Jul 30 07:22:16 PM PDT 24
Peak memory 201664 kb
Host smart-dea00af4-2098-4b7b-8486-f8059ce9cecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390204546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3390204546
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3659491601
Short name T90
Test name
Test status
Simulation time 562438606 ps
CPU time 2.17 seconds
Started Jul 30 07:22:00 PM PDT 24
Finished Jul 30 07:22:02 PM PDT 24
Peak memory 201524 kb
Host smart-f4f32a6b-df5a-42a0-be39-b6d093aca2b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659491601 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3659491601
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3211800187
Short name T844
Test name
Test status
Simulation time 346134964 ps
CPU time 1.56 seconds
Started Jul 30 07:22:00 PM PDT 24
Finished Jul 30 07:22:02 PM PDT 24
Peak memory 201416 kb
Host smart-afe34968-7761-4cfb-a70a-8b21d4ccb969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211800187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3211800187
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3258954927
Short name T900
Test name
Test status
Simulation time 386124009 ps
CPU time 1.52 seconds
Started Jul 30 07:21:58 PM PDT 24
Finished Jul 30 07:22:00 PM PDT 24
Peak memory 201388 kb
Host smart-af0fad22-6738-4e89-922e-2ae5dc456e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258954927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3258954927
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3995495917
Short name T887
Test name
Test status
Simulation time 1841645911 ps
CPU time 4.87 seconds
Started Jul 30 07:22:00 PM PDT 24
Finished Jul 30 07:22:05 PM PDT 24
Peak memory 201444 kb
Host smart-e688cefa-c2ad-43a5-a693-cd1260a30d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995495917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3995495917
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4108810523
Short name T85
Test name
Test status
Simulation time 559307157 ps
CPU time 3.2 seconds
Started Jul 30 07:21:55 PM PDT 24
Finished Jul 30 07:21:58 PM PDT 24
Peak memory 201664 kb
Host smart-37436d7c-4ed3-4bc3-bda5-1f9cd9793642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108810523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4108810523
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.492727410
Short name T829
Test name
Test status
Simulation time 4590837827 ps
CPU time 4.21 seconds
Started Jul 30 07:21:56 PM PDT 24
Finished Jul 30 07:22:00 PM PDT 24
Peak memory 201476 kb
Host smart-222b449f-ae60-4b63-814d-0394cb91327e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492727410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.492727410
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2447910227
Short name T847
Test name
Test status
Simulation time 665046200 ps
CPU time 1.37 seconds
Started Jul 30 07:22:06 PM PDT 24
Finished Jul 30 07:22:08 PM PDT 24
Peak memory 201500 kb
Host smart-71ef2d48-e2cb-4d14-bc01-fd8984a52ac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447910227 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2447910227
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2607056486
Short name T817
Test name
Test status
Simulation time 527123223 ps
CPU time 1.27 seconds
Started Jul 30 07:22:04 PM PDT 24
Finished Jul 30 07:22:06 PM PDT 24
Peak memory 201372 kb
Host smart-a3d98430-5e15-41af-b8af-065e5130c7b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607056486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2607056486
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4080020434
Short name T848
Test name
Test status
Simulation time 366502686 ps
CPU time 1.46 seconds
Started Jul 30 07:22:01 PM PDT 24
Finished Jul 30 07:22:03 PM PDT 24
Peak memory 201344 kb
Host smart-3f4b234e-4c2d-4b6d-8fd3-6dc190ab72e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080020434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4080020434
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3464042721
Short name T827
Test name
Test status
Simulation time 2585882206 ps
CPU time 2.31 seconds
Started Jul 30 07:22:06 PM PDT 24
Finished Jul 30 07:22:09 PM PDT 24
Peak memory 201552 kb
Host smart-39bde8e6-e5b7-494a-8415-60d3ed705d47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464042721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3464042721
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3147323055
Short name T908
Test name
Test status
Simulation time 465929166 ps
CPU time 2.34 seconds
Started Jul 30 07:21:58 PM PDT 24
Finished Jul 30 07:22:01 PM PDT 24
Peak memory 201716 kb
Host smart-3a3c2be9-fd32-4101-bd42-681358e10307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147323055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3147323055
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1514732219
Short name T73
Test name
Test status
Simulation time 4676689931 ps
CPU time 4.35 seconds
Started Jul 30 07:22:00 PM PDT 24
Finished Jul 30 07:22:05 PM PDT 24
Peak memory 201612 kb
Host smart-d9a74812-0a10-4042-b613-4eb928be2604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514732219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1514732219
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2619065746
Short name T86
Test name
Test status
Simulation time 663592699 ps
CPU time 1.34 seconds
Started Jul 30 07:22:08 PM PDT 24
Finished Jul 30 07:22:10 PM PDT 24
Peak memory 201520 kb
Host smart-8d1e19ef-25d7-43bd-9a2a-60b0d78b5e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619065746 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2619065746
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1072656304
Short name T915
Test name
Test status
Simulation time 472218681 ps
CPU time 0.84 seconds
Started Jul 30 07:22:06 PM PDT 24
Finished Jul 30 07:22:07 PM PDT 24
Peak memory 201352 kb
Host smart-37006f2d-233c-4013-be70-38d7d3ed3bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072656304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1072656304
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1372665769
Short name T68
Test name
Test status
Simulation time 2228187867 ps
CPU time 5.56 seconds
Started Jul 30 07:22:04 PM PDT 24
Finished Jul 30 07:22:10 PM PDT 24
Peak memory 201416 kb
Host smart-3b51009e-166b-466c-b977-5486eee9cf54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372665769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1372665769
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.165395554
Short name T83
Test name
Test status
Simulation time 415452096 ps
CPU time 2.44 seconds
Started Jul 30 07:22:04 PM PDT 24
Finished Jul 30 07:22:06 PM PDT 24
Peak memory 201716 kb
Host smart-d4f25d7c-c335-40fa-a9e5-843f617de87e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165395554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.165395554
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3835376744
Short name T92
Test name
Test status
Simulation time 4322834840 ps
CPU time 3.95 seconds
Started Jul 30 07:22:04 PM PDT 24
Finished Jul 30 07:22:08 PM PDT 24
Peak memory 201648 kb
Host smart-61acc667-52d1-4151-9333-32c1ffc2e2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835376744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3835376744
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2920353283
Short name T855
Test name
Test status
Simulation time 545095473 ps
CPU time 2.04 seconds
Started Jul 30 07:22:12 PM PDT 24
Finished Jul 30 07:22:14 PM PDT 24
Peak memory 201548 kb
Host smart-e6f24da8-91fd-459a-91d0-3593fcf4b317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920353283 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2920353283
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3855390880
Short name T134
Test name
Test status
Simulation time 548601866 ps
CPU time 1.59 seconds
Started Jul 30 07:22:13 PM PDT 24
Finished Jul 30 07:22:14 PM PDT 24
Peak memory 201356 kb
Host smart-31ac4792-5fd8-47a2-9b67-e64b3c1aa308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855390880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3855390880
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1822542232
Short name T801
Test name
Test status
Simulation time 374125669 ps
CPU time 0.96 seconds
Started Jul 30 07:22:07 PM PDT 24
Finished Jul 30 07:22:08 PM PDT 24
Peak memory 201368 kb
Host smart-95e09ddc-4c4f-477c-855b-4e1525f93790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822542232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1822542232
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2664554376
Short name T835
Test name
Test status
Simulation time 4034919237 ps
CPU time 7.46 seconds
Started Jul 30 07:22:16 PM PDT 24
Finished Jul 30 07:22:24 PM PDT 24
Peak memory 201544 kb
Host smart-88c1bc3e-543b-49dc-9854-5834efe8cde3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664554376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2664554376
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4282262753
Short name T834
Test name
Test status
Simulation time 343165874 ps
CPU time 2.16 seconds
Started Jul 30 07:22:07 PM PDT 24
Finished Jul 30 07:22:09 PM PDT 24
Peak memory 201700 kb
Host smart-0a579042-cf20-4b10-a66c-ce60201157c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282262753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4282262753
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3155681548
Short name T78
Test name
Test status
Simulation time 9021380477 ps
CPU time 23.67 seconds
Started Jul 30 07:22:09 PM PDT 24
Finished Jul 30 07:22:32 PM PDT 24
Peak memory 201616 kb
Host smart-064a1390-4a98-4a4b-ac72-26f66242ca28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155681548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3155681548
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3330034935
Short name T896
Test name
Test status
Simulation time 485101519 ps
CPU time 1.51 seconds
Started Jul 30 07:22:17 PM PDT 24
Finished Jul 30 07:22:19 PM PDT 24
Peak memory 201480 kb
Host smart-781d430c-0d0f-40b8-9ebf-58b3997ffe5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330034935 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3330034935
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4062577465
Short name T138
Test name
Test status
Simulation time 489773965 ps
CPU time 1.85 seconds
Started Jul 30 07:22:17 PM PDT 24
Finished Jul 30 07:22:19 PM PDT 24
Peak memory 201368 kb
Host smart-b8d6f16e-9b86-41f5-bdd2-c00d6d334a6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062577465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4062577465
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4289261308
Short name T798
Test name
Test status
Simulation time 441410984 ps
CPU time 1.67 seconds
Started Jul 30 07:22:11 PM PDT 24
Finished Jul 30 07:22:12 PM PDT 24
Peak memory 201400 kb
Host smart-2db1910d-bbeb-4a32-a9c1-8be2c452ba92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289261308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4289261308
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.366154377
Short name T902
Test name
Test status
Simulation time 4046285637 ps
CPU time 13.7 seconds
Started Jul 30 07:22:15 PM PDT 24
Finished Jul 30 07:22:29 PM PDT 24
Peak memory 201468 kb
Host smart-67223ace-cc38-426f-8543-965afa625b95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366154377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.366154377
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3928602820
Short name T836
Test name
Test status
Simulation time 4490640198 ps
CPU time 6.77 seconds
Started Jul 30 07:22:12 PM PDT 24
Finished Jul 30 07:22:19 PM PDT 24
Peak memory 201664 kb
Host smart-605fb7aa-241b-4917-98b6-72ef63e1e115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928602820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3928602820
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.655931163
Short name T880
Test name
Test status
Simulation time 551499181 ps
CPU time 1.15 seconds
Started Jul 30 07:22:17 PM PDT 24
Finished Jul 30 07:22:18 PM PDT 24
Peak memory 201468 kb
Host smart-d5431d02-3164-478e-8259-974afe9cd535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655931163 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.655931163
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2859265857
Short name T903
Test name
Test status
Simulation time 674596695 ps
CPU time 0.91 seconds
Started Jul 30 07:22:14 PM PDT 24
Finished Jul 30 07:22:15 PM PDT 24
Peak memory 201388 kb
Host smart-2617570b-5997-4016-a9ee-9516269a25ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859265857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2859265857
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1175721979
Short name T814
Test name
Test status
Simulation time 478059941 ps
CPU time 1.73 seconds
Started Jul 30 07:22:17 PM PDT 24
Finished Jul 30 07:22:18 PM PDT 24
Peak memory 201368 kb
Host smart-12811c54-170a-4f04-a4a2-c89703acceed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175721979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1175721979
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3975805406
Short name T852
Test name
Test status
Simulation time 5085259977 ps
CPU time 12.83 seconds
Started Jul 30 07:22:17 PM PDT 24
Finished Jul 30 07:22:30 PM PDT 24
Peak memory 201600 kb
Host smart-95725ff8-56ca-4798-a054-6529a41736cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975805406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3975805406
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1303551994
Short name T846
Test name
Test status
Simulation time 684923492 ps
CPU time 1.65 seconds
Started Jul 30 07:22:15 PM PDT 24
Finished Jul 30 07:22:17 PM PDT 24
Peak memory 201652 kb
Host smart-b99c6997-7ba9-408b-9023-a1fef6831405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303551994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1303551994
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4031658153
Short name T898
Test name
Test status
Simulation time 4691105762 ps
CPU time 11.49 seconds
Started Jul 30 07:22:15 PM PDT 24
Finished Jul 30 07:22:26 PM PDT 24
Peak memory 201692 kb
Host smart-be5a0baa-9c73-443f-ba9d-b2eecb28e7e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031658153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4031658153
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.814771299
Short name T917
Test name
Test status
Simulation time 689617305 ps
CPU time 0.86 seconds
Started Jul 30 07:22:18 PM PDT 24
Finished Jul 30 07:22:19 PM PDT 24
Peak memory 201480 kb
Host smart-7c91d67d-b772-4225-918c-d787e435d3f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814771299 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.814771299
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2880491617
Short name T128
Test name
Test status
Simulation time 345112299 ps
CPU time 0.9 seconds
Started Jul 30 07:22:16 PM PDT 24
Finished Jul 30 07:22:17 PM PDT 24
Peak memory 201372 kb
Host smart-1d7dde6a-0c0b-4a79-a0eb-bdd7bb3ba378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880491617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2880491617
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2866746650
Short name T897
Test name
Test status
Simulation time 398168072 ps
CPU time 1.09 seconds
Started Jul 30 07:22:16 PM PDT 24
Finished Jul 30 07:22:17 PM PDT 24
Peak memory 201328 kb
Host smart-da25821a-acd1-435f-9da9-d8f09cd25e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866746650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2866746650
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3792854429
Short name T857
Test name
Test status
Simulation time 4337844904 ps
CPU time 16.93 seconds
Started Jul 30 07:22:16 PM PDT 24
Finished Jul 30 07:22:33 PM PDT 24
Peak memory 201556 kb
Host smart-443e32a0-b71a-4166-9088-3925cd1de525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792854429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3792854429
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3891151255
Short name T868
Test name
Test status
Simulation time 491311092 ps
CPU time 2.06 seconds
Started Jul 30 07:22:17 PM PDT 24
Finished Jul 30 07:22:19 PM PDT 24
Peak memory 201624 kb
Host smart-c5ea2d35-3e8f-4713-8d38-45c9ca9d1125
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891151255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3891151255
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3627363170
Short name T851
Test name
Test status
Simulation time 5053288982 ps
CPU time 4.54 seconds
Started Jul 30 07:22:16 PM PDT 24
Finished Jul 30 07:22:21 PM PDT 24
Peak memory 201672 kb
Host smart-18f293a6-aa6e-4beb-a928-5a3b77f7174e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627363170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3627363170
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.196454389
Short name T875
Test name
Test status
Simulation time 430854234 ps
CPU time 1.04 seconds
Started Jul 30 07:22:20 PM PDT 24
Finished Jul 30 07:22:21 PM PDT 24
Peak memory 201472 kb
Host smart-07252b3a-c285-443e-9ecb-28eeeb45755d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196454389 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.196454389
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1630469861
Short name T130
Test name
Test status
Simulation time 464254131 ps
CPU time 0.89 seconds
Started Jul 30 07:22:19 PM PDT 24
Finished Jul 30 07:22:20 PM PDT 24
Peak memory 201344 kb
Host smart-f50f0003-ce30-442e-921a-6fcb5773bdba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630469861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1630469861
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3441887584
Short name T824
Test name
Test status
Simulation time 449856814 ps
CPU time 0.85 seconds
Started Jul 30 07:22:20 PM PDT 24
Finished Jul 30 07:22:21 PM PDT 24
Peak memory 201316 kb
Host smart-4f40835d-9bf2-4abd-bb3e-5f0dbc5afd59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441887584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3441887584
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3588613382
Short name T830
Test name
Test status
Simulation time 5274189539 ps
CPU time 7.41 seconds
Started Jul 30 07:22:19 PM PDT 24
Finished Jul 30 07:22:27 PM PDT 24
Peak memory 201516 kb
Host smart-a6c86318-1d36-497c-8327-b7e9cc0149f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588613382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3588613382
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3374570014
Short name T906
Test name
Test status
Simulation time 1024731699 ps
CPU time 2.9 seconds
Started Jul 30 07:22:19 PM PDT 24
Finished Jul 30 07:22:22 PM PDT 24
Peak memory 210896 kb
Host smart-04cf1cc3-1159-47a3-aa3d-e6c285481e01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374570014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3374570014
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1765155230
Short name T901
Test name
Test status
Simulation time 4218325377 ps
CPU time 4.09 seconds
Started Jul 30 07:22:19 PM PDT 24
Finished Jul 30 07:22:23 PM PDT 24
Peak memory 201644 kb
Host smart-7277e587-e1e5-40ff-ad1e-3cc66f73cf5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765155230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1765155230
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2250888993
Short name T853
Test name
Test status
Simulation time 557284076 ps
CPU time 2.74 seconds
Started Jul 30 07:21:17 PM PDT 24
Finished Jul 30 07:21:20 PM PDT 24
Peak memory 201560 kb
Host smart-ff25bf1f-e216-45ef-b0ae-6e756d106d89
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250888993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2250888993
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.596890857
Short name T863
Test name
Test status
Simulation time 26496895002 ps
CPU time 18.96 seconds
Started Jul 30 07:21:12 PM PDT 24
Finished Jul 30 07:21:32 PM PDT 24
Peak memory 201592 kb
Host smart-2b69d6c7-51d3-472e-8f70-8cbc708dd74d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596890857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.596890857
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3244747292
Short name T136
Test name
Test status
Simulation time 672695560 ps
CPU time 1.29 seconds
Started Jul 30 07:21:15 PM PDT 24
Finished Jul 30 07:21:16 PM PDT 24
Peak memory 201368 kb
Host smart-157e5ff7-4832-4d70-8a07-a833e6f8e0bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244747292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3244747292
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3349574972
Short name T88
Test name
Test status
Simulation time 560720039 ps
CPU time 2.37 seconds
Started Jul 30 07:21:21 PM PDT 24
Finished Jul 30 07:21:24 PM PDT 24
Peak memory 201544 kb
Host smart-e25dcb67-509a-43de-bd8e-7418863f3f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349574972 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3349574972
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.434013747
Short name T878
Test name
Test status
Simulation time 439103467 ps
CPU time 1.67 seconds
Started Jul 30 07:21:13 PM PDT 24
Finished Jul 30 07:21:15 PM PDT 24
Peak memory 201368 kb
Host smart-e7848048-e69e-4e02-8749-03929d781fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434013747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.434013747
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4197036900
Short name T849
Test name
Test status
Simulation time 339917773 ps
CPU time 0.79 seconds
Started Jul 30 07:21:12 PM PDT 24
Finished Jul 30 07:21:13 PM PDT 24
Peak memory 201324 kb
Host smart-b4c9f82f-c162-4268-86c9-3849710d3619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197036900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4197036900
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1762064107
Short name T67
Test name
Test status
Simulation time 4381918247 ps
CPU time 2.93 seconds
Started Jul 30 07:21:24 PM PDT 24
Finished Jul 30 07:21:27 PM PDT 24
Peak memory 201600 kb
Host smart-a5f8c228-eefb-4f2e-85d3-c336c4f84330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762064107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1762064107
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4032202743
Short name T89
Test name
Test status
Simulation time 575999264 ps
CPU time 2.9 seconds
Started Jul 30 07:21:16 PM PDT 24
Finished Jul 30 07:21:19 PM PDT 24
Peak memory 217468 kb
Host smart-beef296d-4ebe-4162-909a-750004b9f9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032202743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4032202743
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.147216433
Short name T71
Test name
Test status
Simulation time 4516864416 ps
CPU time 4.24 seconds
Started Jul 30 07:21:16 PM PDT 24
Finished Jul 30 07:21:21 PM PDT 24
Peak memory 201680 kb
Host smart-386e6067-f9a0-4a0c-be5b-360e3e5adf37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147216433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.147216433
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1706981280
Short name T802
Test name
Test status
Simulation time 370107416 ps
CPU time 0.81 seconds
Started Jul 30 07:22:19 PM PDT 24
Finished Jul 30 07:22:20 PM PDT 24
Peak memory 201368 kb
Host smart-3abff345-1acd-4a2b-aa72-ad4958260d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706981280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1706981280
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.92146924
Short name T797
Test name
Test status
Simulation time 393632679 ps
CPU time 0.74 seconds
Started Jul 30 07:22:20 PM PDT 24
Finished Jul 30 07:22:21 PM PDT 24
Peak memory 201328 kb
Host smart-635c1f8e-0de1-4224-b1e5-9deb56f52144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92146924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.92146924
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4051278648
Short name T821
Test name
Test status
Simulation time 553633688 ps
CPU time 0.79 seconds
Started Jul 30 07:22:21 PM PDT 24
Finished Jul 30 07:22:22 PM PDT 24
Peak memory 201344 kb
Host smart-0b6bd6d4-b549-4afc-8145-1bb222c7e048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051278648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4051278648
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.686199083
Short name T809
Test name
Test status
Simulation time 469802576 ps
CPU time 0.8 seconds
Started Jul 30 07:22:23 PM PDT 24
Finished Jul 30 07:22:24 PM PDT 24
Peak memory 201408 kb
Host smart-966cfc15-360c-498e-892f-cdb919634dfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686199083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.686199083
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1864663727
Short name T815
Test name
Test status
Simulation time 403491989 ps
CPU time 1.05 seconds
Started Jul 30 07:22:23 PM PDT 24
Finished Jul 30 07:22:25 PM PDT 24
Peak memory 201352 kb
Host smart-634eaccd-57b8-4372-a92c-25e36b03b170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864663727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1864663727
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2765877312
Short name T840
Test name
Test status
Simulation time 479005364 ps
CPU time 1.72 seconds
Started Jul 30 07:22:23 PM PDT 24
Finished Jul 30 07:22:25 PM PDT 24
Peak memory 201364 kb
Host smart-2b755100-1289-47c8-9631-580a1132cac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765877312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2765877312
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4094783893
Short name T808
Test name
Test status
Simulation time 536063960 ps
CPU time 0.93 seconds
Started Jul 30 07:22:23 PM PDT 24
Finished Jul 30 07:22:24 PM PDT 24
Peak memory 201224 kb
Host smart-f087fe9a-dedd-42b3-9752-65ad3a9b7603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094783893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4094783893
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2785729239
Short name T816
Test name
Test status
Simulation time 386700456 ps
CPU time 0.86 seconds
Started Jul 30 07:22:22 PM PDT 24
Finished Jul 30 07:22:23 PM PDT 24
Peak memory 201536 kb
Host smart-46b541cb-199e-4259-a4fb-0c1d4dc9e057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785729239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2785729239
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3465685574
Short name T806
Test name
Test status
Simulation time 480756749 ps
CPU time 0.77 seconds
Started Jul 30 07:22:23 PM PDT 24
Finished Jul 30 07:22:24 PM PDT 24
Peak memory 201368 kb
Host smart-964a070c-c86b-4544-8912-72891e670d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465685574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3465685574
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.642634144
Short name T842
Test name
Test status
Simulation time 303595641 ps
CPU time 0.8 seconds
Started Jul 30 07:22:26 PM PDT 24
Finished Jul 30 07:22:27 PM PDT 24
Peak memory 201368 kb
Host smart-3e62e278-8723-48c5-8c4a-b893d6397840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642634144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.642634144
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4159152988
Short name T861
Test name
Test status
Simulation time 1191781624 ps
CPU time 4.52 seconds
Started Jul 30 07:21:24 PM PDT 24
Finished Jul 30 07:21:28 PM PDT 24
Peak memory 201596 kb
Host smart-43d7ca00-19bb-48a8-94a5-f884b89ab8ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159152988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4159152988
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.450456069
Short name T891
Test name
Test status
Simulation time 50980241112 ps
CPU time 109.61 seconds
Started Jul 30 07:21:26 PM PDT 24
Finished Jul 30 07:23:16 PM PDT 24
Peak memory 201604 kb
Host smart-867d46be-3214-4ff6-a510-bbce3498d676
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450456069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.450456069
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1034538944
Short name T913
Test name
Test status
Simulation time 903012998 ps
CPU time 0.92 seconds
Started Jul 30 07:21:23 PM PDT 24
Finished Jul 30 07:21:24 PM PDT 24
Peak memory 201380 kb
Host smart-6d372db4-965a-44d7-8c7f-738808ee86bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034538944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1034538944
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2874283973
Short name T87
Test name
Test status
Simulation time 440384120 ps
CPU time 1.07 seconds
Started Jul 30 07:21:28 PM PDT 24
Finished Jul 30 07:21:30 PM PDT 24
Peak memory 201476 kb
Host smart-1a0ce002-ce82-4853-aab4-f2afa4ae1007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874283973 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2874283973
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1173508818
Short name T129
Test name
Test status
Simulation time 461404515 ps
CPU time 1.23 seconds
Started Jul 30 07:21:21 PM PDT 24
Finished Jul 30 07:21:23 PM PDT 24
Peak memory 201396 kb
Host smart-f292076e-e001-4d44-bb65-27acba48ac75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173508818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1173508818
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.926734412
Short name T872
Test name
Test status
Simulation time 287333833 ps
CPU time 1.29 seconds
Started Jul 30 07:21:21 PM PDT 24
Finished Jul 30 07:21:23 PM PDT 24
Peak memory 201324 kb
Host smart-5acebbcb-e971-4797-8f0b-56cfaa1cc86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926734412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.926734412
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3079464653
Short name T874
Test name
Test status
Simulation time 4316333669 ps
CPU time 9.74 seconds
Started Jul 30 07:21:27 PM PDT 24
Finished Jul 30 07:21:37 PM PDT 24
Peak memory 201588 kb
Host smart-8963b0e2-c361-48e1-9e17-32c2b66dce3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079464653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3079464653
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1226171647
Short name T884
Test name
Test status
Simulation time 651639648 ps
CPU time 1.61 seconds
Started Jul 30 07:21:21 PM PDT 24
Finished Jul 30 07:21:23 PM PDT 24
Peak memory 201632 kb
Host smart-9c720383-064e-46bb-81c9-7db66dce47b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226171647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1226171647
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3192798708
Short name T864
Test name
Test status
Simulation time 8474187804 ps
CPU time 6.68 seconds
Started Jul 30 07:21:22 PM PDT 24
Finished Jul 30 07:21:29 PM PDT 24
Peak memory 201660 kb
Host smart-e2f975e8-9dff-4cce-b118-7b2ec41d63f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192798708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3192798708
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2669956913
Short name T822
Test name
Test status
Simulation time 549591632 ps
CPU time 0.82 seconds
Started Jul 30 07:22:22 PM PDT 24
Finished Jul 30 07:22:23 PM PDT 24
Peak memory 201372 kb
Host smart-3edae69f-f4d4-4536-9eae-7bdb0c569754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669956913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2669956913
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3010215106
Short name T854
Test name
Test status
Simulation time 488114963 ps
CPU time 0.73 seconds
Started Jul 30 07:22:22 PM PDT 24
Finished Jul 30 07:22:23 PM PDT 24
Peak memory 201352 kb
Host smart-77e5538a-6544-4ef0-8f5d-0f9ea112e500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010215106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3010215106
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.508591577
Short name T916
Test name
Test status
Simulation time 294496776 ps
CPU time 1.28 seconds
Started Jul 30 07:22:26 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201376 kb
Host smart-fabf6bfe-6de7-44a4-9d06-6d5ed1775bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508591577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.508591577
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4157502039
Short name T804
Test name
Test status
Simulation time 329745466 ps
CPU time 0.83 seconds
Started Jul 30 07:22:28 PM PDT 24
Finished Jul 30 07:22:29 PM PDT 24
Peak memory 201348 kb
Host smart-dcd4ebcf-76dc-4bfa-810c-eee25548eacf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157502039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4157502039
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.141400151
Short name T871
Test name
Test status
Simulation time 481478998 ps
CPU time 1.72 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201324 kb
Host smart-05a02e55-dd08-4093-b128-7fc19b9087b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141400151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.141400151
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3515775281
Short name T876
Test name
Test status
Simulation time 361618361 ps
CPU time 1.05 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201352 kb
Host smart-cfa6cd19-a4d0-442c-9876-2dd5b0d5e45e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515775281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3515775281
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2181376140
Short name T800
Test name
Test status
Simulation time 419309280 ps
CPU time 0.9 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201364 kb
Host smart-ddc4b051-fb23-4962-9b3b-214ff5d34363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181376140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2181376140
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3242419610
Short name T810
Test name
Test status
Simulation time 313849087 ps
CPU time 1.35 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201332 kb
Host smart-731b0478-1bf8-4f60-8a4c-0b4029c550e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242419610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3242419610
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2745188027
Short name T905
Test name
Test status
Simulation time 510655757 ps
CPU time 0.89 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201320 kb
Host smart-05e140b9-7a44-4e99-b051-e9c3098e0d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745188027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2745188027
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1232509636
Short name T904
Test name
Test status
Simulation time 312892929 ps
CPU time 1.33 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201360 kb
Host smart-eabb8e2b-0ee8-420a-adfd-d4f37f3b4398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232509636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1232509636
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2455774428
Short name T126
Test name
Test status
Simulation time 876968423 ps
CPU time 1.88 seconds
Started Jul 30 07:21:39 PM PDT 24
Finished Jul 30 07:21:41 PM PDT 24
Peak memory 201492 kb
Host smart-2c7f8f22-9c79-494a-b9fe-6eca917bac63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455774428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2455774428
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3070937693
Short name T856
Test name
Test status
Simulation time 14680433220 ps
CPU time 10.07 seconds
Started Jul 30 07:21:38 PM PDT 24
Finished Jul 30 07:21:48 PM PDT 24
Peak memory 201552 kb
Host smart-d2333899-f748-40d4-a92e-4086faa01ccf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070937693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3070937693
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2601826247
Short name T826
Test name
Test status
Simulation time 998191528 ps
CPU time 2.62 seconds
Started Jul 30 07:21:39 PM PDT 24
Finished Jul 30 07:21:41 PM PDT 24
Peak memory 201324 kb
Host smart-60920225-0e92-460f-a423-351fa92858c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601826247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2601826247
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1925449378
Short name T886
Test name
Test status
Simulation time 569149072 ps
CPU time 2.26 seconds
Started Jul 30 07:21:38 PM PDT 24
Finished Jul 30 07:21:41 PM PDT 24
Peak memory 201484 kb
Host smart-30be7a8e-1177-4307-a348-9d690897c8f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925449378 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1925449378
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1864380032
Short name T131
Test name
Test status
Simulation time 397043323 ps
CPU time 1.75 seconds
Started Jul 30 07:21:39 PM PDT 24
Finished Jul 30 07:21:41 PM PDT 24
Peak memory 201372 kb
Host smart-e25ff332-31ff-4c2e-80a7-8b158241830e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864380032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1864380032
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2849319692
Short name T910
Test name
Test status
Simulation time 550899789 ps
CPU time 0.92 seconds
Started Jul 30 07:21:28 PM PDT 24
Finished Jul 30 07:21:29 PM PDT 24
Peak memory 201400 kb
Host smart-b8a5dbe7-b01a-4b34-8bbd-27cf04ac8ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849319692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2849319692
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1313737044
Short name T866
Test name
Test status
Simulation time 4137101251 ps
CPU time 1.71 seconds
Started Jul 30 07:21:38 PM PDT 24
Finished Jul 30 07:21:40 PM PDT 24
Peak memory 201560 kb
Host smart-35ff75a4-03a6-4bcf-8689-97d80d4aa407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313737044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1313737044
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1032062109
Short name T879
Test name
Test status
Simulation time 429993512 ps
CPU time 2.2 seconds
Started Jul 30 07:21:28 PM PDT 24
Finished Jul 30 07:21:30 PM PDT 24
Peak memory 201664 kb
Host smart-d5659609-66ee-49ab-894b-2d9e1988d00e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032062109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1032062109
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.313636372
Short name T80
Test name
Test status
Simulation time 4618120133 ps
CPU time 4.1 seconds
Started Jul 30 07:21:29 PM PDT 24
Finished Jul 30 07:21:33 PM PDT 24
Peak memory 201684 kb
Host smart-8840cefb-7e17-4b55-af02-d256de821a08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313636372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.313636372
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3298404648
Short name T812
Test name
Test status
Simulation time 493302188 ps
CPU time 1.15 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201360 kb
Host smart-0ee735ce-91d7-454f-ae99-e2b298118302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298404648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3298404648
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3235917369
Short name T911
Test name
Test status
Simulation time 331460835 ps
CPU time 0.89 seconds
Started Jul 30 07:22:26 PM PDT 24
Finished Jul 30 07:22:27 PM PDT 24
Peak memory 201408 kb
Host smart-80cc54b1-09ae-44f4-b5c1-9eacde41931a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235917369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3235917369
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3360938423
Short name T803
Test name
Test status
Simulation time 502018877 ps
CPU time 1.76 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:29 PM PDT 24
Peak memory 201388 kb
Host smart-3859ad3e-ea12-43b0-a496-3d1644677bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360938423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3360938423
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.612415460
Short name T825
Test name
Test status
Simulation time 469482899 ps
CPU time 0.91 seconds
Started Jul 30 07:22:27 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201340 kb
Host smart-2f0b6945-7f43-452d-a894-b74b6ea53a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612415460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.612415460
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1889405314
Short name T831
Test name
Test status
Simulation time 443654503 ps
CPU time 0.88 seconds
Started Jul 30 07:22:32 PM PDT 24
Finished Jul 30 07:22:33 PM PDT 24
Peak memory 201364 kb
Host smart-6f69e459-6a3c-466c-9107-f6ff0c7cdbaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889405314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1889405314
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1815482119
Short name T843
Test name
Test status
Simulation time 563682321 ps
CPU time 0.99 seconds
Started Jul 30 07:22:33 PM PDT 24
Finished Jul 30 07:22:34 PM PDT 24
Peak memory 201368 kb
Host smart-57cabb8d-c15a-43f7-80b5-a135398a4422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815482119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1815482119
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.146702695
Short name T914
Test name
Test status
Simulation time 518143581 ps
CPU time 1.65 seconds
Started Jul 30 07:22:32 PM PDT 24
Finished Jul 30 07:22:34 PM PDT 24
Peak memory 201212 kb
Host smart-811185c4-3fcf-4625-ab90-177dcaa2dd23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146702695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.146702695
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.148784662
Short name T907
Test name
Test status
Simulation time 327569491 ps
CPU time 0.82 seconds
Started Jul 30 07:22:31 PM PDT 24
Finished Jul 30 07:22:32 PM PDT 24
Peak memory 201388 kb
Host smart-71817b5f-7a56-4047-90d9-6ec2be5eaba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148784662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.148784662
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.241744675
Short name T813
Test name
Test status
Simulation time 329757979 ps
CPU time 1.36 seconds
Started Jul 30 07:22:30 PM PDT 24
Finished Jul 30 07:22:31 PM PDT 24
Peak memory 201368 kb
Host smart-f04f93d7-3dfc-4f24-838b-1f1848eed952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241744675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.241744675
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1830266560
Short name T893
Test name
Test status
Simulation time 469833662 ps
CPU time 1.74 seconds
Started Jul 30 07:22:32 PM PDT 24
Finished Jul 30 07:22:34 PM PDT 24
Peak memory 201352 kb
Host smart-e2ef004d-8a8a-4095-a3af-31ee2d144a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830266560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1830266560
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1905159943
Short name T91
Test name
Test status
Simulation time 512172496 ps
CPU time 1.27 seconds
Started Jul 30 07:21:40 PM PDT 24
Finished Jul 30 07:21:41 PM PDT 24
Peak memory 201512 kb
Host smart-bb6afb4c-9e51-4332-9c00-58b9d4ea8570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905159943 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1905159943
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2056014139
Short name T132
Test name
Test status
Simulation time 353969111 ps
CPU time 1.57 seconds
Started Jul 30 07:21:38 PM PDT 24
Finished Jul 30 07:21:40 PM PDT 24
Peak memory 201540 kb
Host smart-478b8b67-598a-4936-be67-15720ccc9a30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056014139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2056014139
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.290313184
Short name T811
Test name
Test status
Simulation time 431346414 ps
CPU time 0.87 seconds
Started Jul 30 07:21:40 PM PDT 24
Finished Jul 30 07:21:41 PM PDT 24
Peak memory 201280 kb
Host smart-d07fefed-e239-4224-afd7-faf07bfdc523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290313184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.290313184
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2068774670
Short name T820
Test name
Test status
Simulation time 4055864607 ps
CPU time 15.59 seconds
Started Jul 30 07:21:39 PM PDT 24
Finished Jul 30 07:21:55 PM PDT 24
Peak memory 201596 kb
Host smart-fdb2b7a4-d415-48a8-a22f-fc2d996f595d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068774670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2068774670
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3181970908
Short name T838
Test name
Test status
Simulation time 578560540 ps
CPU time 1.78 seconds
Started Jul 30 07:21:37 PM PDT 24
Finished Jul 30 07:21:39 PM PDT 24
Peak memory 201700 kb
Host smart-bc0b3655-b241-4fe7-a8ce-a8318d500aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181970908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3181970908
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2870438739
Short name T72
Test name
Test status
Simulation time 4718193139 ps
CPU time 6.68 seconds
Started Jul 30 07:21:32 PM PDT 24
Finished Jul 30 07:21:39 PM PDT 24
Peak memory 201536 kb
Host smart-91356d4a-367f-400a-b124-6494751cb82b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870438739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2870438739
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3363779567
Short name T74
Test name
Test status
Simulation time 509872959 ps
CPU time 1.88 seconds
Started Jul 30 07:21:40 PM PDT 24
Finished Jul 30 07:21:42 PM PDT 24
Peak memory 201476 kb
Host smart-ec1ac79d-8d86-450b-b37a-d1a0f58fb6ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363779567 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3363779567
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.346096809
Short name T877
Test name
Test status
Simulation time 532660736 ps
CPU time 1.11 seconds
Started Jul 30 07:21:43 PM PDT 24
Finished Jul 30 07:21:44 PM PDT 24
Peak memory 201368 kb
Host smart-dccde10f-2f76-4fa9-98c6-ea46576ddafb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346096809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.346096809
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1398271430
Short name T909
Test name
Test status
Simulation time 444682951 ps
CPU time 0.88 seconds
Started Jul 30 07:21:40 PM PDT 24
Finished Jul 30 07:21:41 PM PDT 24
Peak memory 201340 kb
Host smart-1708c906-0d76-4cf0-862f-b985c9d5a140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398271430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1398271430
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.947165308
Short name T841
Test name
Test status
Simulation time 2591771714 ps
CPU time 2.17 seconds
Started Jul 30 07:21:41 PM PDT 24
Finished Jul 30 07:21:43 PM PDT 24
Peak memory 201448 kb
Host smart-995cb8a2-f3cc-4849-9241-95483f717e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947165308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.947165308
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1384933644
Short name T890
Test name
Test status
Simulation time 950899376 ps
CPU time 2.52 seconds
Started Jul 30 07:21:37 PM PDT 24
Finished Jul 30 07:21:40 PM PDT 24
Peak memory 201684 kb
Host smart-3837c955-930f-4a90-97dc-74540384a7be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384933644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1384933644
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.477015707
Short name T889
Test name
Test status
Simulation time 461848404 ps
CPU time 1.12 seconds
Started Jul 30 07:21:44 PM PDT 24
Finished Jul 30 07:21:45 PM PDT 24
Peak memory 201540 kb
Host smart-8a24de98-e105-49f5-b638-fe43b5eb0a5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477015707 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.477015707
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2365150521
Short name T918
Test name
Test status
Simulation time 391410122 ps
CPU time 0.78 seconds
Started Jul 30 07:21:45 PM PDT 24
Finished Jul 30 07:21:46 PM PDT 24
Peak memory 201368 kb
Host smart-9ca1ae4f-cdfc-4690-9bf8-c74912b86d22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365150521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2365150521
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3728772884
Short name T799
Test name
Test status
Simulation time 501461974 ps
CPU time 0.92 seconds
Started Jul 30 07:21:44 PM PDT 24
Finished Jul 30 07:21:45 PM PDT 24
Peak memory 201360 kb
Host smart-c334701e-0dbc-4256-9244-3400c4903346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728772884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3728772884
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.713112604
Short name T862
Test name
Test status
Simulation time 4816862207 ps
CPU time 11.44 seconds
Started Jul 30 07:21:43 PM PDT 24
Finished Jul 30 07:21:55 PM PDT 24
Peak memory 201648 kb
Host smart-7fb1ff4f-f785-48f9-9e8b-e04923051140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713112604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.713112604
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3298273610
Short name T82
Test name
Test status
Simulation time 1133247300 ps
CPU time 1.44 seconds
Started Jul 30 07:21:41 PM PDT 24
Finished Jul 30 07:21:42 PM PDT 24
Peak memory 201608 kb
Host smart-32fb2576-1fd7-4cac-8295-a24ca3116459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298273610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3298273610
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1393191838
Short name T321
Test name
Test status
Simulation time 8698424679 ps
CPU time 19.54 seconds
Started Jul 30 07:21:41 PM PDT 24
Finished Jul 30 07:22:00 PM PDT 24
Peak memory 201580 kb
Host smart-edbca5b4-1100-43b7-9a83-9f58cd5b83a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393191838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1393191838
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2188538892
Short name T828
Test name
Test status
Simulation time 416361285 ps
CPU time 1.22 seconds
Started Jul 30 07:21:48 PM PDT 24
Finished Jul 30 07:21:50 PM PDT 24
Peak memory 201456 kb
Host smart-ea7bbfc1-4019-435f-ad5e-af6004508e96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188538892 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2188538892
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.438367825
Short name T133
Test name
Test status
Simulation time 476262529 ps
CPU time 1.34 seconds
Started Jul 30 07:21:49 PM PDT 24
Finished Jul 30 07:21:51 PM PDT 24
Peak memory 201400 kb
Host smart-afaeee83-1e19-4827-ad14-d1ec3f13809c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438367825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.438367825
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2086929436
Short name T869
Test name
Test status
Simulation time 403556382 ps
CPU time 0.84 seconds
Started Jul 30 07:21:49 PM PDT 24
Finished Jul 30 07:21:50 PM PDT 24
Peak memory 201316 kb
Host smart-dd544ff9-88bb-4093-bcf1-7b96ee2a2b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086929436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2086929436
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1344296930
Short name T139
Test name
Test status
Simulation time 2781492742 ps
CPU time 1.59 seconds
Started Jul 30 07:21:50 PM PDT 24
Finished Jul 30 07:21:51 PM PDT 24
Peak memory 201416 kb
Host smart-5d5c192d-578e-4c23-a1c1-444a6edaff3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344296930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1344296930
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3244477526
Short name T833
Test name
Test status
Simulation time 4247816937 ps
CPU time 6.54 seconds
Started Jul 30 07:21:43 PM PDT 24
Finished Jul 30 07:21:50 PM PDT 24
Peak memory 201680 kb
Host smart-09c106a5-818c-4554-bdca-11bfa2bc4b33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244477526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3244477526
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.891865209
Short name T873
Test name
Test status
Simulation time 491164568 ps
CPU time 1.94 seconds
Started Jul 30 07:21:52 PM PDT 24
Finished Jul 30 07:21:54 PM PDT 24
Peak memory 201492 kb
Host smart-e0aa2772-b212-47b7-971b-4d0f2ab1909e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891865209 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.891865209
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1409121874
Short name T865
Test name
Test status
Simulation time 348539946 ps
CPU time 1.59 seconds
Started Jul 30 07:21:46 PM PDT 24
Finished Jul 30 07:21:48 PM PDT 24
Peak memory 201340 kb
Host smart-2d38494b-5144-402d-a29f-46d6a7270646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409121874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1409121874
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3349300994
Short name T895
Test name
Test status
Simulation time 452843002 ps
CPU time 0.86 seconds
Started Jul 30 07:21:47 PM PDT 24
Finished Jul 30 07:21:48 PM PDT 24
Peak memory 201356 kb
Host smart-73bf20ba-f240-4703-b10e-d60dff108fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349300994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3349300994
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1999259134
Short name T894
Test name
Test status
Simulation time 2314808958 ps
CPU time 2.15 seconds
Started Jul 30 07:21:49 PM PDT 24
Finished Jul 30 07:21:52 PM PDT 24
Peak memory 201420 kb
Host smart-125659ab-26fb-47e0-90b3-d4272f61aa3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999259134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1999259134
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3429144037
Short name T81
Test name
Test status
Simulation time 453031720 ps
CPU time 2.56 seconds
Started Jul 30 07:21:49 PM PDT 24
Finished Jul 30 07:21:52 PM PDT 24
Peak memory 201628 kb
Host smart-ac1351b9-5dc9-4e7e-9cf9-7125fc7370e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429144037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3429144037
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2727849760
Short name T860
Test name
Test status
Simulation time 8057274664 ps
CPU time 11 seconds
Started Jul 30 07:21:47 PM PDT 24
Finished Jul 30 07:21:58 PM PDT 24
Peak memory 201692 kb
Host smart-925e35f3-f711-43d5-b425-375bd4cd64f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727849760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2727849760
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.527252373
Short name T585
Test name
Test status
Simulation time 393232465 ps
CPU time 1.1 seconds
Started Jul 30 07:06:12 PM PDT 24
Finished Jul 30 07:06:14 PM PDT 24
Peak memory 201300 kb
Host smart-30d4b301-c905-4074-9dd3-f9177a11f2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527252373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.527252373
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2450954677
Short name T225
Test name
Test status
Simulation time 218841717522 ps
CPU time 515.32 seconds
Started Jul 30 07:05:56 PM PDT 24
Finished Jul 30 07:14:32 PM PDT 24
Peak memory 201444 kb
Host smart-8d58e5dd-8922-469c-963b-685c71d7bcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450954677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2450954677
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4141384089
Short name T264
Test name
Test status
Simulation time 495647200655 ps
CPU time 280 seconds
Started Jul 30 07:05:54 PM PDT 24
Finished Jul 30 07:10:34 PM PDT 24
Peak memory 201416 kb
Host smart-b5554d4d-b545-4082-b20a-caa36e112bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141384089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4141384089
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.769728561
Short name T339
Test name
Test status
Simulation time 321904075657 ps
CPU time 745.2 seconds
Started Jul 30 07:05:57 PM PDT 24
Finished Jul 30 07:18:22 PM PDT 24
Peak memory 201444 kb
Host smart-a71496fb-badc-4cb7-908c-b3200a0e5bee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=769728561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.769728561
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1976420280
Short name T728
Test name
Test status
Simulation time 496859155729 ps
CPU time 1220.02 seconds
Started Jul 30 07:05:57 PM PDT 24
Finished Jul 30 07:26:17 PM PDT 24
Peak memory 201440 kb
Host smart-3c2edf78-c5a5-432d-b9b7-dbdf941b55db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976420280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1976420280
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4267952048
Short name T680
Test name
Test status
Simulation time 330966894236 ps
CPU time 126.65 seconds
Started Jul 30 07:05:53 PM PDT 24
Finished Jul 30 07:08:00 PM PDT 24
Peak memory 201504 kb
Host smart-9a305459-8afe-4274-8951-fd987a13f922
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267952048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4267952048
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2462552606
Short name T699
Test name
Test status
Simulation time 162232066703 ps
CPU time 44.2 seconds
Started Jul 30 07:05:56 PM PDT 24
Finished Jul 30 07:06:41 PM PDT 24
Peak memory 201448 kb
Host smart-d8f05928-5fe1-4f46-a769-0558d0d166da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462552606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2462552606
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2470702292
Short name T417
Test name
Test status
Simulation time 623359538876 ps
CPU time 324.18 seconds
Started Jul 30 07:05:56 PM PDT 24
Finished Jul 30 07:11:21 PM PDT 24
Peak memory 201460 kb
Host smart-dd86055a-cdb3-4d33-9452-155438da69b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470702292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2470702292
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2929936524
Short name T732
Test name
Test status
Simulation time 37568326289 ps
CPU time 17.69 seconds
Started Jul 30 07:06:01 PM PDT 24
Finished Jul 30 07:06:18 PM PDT 24
Peak memory 201336 kb
Host smart-8c71fdc2-24d5-48ca-b964-33e308ee76b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929936524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2929936524
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2392656563
Short name T50
Test name
Test status
Simulation time 4669741891 ps
CPU time 3.54 seconds
Started Jul 30 07:05:58 PM PDT 24
Finished Jul 30 07:06:01 PM PDT 24
Peak memory 201284 kb
Host smart-9120c9db-0127-4453-8661-891f682dd167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392656563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2392656563
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3547769931
Short name T93
Test name
Test status
Simulation time 8346321537 ps
CPU time 5.37 seconds
Started Jul 30 07:06:10 PM PDT 24
Finished Jul 30 07:06:15 PM PDT 24
Peak memory 217780 kb
Host smart-405b77b0-d9eb-4ef3-9d32-250298523323
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547769931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3547769931
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3616513677
Short name T715
Test name
Test status
Simulation time 5972641998 ps
CPU time 4.3 seconds
Started Jul 30 07:05:55 PM PDT 24
Finished Jul 30 07:05:59 PM PDT 24
Peak memory 201376 kb
Host smart-5fca43b0-0683-4c2f-a7a9-4e2524dd88fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616513677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3616513677
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2088107247
Short name T196
Test name
Test status
Simulation time 1108524386597 ps
CPU time 1464.74 seconds
Started Jul 30 07:06:07 PM PDT 24
Finished Jul 30 07:30:32 PM PDT 24
Peak memory 210100 kb
Host smart-feea21b6-2ccb-48e7-8feb-50455470a2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088107247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2088107247
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1911283722
Short name T102
Test name
Test status
Simulation time 43834768103 ps
CPU time 125.18 seconds
Started Jul 30 07:06:07 PM PDT 24
Finished Jul 30 07:08:12 PM PDT 24
Peak memory 218348 kb
Host smart-c083b21d-f7a9-432e-8c80-205991ade071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911283722 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1911283722
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1201738001
Short name T518
Test name
Test status
Simulation time 517933545 ps
CPU time 1.42 seconds
Started Jul 30 07:06:39 PM PDT 24
Finished Jul 30 07:06:41 PM PDT 24
Peak memory 201228 kb
Host smart-3b602ee9-65f4-46dc-8bee-6ef1e9557eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201738001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1201738001
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1649552677
Short name T567
Test name
Test status
Simulation time 168682453797 ps
CPU time 205.75 seconds
Started Jul 30 07:06:22 PM PDT 24
Finished Jul 30 07:09:48 PM PDT 24
Peak memory 201428 kb
Host smart-5826b69e-ee7a-45a0-91c5-18fc18b574e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649552677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1649552677
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2123062276
Short name T570
Test name
Test status
Simulation time 506674524821 ps
CPU time 1185.58 seconds
Started Jul 30 07:06:16 PM PDT 24
Finished Jul 30 07:26:02 PM PDT 24
Peak memory 201384 kb
Host smart-fa08f001-70c6-45d6-9658-e04fef40cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123062276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2123062276
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1055491516
Short name T10
Test name
Test status
Simulation time 329214801910 ps
CPU time 181.39 seconds
Started Jul 30 07:06:23 PM PDT 24
Finished Jul 30 07:09:24 PM PDT 24
Peak memory 201448 kb
Host smart-6e7d1d3f-6160-4e6a-b52a-7b18b16f3532
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055491516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1055491516
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3996204805
Short name T577
Test name
Test status
Simulation time 178296908270 ps
CPU time 408.59 seconds
Started Jul 30 07:06:29 PM PDT 24
Finished Jul 30 07:13:18 PM PDT 24
Peak memory 201416 kb
Host smart-751f3125-e5e9-411a-a037-6abd50249a5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996204805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3996204805
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1897799186
Short name T541
Test name
Test status
Simulation time 205337259579 ps
CPU time 124.35 seconds
Started Jul 30 07:06:20 PM PDT 24
Finished Jul 30 07:08:25 PM PDT 24
Peak memory 201436 kb
Host smart-2f164cc2-c90e-4573-aaa9-5c7470bd3b6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897799186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1897799186
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3181684824
Short name T357
Test name
Test status
Simulation time 42664131536 ps
CPU time 25.72 seconds
Started Jul 30 07:06:30 PM PDT 24
Finished Jul 30 07:06:56 PM PDT 24
Peak memory 201384 kb
Host smart-c27da287-38f9-4c92-86cf-df83bff7f858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181684824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3181684824
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4110002363
Short name T334
Test name
Test status
Simulation time 4155820460 ps
CPU time 10.11 seconds
Started Jul 30 07:06:31 PM PDT 24
Finished Jul 30 07:06:41 PM PDT 24
Peak memory 201348 kb
Host smart-fc69cce9-247c-447e-b1bd-e3656f43f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110002363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4110002363
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2460315529
Short name T757
Test name
Test status
Simulation time 5823552648 ps
CPU time 14.19 seconds
Started Jul 30 07:06:17 PM PDT 24
Finished Jul 30 07:06:32 PM PDT 24
Peak memory 201512 kb
Host smart-af075471-b905-4e22-8cfe-50f7252a5aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460315529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2460315529
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1200780118
Short name T677
Test name
Test status
Simulation time 287812275 ps
CPU time 1.3 seconds
Started Jul 30 07:09:44 PM PDT 24
Finished Jul 30 07:09:45 PM PDT 24
Peak memory 201240 kb
Host smart-145b0c15-4295-4b13-a3f1-3a9558127154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200780118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1200780118
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.79380062
Short name T703
Test name
Test status
Simulation time 171579475651 ps
CPU time 192.22 seconds
Started Jul 30 07:09:34 PM PDT 24
Finished Jul 30 07:12:46 PM PDT 24
Peak memory 201372 kb
Host smart-6c66033c-fc0f-442c-bb86-179d383094c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79380062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gatin
g.79380062
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.22061903
Short name T448
Test name
Test status
Simulation time 201354863887 ps
CPU time 459.06 seconds
Started Jul 30 07:09:38 PM PDT 24
Finished Jul 30 07:17:17 PM PDT 24
Peak memory 201488 kb
Host smart-2194bdef-867f-4917-b025-db112a6c04e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22061903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.22061903
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1709559088
Short name T249
Test name
Test status
Simulation time 498380953502 ps
CPU time 307.18 seconds
Started Jul 30 07:09:28 PM PDT 24
Finished Jul 30 07:14:35 PM PDT 24
Peak memory 201496 kb
Host smart-eebf47e1-0cbb-470d-bb00-bb5a23a141ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709559088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1709559088
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1567696602
Short name T694
Test name
Test status
Simulation time 164747312552 ps
CPU time 250.7 seconds
Started Jul 30 07:09:31 PM PDT 24
Finished Jul 30 07:13:42 PM PDT 24
Peak memory 201408 kb
Host smart-c065fea7-c16b-4124-9f06-1c73b4a320fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567696602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1567696602
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3534964027
Short name T758
Test name
Test status
Simulation time 328832869035 ps
CPU time 182.25 seconds
Started Jul 30 07:09:26 PM PDT 24
Finished Jul 30 07:12:28 PM PDT 24
Peak memory 201440 kb
Host smart-4815dc7e-f379-44f2-b658-4a77edb7578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534964027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3534964027
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.756632875
Short name T583
Test name
Test status
Simulation time 169655907917 ps
CPU time 378.19 seconds
Started Jul 30 07:09:28 PM PDT 24
Finished Jul 30 07:15:47 PM PDT 24
Peak memory 201448 kb
Host smart-7534b8bd-0f43-4b07-8f95-10bb6218a35f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=756632875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.756632875
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3122598668
Short name T189
Test name
Test status
Simulation time 391893712167 ps
CPU time 226.89 seconds
Started Jul 30 07:09:29 PM PDT 24
Finished Jul 30 07:13:16 PM PDT 24
Peak memory 201448 kb
Host smart-1afd4e9c-ec9f-40bb-95f4-f444d7068f98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122598668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3122598668
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3241578201
Short name T564
Test name
Test status
Simulation time 140864152361 ps
CPU time 413.8 seconds
Started Jul 30 07:09:40 PM PDT 24
Finished Jul 30 07:16:34 PM PDT 24
Peak memory 201808 kb
Host smart-ca735e6f-11e7-4d7d-a0b0-6a3f0e5243bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241578201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3241578201
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1221873781
Short name T514
Test name
Test status
Simulation time 37093519194 ps
CPU time 22.86 seconds
Started Jul 30 07:09:37 PM PDT 24
Finished Jul 30 07:10:00 PM PDT 24
Peak memory 201336 kb
Host smart-886eddeb-6dbe-45d3-b60e-7018bf439308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221873781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1221873781
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.886313203
Short name T614
Test name
Test status
Simulation time 4583810389 ps
CPU time 3.44 seconds
Started Jul 30 07:09:37 PM PDT 24
Finished Jul 30 07:09:41 PM PDT 24
Peak memory 201296 kb
Host smart-374680ca-d028-448e-aef7-690a088ca521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886313203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.886313203
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3856596850
Short name T199
Test name
Test status
Simulation time 5991069509 ps
CPU time 13.64 seconds
Started Jul 30 07:09:23 PM PDT 24
Finished Jul 30 07:09:37 PM PDT 24
Peak memory 201368 kb
Host smart-814a8234-1436-40bb-811a-1bf1688bb09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856596850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3856596850
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.4003826409
Short name T517
Test name
Test status
Simulation time 200542770208 ps
CPU time 440.38 seconds
Started Jul 30 07:09:45 PM PDT 24
Finished Jul 30 07:17:06 PM PDT 24
Peak memory 201476 kb
Host smart-72c29354-d525-450b-ab1c-bb9311853724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003826409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.4003826409
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3453624577
Short name T522
Test name
Test status
Simulation time 379485813 ps
CPU time 0.81 seconds
Started Jul 30 07:09:59 PM PDT 24
Finished Jul 30 07:10:00 PM PDT 24
Peak memory 201260 kb
Host smart-844b9e4e-a17c-4522-9465-9ac7a019898a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453624577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3453624577
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3329759491
Short name T691
Test name
Test status
Simulation time 505775579023 ps
CPU time 109.92 seconds
Started Jul 30 07:09:51 PM PDT 24
Finished Jul 30 07:11:41 PM PDT 24
Peak memory 201452 kb
Host smart-95ce98aa-bab2-49a3-94b9-a8ef0bdf1ec2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329759491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3329759491
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3671464891
Short name T152
Test name
Test status
Simulation time 521976829396 ps
CPU time 607.25 seconds
Started Jul 30 07:09:50 PM PDT 24
Finished Jul 30 07:19:57 PM PDT 24
Peak memory 201436 kb
Host smart-cbb7ae6e-2162-44b2-995c-4a079c7806a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671464891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3671464891
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3509899665
Short name T563
Test name
Test status
Simulation time 501081500124 ps
CPU time 347.27 seconds
Started Jul 30 07:09:47 PM PDT 24
Finished Jul 30 07:15:35 PM PDT 24
Peak memory 201468 kb
Host smart-6fdb2c78-e248-4ce7-b629-bfcdd1461b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509899665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3509899665
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3856686329
Short name T505
Test name
Test status
Simulation time 165370268681 ps
CPU time 108.18 seconds
Started Jul 30 07:09:50 PM PDT 24
Finished Jul 30 07:11:39 PM PDT 24
Peak memory 201444 kb
Host smart-4c94b0b4-59e5-4e93-9da2-01d7e602bf82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856686329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3856686329
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3533532387
Short name T158
Test name
Test status
Simulation time 168752098399 ps
CPU time 387.62 seconds
Started Jul 30 07:09:47 PM PDT 24
Finished Jul 30 07:16:15 PM PDT 24
Peak memory 201496 kb
Host smart-831fcb53-4b20-4d64-a195-692219c72cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533532387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3533532387
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1929917426
Short name T658
Test name
Test status
Simulation time 324794877726 ps
CPU time 733.17 seconds
Started Jul 30 07:09:48 PM PDT 24
Finished Jul 30 07:22:01 PM PDT 24
Peak memory 201456 kb
Host smart-504dcbe1-a9ba-4cb0-a5bd-a07e4eb7a76d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929917426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1929917426
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2371535045
Short name T404
Test name
Test status
Simulation time 600814366901 ps
CPU time 685.84 seconds
Started Jul 30 07:09:51 PM PDT 24
Finished Jul 30 07:21:17 PM PDT 24
Peak memory 201428 kb
Host smart-805cec9c-64d5-4166-a17b-2573c840f2de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371535045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2371535045
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3553166572
Short name T215
Test name
Test status
Simulation time 96550522327 ps
CPU time 323.76 seconds
Started Jul 30 07:09:57 PM PDT 24
Finished Jul 30 07:15:21 PM PDT 24
Peak memory 201884 kb
Host smart-40a6295c-de49-463f-8168-369a1aa58542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553166572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3553166572
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1619520341
Short name T331
Test name
Test status
Simulation time 25838553763 ps
CPU time 56.5 seconds
Started Jul 30 07:09:54 PM PDT 24
Finished Jul 30 07:10:51 PM PDT 24
Peak memory 201364 kb
Host smart-81495f47-273d-4cd7-9cdd-360d0fe19c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619520341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1619520341
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2193996959
Short name T484
Test name
Test status
Simulation time 3160748004 ps
CPU time 2.34 seconds
Started Jul 30 07:09:56 PM PDT 24
Finished Jul 30 07:09:59 PM PDT 24
Peak memory 201356 kb
Host smart-cd08294d-bd28-448c-93c8-07e45ef46b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193996959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2193996959
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1888578937
Short name T515
Test name
Test status
Simulation time 5820261208 ps
CPU time 2.83 seconds
Started Jul 30 07:09:47 PM PDT 24
Finished Jul 30 07:09:50 PM PDT 24
Peak memory 201360 kb
Host smart-4e496885-5aa4-479b-b80e-1be34365d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888578937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1888578937
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.17965377
Short name T258
Test name
Test status
Simulation time 329354540359 ps
CPU time 191.45 seconds
Started Jul 30 07:09:58 PM PDT 24
Finished Jul 30 07:13:10 PM PDT 24
Peak memory 201556 kb
Host smart-c46bffee-04e8-40af-a2a3-c074dd196c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17965377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.17965377
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2722524672
Short name T640
Test name
Test status
Simulation time 189739454970 ps
CPU time 59.92 seconds
Started Jul 30 07:09:58 PM PDT 24
Finished Jul 30 07:10:58 PM PDT 24
Peak memory 209824 kb
Host smart-75391bf0-9627-435f-8e09-095bc4f2e428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722524672 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2722524672
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3780677484
Short name T429
Test name
Test status
Simulation time 386996634 ps
CPU time 0.83 seconds
Started Jul 30 07:10:19 PM PDT 24
Finished Jul 30 07:10:20 PM PDT 24
Peak memory 201144 kb
Host smart-38ebed89-46f8-47df-82ea-c30bf12efb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780677484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3780677484
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.4257449501
Short name T69
Test name
Test status
Simulation time 192200766301 ps
CPU time 420.57 seconds
Started Jul 30 07:10:04 PM PDT 24
Finished Jul 30 07:17:05 PM PDT 24
Peak memory 201668 kb
Host smart-42dc91c9-e1d2-4f85-91fa-9b9fc640515e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257449501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.4257449501
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3845842767
Short name T254
Test name
Test status
Simulation time 161157352254 ps
CPU time 139.23 seconds
Started Jul 30 07:10:09 PM PDT 24
Finished Jul 30 07:12:29 PM PDT 24
Peak memory 201496 kb
Host smart-60932a9d-0cc3-4bd1-a5d0-7b00c6e0c718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845842767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3845842767
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3080268849
Short name T438
Test name
Test status
Simulation time 494688674974 ps
CPU time 472.82 seconds
Started Jul 30 07:10:02 PM PDT 24
Finished Jul 30 07:17:54 PM PDT 24
Peak memory 201276 kb
Host smart-aac23cc4-0622-4552-a8a8-f6c250274fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080268849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3080268849
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.653770777
Short name T600
Test name
Test status
Simulation time 161569270963 ps
CPU time 378.87 seconds
Started Jul 30 07:10:06 PM PDT 24
Finished Jul 30 07:16:25 PM PDT 24
Peak memory 201528 kb
Host smart-f395577c-b289-45bf-b395-7f71bfdd86eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653770777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.653770777
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4238388170
Short name T142
Test name
Test status
Simulation time 332186648719 ps
CPU time 77.06 seconds
Started Jul 30 07:10:01 PM PDT 24
Finished Jul 30 07:11:18 PM PDT 24
Peak memory 201412 kb
Host smart-ce4b2ded-db8e-4c28-8c3d-0e2344415ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238388170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4238388170
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3429988067
Short name T395
Test name
Test status
Simulation time 164073379268 ps
CPU time 372.4 seconds
Started Jul 30 07:10:03 PM PDT 24
Finished Jul 30 07:16:15 PM PDT 24
Peak memory 201452 kb
Host smart-154b6656-cc41-4280-8f93-cc0deaa31780
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429988067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3429988067
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1144647636
Short name T271
Test name
Test status
Simulation time 380380919266 ps
CPU time 225.44 seconds
Started Jul 30 07:10:04 PM PDT 24
Finished Jul 30 07:13:50 PM PDT 24
Peak memory 201460 kb
Host smart-a900a739-e695-4ac6-ba49-f7a2d76da101
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144647636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1144647636
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1467222135
Short name T709
Test name
Test status
Simulation time 622182439065 ps
CPU time 1393.32 seconds
Started Jul 30 07:10:04 PM PDT 24
Finished Jul 30 07:33:18 PM PDT 24
Peak memory 201432 kb
Host smart-0f2195ac-c35d-4c23-b321-4eb3c35eade4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467222135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1467222135
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.55205150
Short name T382
Test name
Test status
Simulation time 131047637475 ps
CPU time 705.12 seconds
Started Jul 30 07:10:12 PM PDT 24
Finished Jul 30 07:21:58 PM PDT 24
Peak memory 201948 kb
Host smart-f89fd4dc-4340-4df2-82ed-62c23a0792d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55205150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.55205150
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.704794649
Short name T519
Test name
Test status
Simulation time 37316131689 ps
CPU time 83.46 seconds
Started Jul 30 07:10:13 PM PDT 24
Finished Jul 30 07:11:36 PM PDT 24
Peak memory 201344 kb
Host smart-4608d2db-650e-4e79-9884-53d3c4b9b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704794649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.704794649
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.634402877
Short name T364
Test name
Test status
Simulation time 3446760494 ps
CPU time 2.71 seconds
Started Jul 30 07:10:12 PM PDT 24
Finished Jul 30 07:10:15 PM PDT 24
Peak memory 201364 kb
Host smart-ad7ab952-9410-4ddb-b3e3-5868ecb09349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634402877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.634402877
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4243981582
Short name T45
Test name
Test status
Simulation time 6134504517 ps
CPU time 13.59 seconds
Started Jul 30 07:09:58 PM PDT 24
Finished Jul 30 07:10:11 PM PDT 24
Peak memory 201348 kb
Host smart-8b2bf0c2-92da-4053-b171-c95fe648471f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243981582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4243981582
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3097391546
Short name T224
Test name
Test status
Simulation time 328912630676 ps
CPU time 740.22 seconds
Started Jul 30 07:10:15 PM PDT 24
Finished Jul 30 07:22:36 PM PDT 24
Peak memory 201456 kb
Host smart-af2b1b6b-4473-4075-a2c5-1a6ffe797d4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097391546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3097391546
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1242555911
Short name T104
Test name
Test status
Simulation time 336087898355 ps
CPU time 404.26 seconds
Started Jul 30 07:10:13 PM PDT 24
Finished Jul 30 07:16:57 PM PDT 24
Peak memory 210208 kb
Host smart-86ab1c1f-7748-4aec-93fa-3f7a81938ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242555911 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1242555911
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1877134794
Short name T722
Test name
Test status
Simulation time 403684853 ps
CPU time 0.74 seconds
Started Jul 30 07:10:46 PM PDT 24
Finished Jul 30 07:10:47 PM PDT 24
Peak memory 201200 kb
Host smart-72c45781-169e-4a20-b131-243e95e35994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877134794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1877134794
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1070200631
Short name T217
Test name
Test status
Simulation time 166672183852 ps
CPU time 372.96 seconds
Started Jul 30 07:10:19 PM PDT 24
Finished Jul 30 07:16:32 PM PDT 24
Peak memory 201448 kb
Host smart-7e40092c-d966-4676-b528-02592f953adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070200631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1070200631
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3870251122
Short name T628
Test name
Test status
Simulation time 488226247013 ps
CPU time 530.28 seconds
Started Jul 30 07:10:18 PM PDT 24
Finished Jul 30 07:19:08 PM PDT 24
Peak memory 201512 kb
Host smart-fafb11f2-9ee1-4858-b86c-5d76daed281a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870251122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3870251122
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1460809930
Short name T605
Test name
Test status
Simulation time 488827710715 ps
CPU time 1158.85 seconds
Started Jul 30 07:10:20 PM PDT 24
Finished Jul 30 07:29:39 PM PDT 24
Peak memory 201456 kb
Host smart-412ddb4c-fe8a-423e-8805-69f1b064f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460809930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1460809930
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3389424159
Short name T491
Test name
Test status
Simulation time 320219457047 ps
CPU time 97.26 seconds
Started Jul 30 07:10:19 PM PDT 24
Finished Jul 30 07:11:57 PM PDT 24
Peak memory 201472 kb
Host smart-9dd4798c-1b9d-47ca-b46f-2f1f57985a4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389424159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3389424159
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3931876164
Short name T606
Test name
Test status
Simulation time 197817690411 ps
CPU time 242.2 seconds
Started Jul 30 07:10:27 PM PDT 24
Finished Jul 30 07:14:29 PM PDT 24
Peak memory 201464 kb
Host smart-b9c72a9e-8151-4d13-86ce-a672cbe26e9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931876164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3931876164
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2407001937
Short name T737
Test name
Test status
Simulation time 90597491364 ps
CPU time 437.06 seconds
Started Jul 30 07:10:39 PM PDT 24
Finished Jul 30 07:17:56 PM PDT 24
Peak memory 201880 kb
Host smart-55365f56-2f54-43a2-9f5c-7569d63222f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407001937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2407001937
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1890604540
Short name T463
Test name
Test status
Simulation time 38321890807 ps
CPU time 23.57 seconds
Started Jul 30 07:10:33 PM PDT 24
Finished Jul 30 07:10:57 PM PDT 24
Peak memory 201336 kb
Host smart-92e8a15f-2085-458e-9672-7caa2675f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890604540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1890604540
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1885712950
Short name T373
Test name
Test status
Simulation time 4555464618 ps
CPU time 4.41 seconds
Started Jul 30 07:10:32 PM PDT 24
Finished Jul 30 07:10:37 PM PDT 24
Peak memory 201392 kb
Host smart-61bc96ad-92d5-4509-b76a-781c2a637c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885712950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1885712950
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1940047896
Short name T487
Test name
Test status
Simulation time 5712127466 ps
CPU time 12.89 seconds
Started Jul 30 07:10:19 PM PDT 24
Finished Jul 30 07:10:32 PM PDT 24
Peak memory 201372 kb
Host smart-8e970323-8a7b-4d1b-8eb2-32aaa44f7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940047896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1940047896
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1357494628
Short name T240
Test name
Test status
Simulation time 217385038504 ps
CPU time 96.7 seconds
Started Jul 30 07:10:46 PM PDT 24
Finished Jul 30 07:12:23 PM PDT 24
Peak memory 201504 kb
Host smart-3b4159ca-d77e-4bb8-b5f8-71ed9f4d052d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357494628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1357494628
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2490529416
Short name T744
Test name
Test status
Simulation time 477597452 ps
CPU time 1.27 seconds
Started Jul 30 07:11:12 PM PDT 24
Finished Jul 30 07:11:13 PM PDT 24
Peak memory 201228 kb
Host smart-dcecb008-7b8c-45d7-8eda-9bc5b2820d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490529416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2490529416
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.812687264
Short name T157
Test name
Test status
Simulation time 540782529888 ps
CPU time 589.47 seconds
Started Jul 30 07:10:59 PM PDT 24
Finished Jul 30 07:20:49 PM PDT 24
Peak memory 201360 kb
Host smart-af293b8e-2219-4983-b146-ee358b0c96f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812687264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.812687264
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3993562857
Short name T747
Test name
Test status
Simulation time 338249605444 ps
CPU time 205.97 seconds
Started Jul 30 07:11:04 PM PDT 24
Finished Jul 30 07:14:30 PM PDT 24
Peak memory 201408 kb
Host smart-d5a6bf99-f3c7-45da-bb8c-66a6a6b36572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993562857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3993562857
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3191426100
Short name T464
Test name
Test status
Simulation time 167556149168 ps
CPU time 381.71 seconds
Started Jul 30 07:10:56 PM PDT 24
Finished Jul 30 07:17:17 PM PDT 24
Peak memory 201276 kb
Host smart-7e66ad60-d192-4594-9cbc-870c12ebd129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191426100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3191426100
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2809652895
Short name T627
Test name
Test status
Simulation time 488936990385 ps
CPU time 540.44 seconds
Started Jul 30 07:10:54 PM PDT 24
Finished Jul 30 07:19:55 PM PDT 24
Peak memory 201540 kb
Host smart-ce9d9fef-dd29-4e27-ab27-ad0dd745ae00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809652895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2809652895
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1161917814
Short name T179
Test name
Test status
Simulation time 509630653517 ps
CPU time 123.37 seconds
Started Jul 30 07:10:51 PM PDT 24
Finished Jul 30 07:12:54 PM PDT 24
Peak memory 201428 kb
Host smart-b02da303-e0df-4763-b277-ecb3f5845852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161917814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1161917814
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.279273631
Short name T444
Test name
Test status
Simulation time 162049995735 ps
CPU time 90.59 seconds
Started Jul 30 07:10:50 PM PDT 24
Finished Jul 30 07:12:21 PM PDT 24
Peak memory 201424 kb
Host smart-efffbf6f-d6c1-498b-8f2c-ce0ea021460a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=279273631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.279273631
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2368486694
Short name T420
Test name
Test status
Simulation time 395033543679 ps
CPU time 890.74 seconds
Started Jul 30 07:10:56 PM PDT 24
Finished Jul 30 07:25:47 PM PDT 24
Peak memory 201452 kb
Host smart-7534f46e-dc4a-474d-97a2-93d27666eaae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368486694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2368486694
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.175011569
Short name T603
Test name
Test status
Simulation time 80775729523 ps
CPU time 286.16 seconds
Started Jul 30 07:11:08 PM PDT 24
Finished Jul 30 07:15:54 PM PDT 24
Peak memory 201828 kb
Host smart-6b9b317d-7a08-4131-9b44-8c946fbb2915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175011569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.175011569
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3898797633
Short name T340
Test name
Test status
Simulation time 44305000785 ps
CPU time 98.31 seconds
Started Jul 30 07:11:07 PM PDT 24
Finished Jul 30 07:12:45 PM PDT 24
Peak memory 201372 kb
Host smart-5e826e96-063d-4b7b-9052-e469b498a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898797633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3898797633
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2160934572
Short name T341
Test name
Test status
Simulation time 4089720087 ps
CPU time 10.53 seconds
Started Jul 30 07:11:05 PM PDT 24
Finished Jul 30 07:11:16 PM PDT 24
Peak memory 201388 kb
Host smart-2deeb201-742e-473c-93bc-c917ce48a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160934572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2160934572
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3974615498
Short name T595
Test name
Test status
Simulation time 5790410891 ps
CPU time 2.36 seconds
Started Jul 30 07:10:48 PM PDT 24
Finished Jul 30 07:10:50 PM PDT 24
Peak memory 201364 kb
Host smart-a9530fdd-9984-4d20-b1df-b5e44bd5360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974615498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3974615498
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1591810424
Short name T646
Test name
Test status
Simulation time 364686482951 ps
CPU time 218.53 seconds
Started Jul 30 07:11:07 PM PDT 24
Finished Jul 30 07:14:46 PM PDT 24
Peak memory 201484 kb
Host smart-ce0a85c5-ef4d-473c-873f-df9267cf9b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591810424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1591810424
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1470376603
Short name T698
Test name
Test status
Simulation time 166302484996 ps
CPU time 92.32 seconds
Started Jul 30 07:11:22 PM PDT 24
Finished Jul 30 07:12:55 PM PDT 24
Peak memory 201416 kb
Host smart-0b039fb2-1e0a-4823-af66-b10b79db4119
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470376603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1470376603
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3185737468
Short name T233
Test name
Test status
Simulation time 162996623753 ps
CPU time 330.57 seconds
Started Jul 30 07:11:10 PM PDT 24
Finished Jul 30 07:16:41 PM PDT 24
Peak memory 201444 kb
Host smart-44615fc3-153f-4aad-bb5a-0cc57b052562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185737468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3185737468
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1783608498
Short name T384
Test name
Test status
Simulation time 321565242068 ps
CPU time 690.24 seconds
Started Jul 30 07:11:15 PM PDT 24
Finished Jul 30 07:22:46 PM PDT 24
Peak memory 201476 kb
Host smart-ce5e749c-c7e7-4ea0-832b-54d876f18699
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783608498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1783608498
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.731043744
Short name T644
Test name
Test status
Simulation time 169206842578 ps
CPU time 98.87 seconds
Started Jul 30 07:11:12 PM PDT 24
Finished Jul 30 07:12:51 PM PDT 24
Peak memory 201444 kb
Host smart-00919f02-c216-4076-a335-af99dd8a1cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731043744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.731043744
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.13392858
Short name T345
Test name
Test status
Simulation time 502174785323 ps
CPU time 1230.05 seconds
Started Jul 30 07:11:11 PM PDT 24
Finished Jul 30 07:31:41 PM PDT 24
Peak memory 201452 kb
Host smart-becb3348-0b7d-4fc7-9faa-1da13b2e4024
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=13392858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed
.13392858
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.662970698
Short name T164
Test name
Test status
Simulation time 198694424993 ps
CPU time 206.46 seconds
Started Jul 30 07:11:19 PM PDT 24
Finished Jul 30 07:14:46 PM PDT 24
Peak memory 201420 kb
Host smart-2fcb768e-6f66-4f32-b949-0e7efe6cfc10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662970698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.662970698
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.209151337
Short name T469
Test name
Test status
Simulation time 101134045950 ps
CPU time 349.65 seconds
Started Jul 30 07:11:31 PM PDT 24
Finished Jul 30 07:17:20 PM PDT 24
Peak memory 201904 kb
Host smart-cb5d9ff4-d174-4b54-96e4-1a40ad42aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209151337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.209151337
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1145969957
Short name T508
Test name
Test status
Simulation time 25647135605 ps
CPU time 15.88 seconds
Started Jul 30 07:11:31 PM PDT 24
Finished Jul 30 07:11:47 PM PDT 24
Peak memory 201364 kb
Host smart-90228f6b-d237-4d6c-87b5-f022f4427cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145969957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1145969957
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.40566708
Short name T561
Test name
Test status
Simulation time 3039333913 ps
CPU time 7.63 seconds
Started Jul 30 07:11:27 PM PDT 24
Finished Jul 30 07:11:34 PM PDT 24
Peak memory 201340 kb
Host smart-9838a71f-2863-4115-8896-f275b29e1e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40566708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.40566708
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1780559031
Short name T762
Test name
Test status
Simulation time 5739324182 ps
CPU time 3.76 seconds
Started Jul 30 07:11:13 PM PDT 24
Finished Jul 30 07:11:17 PM PDT 24
Peak memory 201372 kb
Host smart-830a4db4-7001-41cf-b094-1db3f35511f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780559031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1780559031
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2912964741
Short name T675
Test name
Test status
Simulation time 374673119574 ps
CPU time 51.02 seconds
Started Jul 30 07:11:35 PM PDT 24
Finished Jul 30 07:12:26 PM PDT 24
Peak memory 201444 kb
Host smart-f7efaded-2adb-4ab4-a3b7-0b2e89768624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912964741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2912964741
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.558214385
Short name T105
Test name
Test status
Simulation time 198284576440 ps
CPU time 149.49 seconds
Started Jul 30 07:11:31 PM PDT 24
Finished Jul 30 07:14:01 PM PDT 24
Peak memory 210200 kb
Host smart-4028784d-e2cc-420b-8e0d-01ad62ca3278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558214385 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.558214385
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1261208238
Short name T682
Test name
Test status
Simulation time 490151885 ps
CPU time 1.19 seconds
Started Jul 30 07:11:50 PM PDT 24
Finished Jul 30 07:11:52 PM PDT 24
Peak memory 201168 kb
Host smart-d473b275-68f3-44d5-9d40-d3b21d81e255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261208238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1261208238
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.296356512
Short name T678
Test name
Test status
Simulation time 514162195408 ps
CPU time 288.26 seconds
Started Jul 30 07:11:41 PM PDT 24
Finished Jul 30 07:16:29 PM PDT 24
Peak memory 201428 kb
Host smart-3ef4df3e-cb74-4c47-bc00-f96f27ab6be0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296356512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.296356512
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2497529395
Short name T317
Test name
Test status
Simulation time 165132730438 ps
CPU time 382.01 seconds
Started Jul 30 07:11:35 PM PDT 24
Finished Jul 30 07:17:57 PM PDT 24
Peak memory 201452 kb
Host smart-a68bce2a-325e-4333-94cc-e3082b2893ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497529395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2497529395
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2009837671
Short name T141
Test name
Test status
Simulation time 163977184757 ps
CPU time 178.63 seconds
Started Jul 30 07:11:36 PM PDT 24
Finished Jul 30 07:14:35 PM PDT 24
Peak memory 201480 kb
Host smart-7fa94db9-4195-4a6d-9907-523618df771c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009837671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2009837671
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.747508860
Short name T741
Test name
Test status
Simulation time 171651971787 ps
CPU time 204.42 seconds
Started Jul 30 07:11:32 PM PDT 24
Finished Jul 30 07:14:57 PM PDT 24
Peak memory 201492 kb
Host smart-403ed648-f388-43c3-96ef-a5713bd98673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747508860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.747508860
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.700725059
Short name T49
Test name
Test status
Simulation time 162132651196 ps
CPU time 71.84 seconds
Started Jul 30 07:11:35 PM PDT 24
Finished Jul 30 07:12:47 PM PDT 24
Peak memory 201456 kb
Host smart-9e8e61e6-c71a-49c3-8069-3845c941371f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=700725059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.700725059
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2936214800
Short name T616
Test name
Test status
Simulation time 429384463407 ps
CPU time 354.67 seconds
Started Jul 30 07:11:39 PM PDT 24
Finished Jul 30 07:17:33 PM PDT 24
Peak memory 201444 kb
Host smart-fd3332c4-e8b6-47f7-b226-3c36bc7a2113
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936214800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2936214800
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.720491953
Short name T457
Test name
Test status
Simulation time 618346015467 ps
CPU time 660.57 seconds
Started Jul 30 07:11:39 PM PDT 24
Finished Jul 30 07:22:40 PM PDT 24
Peak memory 201428 kb
Host smart-b47588ea-5889-4adc-89aa-cda231cf1919
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720491953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.720491953
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.395761771
Short name T354
Test name
Test status
Simulation time 35448796645 ps
CPU time 70.21 seconds
Started Jul 30 07:11:47 PM PDT 24
Finished Jul 30 07:12:57 PM PDT 24
Peak memory 201392 kb
Host smart-73849267-33ea-4530-8af8-a5b2448b288c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395761771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.395761771
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3427876755
Short name T746
Test name
Test status
Simulation time 3956220804 ps
CPU time 2.63 seconds
Started Jul 30 07:11:41 PM PDT 24
Finished Jul 30 07:11:43 PM PDT 24
Peak memory 201372 kb
Host smart-4364c425-6fb6-4c18-94fd-d0ef3aab0a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427876755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3427876755
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2227892997
Short name T592
Test name
Test status
Simulation time 5670757932 ps
CPU time 4.59 seconds
Started Jul 30 07:11:35 PM PDT 24
Finished Jul 30 07:11:39 PM PDT 24
Peak memory 201356 kb
Host smart-7619f637-3194-4fa8-a920-18acf146a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227892997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2227892997
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3143855846
Short name T380
Test name
Test status
Simulation time 142776555350 ps
CPU time 384.41 seconds
Started Jul 30 07:11:46 PM PDT 24
Finished Jul 30 07:18:10 PM PDT 24
Peak memory 201900 kb
Host smart-4fcda580-d159-4b8b-a33e-d83f9087d1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143855846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3143855846
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3372549127
Short name T103
Test name
Test status
Simulation time 1698157954357 ps
CPU time 524.39 seconds
Started Jul 30 07:11:46 PM PDT 24
Finished Jul 30 07:20:31 PM PDT 24
Peak memory 218168 kb
Host smart-4b03aed2-f5c4-4c46-8aa2-31c708395290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372549127 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3372549127
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3052997149
Short name T57
Test name
Test status
Simulation time 349286217 ps
CPU time 1.04 seconds
Started Jul 30 07:12:10 PM PDT 24
Finished Jul 30 07:12:11 PM PDT 24
Peak memory 201244 kb
Host smart-57da9c42-049e-48d9-ae50-c11f830756ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052997149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3052997149
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2071652971
Short name T771
Test name
Test status
Simulation time 516093081967 ps
CPU time 1212.27 seconds
Started Jul 30 07:11:58 PM PDT 24
Finished Jul 30 07:32:11 PM PDT 24
Peak memory 201460 kb
Host smart-1fc695c0-a48d-45e2-891f-f3ce5a577028
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071652971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2071652971
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.274646258
Short name T530
Test name
Test status
Simulation time 550300108880 ps
CPU time 344.91 seconds
Started Jul 30 07:12:05 PM PDT 24
Finished Jul 30 07:17:50 PM PDT 24
Peak memory 201256 kb
Host smart-0c6eb0e0-b31a-4f56-92f9-e13eda857de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274646258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.274646258
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4283689429
Short name T302
Test name
Test status
Simulation time 493343344032 ps
CPU time 1084.78 seconds
Started Jul 30 07:11:50 PM PDT 24
Finished Jul 30 07:29:55 PM PDT 24
Peak memory 201448 kb
Host smart-474d0457-d4b0-4a8b-b6f8-56f6e6432d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283689429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4283689429
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4037280152
Short name T191
Test name
Test status
Simulation time 162213332363 ps
CPU time 37.07 seconds
Started Jul 30 07:11:54 PM PDT 24
Finished Jul 30 07:12:31 PM PDT 24
Peak memory 201544 kb
Host smart-3c44acbe-b09d-490e-b839-ccdbf3cc4897
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037280152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4037280152
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.488594280
Short name T251
Test name
Test status
Simulation time 494491646929 ps
CPU time 78.74 seconds
Started Jul 30 07:11:50 PM PDT 24
Finished Jul 30 07:13:09 PM PDT 24
Peak memory 201428 kb
Host smart-c3b1a3a8-6383-46e7-8388-030dff413596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488594280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.488594280
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.34309782
Short name T403
Test name
Test status
Simulation time 164123611663 ps
CPU time 175.42 seconds
Started Jul 30 07:11:51 PM PDT 24
Finished Jul 30 07:14:46 PM PDT 24
Peak memory 201436 kb
Host smart-8982ab9d-dec7-4ffc-b3bb-8007c6f6ff37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed
.34309782
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2686750225
Short name T44
Test name
Test status
Simulation time 512435077704 ps
CPU time 614.76 seconds
Started Jul 30 07:11:54 PM PDT 24
Finished Jul 30 07:22:09 PM PDT 24
Peak memory 201428 kb
Host smart-b82d0518-5ba6-4960-9336-2db26210b91e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686750225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2686750225
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.805263510
Short name T335
Test name
Test status
Simulation time 407143568447 ps
CPU time 344.57 seconds
Started Jul 30 07:11:54 PM PDT 24
Finished Jul 30 07:17:39 PM PDT 24
Peak memory 201448 kb
Host smart-2fd075b8-6378-40ad-914a-8672d028ccd3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805263510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.805263510
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1806207215
Short name T621
Test name
Test status
Simulation time 70617928480 ps
CPU time 304.68 seconds
Started Jul 30 07:12:07 PM PDT 24
Finished Jul 30 07:17:12 PM PDT 24
Peak memory 201888 kb
Host smart-45850488-7ab8-4177-917c-506b4597d230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806207215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1806207215
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.539316619
Short name T721
Test name
Test status
Simulation time 34564310295 ps
CPU time 75.49 seconds
Started Jul 30 07:12:05 PM PDT 24
Finished Jul 30 07:13:21 PM PDT 24
Peak memory 201400 kb
Host smart-828ed055-db06-4f58-aa7f-120063b7dd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539316619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.539316619
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1995050151
Short name T560
Test name
Test status
Simulation time 3369313857 ps
CPU time 1.7 seconds
Started Jul 30 07:12:07 PM PDT 24
Finished Jul 30 07:12:09 PM PDT 24
Peak memory 201356 kb
Host smart-3c207d8f-5453-43cb-ba53-4bc984eb25ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995050151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1995050151
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3247691884
Short name T615
Test name
Test status
Simulation time 6098165248 ps
CPU time 13.76 seconds
Started Jul 30 07:11:50 PM PDT 24
Finished Jul 30 07:12:04 PM PDT 24
Peak memory 201300 kb
Host smart-7a6c9c5c-96ac-4409-8aa1-fad9f9db423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247691884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3247691884
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.228897259
Short name T759
Test name
Test status
Simulation time 220327514820 ps
CPU time 373.73 seconds
Started Jul 30 07:12:06 PM PDT 24
Finished Jul 30 07:18:20 PM PDT 24
Peak memory 201516 kb
Host smart-4100c86f-37f9-43ca-afad-fb0fb58ba5db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228897259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
228897259
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3808748636
Short name T100
Test name
Test status
Simulation time 28260009764 ps
CPU time 35.77 seconds
Started Jul 30 07:12:07 PM PDT 24
Finished Jul 30 07:12:42 PM PDT 24
Peak memory 209820 kb
Host smart-a41c96d8-e86a-46ab-b059-ea497bbf5f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808748636 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3808748636
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2124936828
Short name T374
Test name
Test status
Simulation time 459821297 ps
CPU time 0.87 seconds
Started Jul 30 07:12:22 PM PDT 24
Finished Jul 30 07:12:23 PM PDT 24
Peak memory 201240 kb
Host smart-497f3253-d210-4db3-9af0-55de53f4b104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124936828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2124936828
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.569031283
Short name T239
Test name
Test status
Simulation time 162574362909 ps
CPU time 132.19 seconds
Started Jul 30 07:12:14 PM PDT 24
Finished Jul 30 07:14:26 PM PDT 24
Peak memory 201444 kb
Host smart-2279c8b9-60bb-4a2a-a1dd-a51545ffa093
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569031283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.569031283
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4289050304
Short name T283
Test name
Test status
Simulation time 523186620328 ps
CPU time 540.56 seconds
Started Jul 30 07:12:14 PM PDT 24
Finished Jul 30 07:21:15 PM PDT 24
Peak memory 201444 kb
Host smart-0796e1bc-f7d7-4c2a-b10f-a07388a17a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289050304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4289050304
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3384141819
Short name T150
Test name
Test status
Simulation time 499241822124 ps
CPU time 308.49 seconds
Started Jul 30 07:12:08 PM PDT 24
Finished Jul 30 07:17:17 PM PDT 24
Peak memory 201532 kb
Host smart-eefdabcc-fced-4528-945c-464147e10194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384141819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3384141819
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3612165013
Short name T496
Test name
Test status
Simulation time 496542096457 ps
CPU time 1044.11 seconds
Started Jul 30 07:12:14 PM PDT 24
Finished Jul 30 07:29:38 PM PDT 24
Peak memory 201436 kb
Host smart-3eed5299-7157-4cce-a366-c0c1012a6c80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612165013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3612165013
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3329656883
Short name T177
Test name
Test status
Simulation time 161754554083 ps
CPU time 100.67 seconds
Started Jul 30 07:12:10 PM PDT 24
Finished Jul 30 07:13:51 PM PDT 24
Peak memory 201460 kb
Host smart-af5a5fd4-9785-4e0c-aff6-bb12b3089f10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329656883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3329656883
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.280866083
Short name T330
Test name
Test status
Simulation time 199780128450 ps
CPU time 216.1 seconds
Started Jul 30 07:12:14 PM PDT 24
Finished Jul 30 07:15:50 PM PDT 24
Peak memory 201440 kb
Host smart-3bcb6193-fb87-4639-b7c1-0a5e4533a22b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280866083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.280866083
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1952572512
Short name T209
Test name
Test status
Simulation time 104406060538 ps
CPU time 540.76 seconds
Started Jul 30 07:12:18 PM PDT 24
Finished Jul 30 07:21:19 PM PDT 24
Peak memory 201828 kb
Host smart-aa992ac3-9c79-4221-b1b3-f73af0faabda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952572512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1952572512
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3465852557
Short name T432
Test name
Test status
Simulation time 36519963172 ps
CPU time 85.35 seconds
Started Jul 30 07:12:16 PM PDT 24
Finished Jul 30 07:13:41 PM PDT 24
Peak memory 201364 kb
Host smart-decb065c-01d1-41da-87eb-7958fe931c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465852557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3465852557
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1849370101
Short name T795
Test name
Test status
Simulation time 5143088634 ps
CPU time 7.74 seconds
Started Jul 30 07:12:17 PM PDT 24
Finished Jul 30 07:12:25 PM PDT 24
Peak memory 201300 kb
Host smart-40e3f67c-5396-4e59-816a-42c6eb40d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849370101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1849370101
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2978909358
Short name T660
Test name
Test status
Simulation time 6098308669 ps
CPU time 1.72 seconds
Started Jul 30 07:12:09 PM PDT 24
Finished Jul 30 07:12:11 PM PDT 24
Peak memory 201324 kb
Host smart-cad18ffa-3327-4917-8314-1b4cec1bc762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978909358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2978909358
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2304275072
Short name T41
Test name
Test status
Simulation time 73681159505 ps
CPU time 42.29 seconds
Started Jul 30 07:12:18 PM PDT 24
Finished Jul 30 07:13:00 PM PDT 24
Peak memory 209836 kb
Host smart-8be6b9f0-b96c-4045-976a-ea229eefd5a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304275072 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2304275072
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3527939919
Short name T16
Test name
Test status
Simulation time 457129063 ps
CPU time 0.89 seconds
Started Jul 30 07:12:36 PM PDT 24
Finished Jul 30 07:12:37 PM PDT 24
Peak memory 201268 kb
Host smart-203cdfd8-1ce8-4d8a-a451-c57a96b6bd83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527939919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3527939919
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1712916930
Short name T154
Test name
Test status
Simulation time 496699581531 ps
CPU time 275.52 seconds
Started Jul 30 07:12:24 PM PDT 24
Finished Jul 30 07:17:00 PM PDT 24
Peak memory 201492 kb
Host smart-8b9264ef-6b62-4f22-b762-d28637b5b4f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712916930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1712916930
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2526396007
Short name T267
Test name
Test status
Simulation time 165820171291 ps
CPU time 337.85 seconds
Started Jul 30 07:12:25 PM PDT 24
Finished Jul 30 07:18:03 PM PDT 24
Peak memory 201452 kb
Host smart-38a74637-9f1b-415d-af81-202dc889c825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526396007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2526396007
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3898292527
Short name T222
Test name
Test status
Simulation time 163357814430 ps
CPU time 100.49 seconds
Started Jul 30 07:12:24 PM PDT 24
Finished Jul 30 07:14:05 PM PDT 24
Peak memory 201544 kb
Host smart-7f034078-66c3-427c-8023-bfa39ce14ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898292527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3898292527
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1574219974
Short name T683
Test name
Test status
Simulation time 155940752964 ps
CPU time 95.3 seconds
Started Jul 30 07:12:24 PM PDT 24
Finished Jul 30 07:13:59 PM PDT 24
Peak memory 201540 kb
Host smart-c2c46454-4736-4720-bce2-8ebaad172a65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574219974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1574219974
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.375384064
Short name T291
Test name
Test status
Simulation time 166618187517 ps
CPU time 100.02 seconds
Started Jul 30 07:12:23 PM PDT 24
Finished Jul 30 07:14:03 PM PDT 24
Peak memory 201528 kb
Host smart-b8da10a0-27ef-4939-b022-309cc8de85e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375384064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.375384064
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3922423703
Short name T391
Test name
Test status
Simulation time 164648489240 ps
CPU time 92.04 seconds
Started Jul 30 07:12:21 PM PDT 24
Finished Jul 30 07:13:53 PM PDT 24
Peak memory 201444 kb
Host smart-caba9528-7433-4204-81a1-d865e4f61598
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922423703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3922423703
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3949850509
Short name T727
Test name
Test status
Simulation time 599301275963 ps
CPU time 354.5 seconds
Started Jul 30 07:12:26 PM PDT 24
Finished Jul 30 07:18:21 PM PDT 24
Peak memory 201440 kb
Host smart-49e9f4eb-627f-486a-b797-c229bed9a87e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949850509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3949850509
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1693775359
Short name T558
Test name
Test status
Simulation time 130822898567 ps
CPU time 443.34 seconds
Started Jul 30 07:12:28 PM PDT 24
Finished Jul 30 07:19:52 PM PDT 24
Peak memory 201892 kb
Host smart-bfbe0f0b-db63-40c1-9c53-126939d4ede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693775359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1693775359
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2570555831
Short name T470
Test name
Test status
Simulation time 34718150470 ps
CPU time 81.32 seconds
Started Jul 30 07:12:28 PM PDT 24
Finished Jul 30 07:13:50 PM PDT 24
Peak memory 201324 kb
Host smart-bbead2dd-21b5-4f51-90a7-413783915c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570555831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2570555831
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3079237427
Short name T654
Test name
Test status
Simulation time 4051130651 ps
CPU time 10.83 seconds
Started Jul 30 07:12:26 PM PDT 24
Finished Jul 30 07:12:37 PM PDT 24
Peak memory 201340 kb
Host smart-9c436051-edc0-4bdd-a96b-7ccc9f7654ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079237427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3079237427
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.706609961
Short name T705
Test name
Test status
Simulation time 5664140854 ps
CPU time 8.05 seconds
Started Jul 30 07:12:23 PM PDT 24
Finished Jul 30 07:12:31 PM PDT 24
Peak memory 201376 kb
Host smart-c09e4fd1-fbda-43c4-a6f3-78d13015cf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706609961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.706609961
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3353399233
Short name T792
Test name
Test status
Simulation time 2675452704 ps
CPU time 6.61 seconds
Started Jul 30 07:12:32 PM PDT 24
Finished Jul 30 07:12:39 PM PDT 24
Peak memory 201804 kb
Host smart-f0b03ae2-b2a7-4ffd-96f1-9f11b519ca93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353399233 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3353399233
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3149314936
Short name T565
Test name
Test status
Simulation time 430884711 ps
CPU time 1.13 seconds
Started Jul 30 07:07:01 PM PDT 24
Finished Jul 30 07:07:03 PM PDT 24
Peak memory 201232 kb
Host smart-2786c07c-26da-4a3d-b8ca-5cf74b489f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149314936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3149314936
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.903036418
Short name T659
Test name
Test status
Simulation time 163941403992 ps
CPU time 66.63 seconds
Started Jul 30 07:06:48 PM PDT 24
Finished Jul 30 07:07:55 PM PDT 24
Peak memory 201448 kb
Host smart-7d7a21c5-aa67-408a-b992-0cb36e40996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903036418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.903036418
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2414561113
Short name T651
Test name
Test status
Simulation time 492075665189 ps
CPU time 327.38 seconds
Started Jul 30 07:06:50 PM PDT 24
Finished Jul 30 07:12:17 PM PDT 24
Peak memory 201468 kb
Host smart-80405bc8-3080-42ef-9131-c9f772cbbd91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414561113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2414561113
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.43832701
Short name T766
Test name
Test status
Simulation time 163446853982 ps
CPU time 27.57 seconds
Started Jul 30 07:06:39 PM PDT 24
Finished Jul 30 07:07:06 PM PDT 24
Peak memory 201380 kb
Host smart-6d88f286-710a-45ad-a1fe-61856c0f61c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43832701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.43832701
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.232562295
Short name T579
Test name
Test status
Simulation time 484955903056 ps
CPU time 273.11 seconds
Started Jul 30 07:06:43 PM PDT 24
Finished Jul 30 07:11:16 PM PDT 24
Peak memory 201464 kb
Host smart-db91d356-d1ac-4ebe-b394-e7cb8aa5ba28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=232562295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.232562295
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3190764567
Short name T172
Test name
Test status
Simulation time 533233483123 ps
CPU time 301.48 seconds
Started Jul 30 07:06:50 PM PDT 24
Finished Jul 30 07:11:51 PM PDT 24
Peak memory 201420 kb
Host smart-b1045668-dea6-416c-aabe-55f01aa9f1df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190764567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3190764567
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2156820333
Short name T576
Test name
Test status
Simulation time 599923970631 ps
CPU time 1310.05 seconds
Started Jul 30 07:06:51 PM PDT 24
Finished Jul 30 07:28:41 PM PDT 24
Peak memory 201488 kb
Host smart-c09d8042-f576-44bb-8168-138bb816839a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156820333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2156820333
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4200883557
Short name T656
Test name
Test status
Simulation time 116944397096 ps
CPU time 633.69 seconds
Started Jul 30 07:06:55 PM PDT 24
Finished Jul 30 07:17:29 PM PDT 24
Peak memory 201820 kb
Host smart-2de8a3b6-6988-49d0-9ce8-60f5aaee85dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200883557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4200883557
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.577287533
Short name T409
Test name
Test status
Simulation time 32987678071 ps
CPU time 72.47 seconds
Started Jul 30 07:06:55 PM PDT 24
Finished Jul 30 07:08:07 PM PDT 24
Peak memory 201372 kb
Host smart-c39af650-e111-4de9-ad92-a4930a400b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577287533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.577287533
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1788356443
Short name T749
Test name
Test status
Simulation time 4648771128 ps
CPU time 3.6 seconds
Started Jul 30 07:06:54 PM PDT 24
Finished Jul 30 07:06:58 PM PDT 24
Peak memory 201300 kb
Host smart-ce08d21a-37c9-4f1c-b6c3-499f255bf68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788356443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1788356443
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.4293341606
Short name T48
Test name
Test status
Simulation time 3857726224 ps
CPU time 2.99 seconds
Started Jul 30 07:07:02 PM PDT 24
Finished Jul 30 07:07:05 PM PDT 24
Peak memory 217152 kb
Host smart-f0610f28-15fa-4854-a26d-40d799747193
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293341606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.4293341606
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2201251075
Short name T609
Test name
Test status
Simulation time 5859345553 ps
CPU time 7.05 seconds
Started Jul 30 07:06:39 PM PDT 24
Finished Jul 30 07:06:46 PM PDT 24
Peak memory 201392 kb
Host smart-1b777377-0b3f-459f-a193-f3b173ae4acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201251075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2201251075
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1979238465
Short name T740
Test name
Test status
Simulation time 491380946 ps
CPU time 1.25 seconds
Started Jul 30 07:13:04 PM PDT 24
Finished Jul 30 07:13:05 PM PDT 24
Peak memory 201236 kb
Host smart-8f83e515-3e5d-4c0c-aa77-5e3c0cf11c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979238465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1979238465
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.345539394
Short name T314
Test name
Test status
Simulation time 331677064153 ps
CPU time 776.85 seconds
Started Jul 30 07:12:56 PM PDT 24
Finished Jul 30 07:25:53 PM PDT 24
Peak memory 201440 kb
Host smart-d87369ff-10a5-4741-b260-5df560f767a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345539394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.345539394
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.502216610
Short name T642
Test name
Test status
Simulation time 167675247672 ps
CPU time 38.91 seconds
Started Jul 30 07:12:44 PM PDT 24
Finished Jul 30 07:13:23 PM PDT 24
Peak memory 201472 kb
Host smart-e043d2cb-a5ee-4491-88bf-5e65e8de3e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502216610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.502216610
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2550772781
Short name T591
Test name
Test status
Simulation time 492589017029 ps
CPU time 291.31 seconds
Started Jul 30 07:12:46 PM PDT 24
Finished Jul 30 07:17:37 PM PDT 24
Peak memory 201540 kb
Host smart-2927ed73-ff17-4029-918b-63f294c89bfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550772781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2550772781
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2642433946
Short name T285
Test name
Test status
Simulation time 500889720409 ps
CPU time 308.48 seconds
Started Jul 30 07:12:45 PM PDT 24
Finished Jul 30 07:17:54 PM PDT 24
Peak memory 201508 kb
Host smart-74d906c5-4905-4cd3-9445-58afe140f40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642433946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2642433946
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2554241504
Short name T367
Test name
Test status
Simulation time 167700952769 ps
CPU time 189.01 seconds
Started Jul 30 07:12:44 PM PDT 24
Finished Jul 30 07:15:53 PM PDT 24
Peak memory 201412 kb
Host smart-02bdedfc-1810-451b-abf3-733de5d57970
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554241504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2554241504
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1928290882
Short name T315
Test name
Test status
Simulation time 522006016778 ps
CPU time 471.07 seconds
Started Jul 30 07:12:48 PM PDT 24
Finished Jul 30 07:20:39 PM PDT 24
Peak memory 201420 kb
Host smart-cd0c2a68-52fb-4cf3-9a31-389afeb08670
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928290882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1928290882
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4266817336
Short name T332
Test name
Test status
Simulation time 201915083348 ps
CPU time 82.75 seconds
Started Jul 30 07:12:52 PM PDT 24
Finished Jul 30 07:14:15 PM PDT 24
Peak memory 201364 kb
Host smart-fa295fc0-b119-4084-b4d8-51de8f91dce6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266817336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4266817336
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2269098339
Short name T630
Test name
Test status
Simulation time 27400750303 ps
CPU time 4.96 seconds
Started Jul 30 07:13:00 PM PDT 24
Finished Jul 30 07:13:05 PM PDT 24
Peak memory 201416 kb
Host smart-660ec7b0-09ac-4ac1-a880-7e5cc2b1e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269098339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2269098339
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1352368961
Short name T748
Test name
Test status
Simulation time 5636554726 ps
CPU time 11.06 seconds
Started Jul 30 07:12:55 PM PDT 24
Finished Jul 30 07:13:06 PM PDT 24
Peak memory 201364 kb
Host smart-9960a7ae-ebb2-4c92-a453-c92c36091d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352368961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1352368961
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3741353356
Short name T352
Test name
Test status
Simulation time 5948352900 ps
CPU time 2.74 seconds
Started Jul 30 07:12:37 PM PDT 24
Finished Jul 30 07:12:40 PM PDT 24
Peak memory 201396 kb
Host smart-d975194b-b654-43a0-a074-4fca90363bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741353356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3741353356
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1391632670
Short name T707
Test name
Test status
Simulation time 282273651931 ps
CPU time 232.88 seconds
Started Jul 30 07:13:02 PM PDT 24
Finished Jul 30 07:16:55 PM PDT 24
Peak memory 201448 kb
Host smart-58bc137e-05a0-4cea-a5d5-171c1fc38a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391632670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1391632670
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1880723140
Short name T56
Test name
Test status
Simulation time 388396053554 ps
CPU time 304.01 seconds
Started Jul 30 07:13:00 PM PDT 24
Finished Jul 30 07:18:05 PM PDT 24
Peak memory 211244 kb
Host smart-e675539a-8761-4c2a-9e5c-7ec8460e838f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880723140 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1880723140
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3253541412
Short name T431
Test name
Test status
Simulation time 361422401 ps
CPU time 0.94 seconds
Started Jul 30 07:13:20 PM PDT 24
Finished Jul 30 07:13:21 PM PDT 24
Peak memory 201240 kb
Host smart-d33e18c1-bcb3-40d7-b7d4-df4672d41b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253541412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3253541412
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1500384440
Short name T145
Test name
Test status
Simulation time 500635125632 ps
CPU time 444.89 seconds
Started Jul 30 07:13:16 PM PDT 24
Finished Jul 30 07:20:41 PM PDT 24
Peak memory 201480 kb
Host smart-cac4c98b-1e03-4962-bd6a-5db41eed6ef1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500384440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1500384440
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2668036202
Short name T174
Test name
Test status
Simulation time 330966299108 ps
CPU time 723.25 seconds
Started Jul 30 07:13:13 PM PDT 24
Finished Jul 30 07:25:17 PM PDT 24
Peak memory 201452 kb
Host smart-23f709c4-570e-4628-afa2-ba79b7166db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668036202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2668036202
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2902738933
Short name T588
Test name
Test status
Simulation time 164107997016 ps
CPU time 380.11 seconds
Started Jul 30 07:13:11 PM PDT 24
Finished Jul 30 07:19:31 PM PDT 24
Peak memory 201448 kb
Host smart-40060948-0b74-46b1-8932-8de49e1b1f5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902738933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2902738933
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2406661731
Short name T200
Test name
Test status
Simulation time 328995738710 ps
CPU time 625.82 seconds
Started Jul 30 07:13:07 PM PDT 24
Finished Jul 30 07:23:33 PM PDT 24
Peak memory 201504 kb
Host smart-b7c7bd0d-3bdf-4e08-8895-674f2d886a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406661731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2406661731
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3764618462
Short name T453
Test name
Test status
Simulation time 333304773124 ps
CPU time 712.15 seconds
Started Jul 30 07:13:08 PM PDT 24
Finished Jul 30 07:25:01 PM PDT 24
Peak memory 201408 kb
Host smart-74679f03-09d8-4aee-b92a-46c58683a01e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764618462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3764618462
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2278898795
Short name T724
Test name
Test status
Simulation time 449020001654 ps
CPU time 278.57 seconds
Started Jul 30 07:13:17 PM PDT 24
Finished Jul 30 07:17:55 PM PDT 24
Peak memory 201508 kb
Host smart-e70a0f6b-3b5e-4a4a-92a6-8fbb8122e32e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278898795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2278898795
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2346563423
Short name T689
Test name
Test status
Simulation time 611203443011 ps
CPU time 378.74 seconds
Started Jul 30 07:13:11 PM PDT 24
Finished Jul 30 07:19:30 PM PDT 24
Peak memory 201460 kb
Host smart-c799caf7-5671-49e0-8427-3ec92aef99c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346563423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2346563423
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3163713002
Short name T205
Test name
Test status
Simulation time 97772327401 ps
CPU time 311.85 seconds
Started Jul 30 07:13:17 PM PDT 24
Finished Jul 30 07:18:29 PM PDT 24
Peak memory 201904 kb
Host smart-2653d94a-062f-4318-bbce-20b5bca671ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163713002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3163713002
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.400415479
Short name T328
Test name
Test status
Simulation time 34499857381 ps
CPU time 82.89 seconds
Started Jul 30 07:13:16 PM PDT 24
Finished Jul 30 07:14:39 PM PDT 24
Peak memory 201340 kb
Host smart-1f403cb8-39b5-4d62-8d0d-923d0cd80821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400415479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.400415479
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1601110416
Short name T413
Test name
Test status
Simulation time 5543504615 ps
CPU time 1.95 seconds
Started Jul 30 07:13:17 PM PDT 24
Finished Jul 30 07:13:19 PM PDT 24
Peak memory 201352 kb
Host smart-ae620aa3-983a-4f76-adaf-7557df9f8afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601110416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1601110416
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.307070532
Short name T3
Test name
Test status
Simulation time 5713689106 ps
CPU time 13.8 seconds
Started Jul 30 07:13:03 PM PDT 24
Finished Jul 30 07:13:17 PM PDT 24
Peak memory 201348 kb
Host smart-760be2d6-ff38-4744-85af-c9b74ef44924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307070532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.307070532
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3189270019
Short name T763
Test name
Test status
Simulation time 52912605851 ps
CPU time 31.06 seconds
Started Jul 30 07:13:21 PM PDT 24
Finished Jul 30 07:13:52 PM PDT 24
Peak memory 201488 kb
Host smart-b58b92d7-6739-4adc-a591-85eb3bc88184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189270019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3189270019
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2036927387
Short name T289
Test name
Test status
Simulation time 133313404768 ps
CPU time 102.68 seconds
Started Jul 30 07:13:21 PM PDT 24
Finished Jul 30 07:15:04 PM PDT 24
Peak memory 218300 kb
Host smart-955c32f7-d03b-4c8c-aa90-9f628c535414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036927387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2036927387
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.78481892
Short name T361
Test name
Test status
Simulation time 556521866 ps
CPU time 0.77 seconds
Started Jul 30 07:13:42 PM PDT 24
Finished Jul 30 07:13:43 PM PDT 24
Peak memory 201272 kb
Host smart-04a84256-bd49-4b47-b5d4-d0333051c759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78481892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.78481892
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1583401789
Short name T633
Test name
Test status
Simulation time 330263078548 ps
CPU time 202.13 seconds
Started Jul 30 07:13:27 PM PDT 24
Finished Jul 30 07:16:49 PM PDT 24
Peak memory 201400 kb
Host smart-5cef341d-5e52-4681-a1bf-b14160bada91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583401789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1583401789
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3061607975
Short name T360
Test name
Test status
Simulation time 333999044201 ps
CPU time 371.55 seconds
Started Jul 30 07:13:28 PM PDT 24
Finished Jul 30 07:19:39 PM PDT 24
Peak memory 201384 kb
Host smart-19610440-b129-4045-99cc-eabf19a60740
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061607975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3061607975
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3300527618
Short name T498
Test name
Test status
Simulation time 328670339066 ps
CPU time 394.32 seconds
Started Jul 30 07:13:24 PM PDT 24
Finished Jul 30 07:19:59 PM PDT 24
Peak memory 201372 kb
Host smart-5d157201-e0ff-4619-97bb-39943048119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300527618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3300527618
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1013382466
Short name T355
Test name
Test status
Simulation time 493097603247 ps
CPU time 1189.87 seconds
Started Jul 30 07:13:24 PM PDT 24
Finished Jul 30 07:33:14 PM PDT 24
Peak memory 201448 kb
Host smart-c5eca065-8a9b-47b1-bbb1-97f4688d6353
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013382466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1013382466
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.4245428835
Short name T634
Test name
Test status
Simulation time 360563398445 ps
CPU time 836.74 seconds
Started Jul 30 07:13:29 PM PDT 24
Finished Jul 30 07:27:26 PM PDT 24
Peak memory 201376 kb
Host smart-5f6ec0df-c4c0-4a08-90a4-9e7b5ca45a99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245428835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.4245428835
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1921185439
Short name T366
Test name
Test status
Simulation time 387433317930 ps
CPU time 866.56 seconds
Started Jul 30 07:13:28 PM PDT 24
Finished Jul 30 07:27:54 PM PDT 24
Peak memory 201500 kb
Host smart-9a08b083-d450-40ce-91ea-177eea81769f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921185439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1921185439
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.4248193446
Short name T535
Test name
Test status
Simulation time 68576457977 ps
CPU time 261.07 seconds
Started Jul 30 07:13:39 PM PDT 24
Finished Jul 30 07:18:01 PM PDT 24
Peak memory 201880 kb
Host smart-9a75a94b-c396-4058-ab9e-a91a3b624ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248193446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.4248193446
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2148156607
Short name T686
Test name
Test status
Simulation time 27398503402 ps
CPU time 30.94 seconds
Started Jul 30 07:13:38 PM PDT 24
Finished Jul 30 07:14:09 PM PDT 24
Peak memory 201336 kb
Host smart-33702543-05c4-4afb-b32d-46902aea59bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148156607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2148156607
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2634009613
Short name T411
Test name
Test status
Simulation time 3102577311 ps
CPU time 2.49 seconds
Started Jul 30 07:13:33 PM PDT 24
Finished Jul 30 07:13:36 PM PDT 24
Peak memory 201344 kb
Host smart-ce0d1cd6-ecfe-4dd7-9837-20640fcf1082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634009613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2634009613
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1336436565
Short name T479
Test name
Test status
Simulation time 5856317907 ps
CPU time 12.89 seconds
Started Jul 30 07:13:21 PM PDT 24
Finished Jul 30 07:13:34 PM PDT 24
Peak memory 201368 kb
Host smart-1edfcf55-47df-4fb6-9b8a-0b340b1b081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336436565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1336436565
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2586357807
Short name T272
Test name
Test status
Simulation time 196855740991 ps
CPU time 101.24 seconds
Started Jul 30 07:13:38 PM PDT 24
Finished Jul 30 07:15:20 PM PDT 24
Peak memory 201488 kb
Host smart-b6f59422-edf2-4a22-bad6-dc75a29d0093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586357807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2586357807
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.296603188
Short name T745
Test name
Test status
Simulation time 111046193559 ps
CPU time 61.07 seconds
Started Jul 30 07:13:38 PM PDT 24
Finished Jul 30 07:14:39 PM PDT 24
Peak memory 217908 kb
Host smart-b8fd27bb-65a3-4a25-8d8a-ed8f1d725461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296603188 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.296603188
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.21423149
Short name T410
Test name
Test status
Simulation time 340225610 ps
CPU time 1.35 seconds
Started Jul 30 07:14:05 PM PDT 24
Finished Jul 30 07:14:07 PM PDT 24
Peak memory 201164 kb
Host smart-d4111a52-6b36-4861-8f69-60de4a3b7af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.21423149
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3894957285
Short name T220
Test name
Test status
Simulation time 515112690912 ps
CPU time 947.74 seconds
Started Jul 30 07:13:54 PM PDT 24
Finished Jul 30 07:29:42 PM PDT 24
Peak memory 201480 kb
Host smart-5cc5830d-8c09-4cb8-9dd2-116119a57955
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894957285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3894957285
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3569938001
Short name T597
Test name
Test status
Simulation time 352360261614 ps
CPU time 200.68 seconds
Started Jul 30 07:13:54 PM PDT 24
Finished Jul 30 07:17:15 PM PDT 24
Peak memory 201452 kb
Host smart-1983d01f-a5d0-4724-82c0-d11f07414cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569938001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3569938001
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.471348879
Short name T624
Test name
Test status
Simulation time 164855878639 ps
CPU time 104.02 seconds
Started Jul 30 07:13:51 PM PDT 24
Finished Jul 30 07:15:35 PM PDT 24
Peak memory 201440 kb
Host smart-9a0418cc-2de3-47aa-a92e-4a287d89f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471348879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.471348879
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.149817902
Short name T388
Test name
Test status
Simulation time 486977287133 ps
CPU time 552.11 seconds
Started Jul 30 07:13:51 PM PDT 24
Finished Jul 30 07:23:03 PM PDT 24
Peak memory 201452 kb
Host smart-19ed59cb-b4d3-4dbc-b770-afeaca3fc492
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=149817902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.149817902
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.170882494
Short name T617
Test name
Test status
Simulation time 161018334235 ps
CPU time 296.2 seconds
Started Jul 30 07:13:53 PM PDT 24
Finished Jul 30 07:18:50 PM PDT 24
Peak memory 201500 kb
Host smart-3a5b2b83-ad82-424d-b87a-4e0efce68ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170882494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.170882494
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2580700795
Short name T742
Test name
Test status
Simulation time 160122704418 ps
CPU time 54.02 seconds
Started Jul 30 07:13:54 PM PDT 24
Finished Jul 30 07:14:48 PM PDT 24
Peak memory 201480 kb
Host smart-804d081b-a7b8-44b1-b7ab-9e3e4f729b9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580700795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2580700795
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2783700582
Short name T504
Test name
Test status
Simulation time 587631032644 ps
CPU time 280.06 seconds
Started Jul 30 07:13:49 PM PDT 24
Finished Jul 30 07:18:29 PM PDT 24
Peak memory 201472 kb
Host smart-11b8891b-cb10-4669-b9ea-f68969b72af8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783700582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2783700582
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.448231840
Short name T370
Test name
Test status
Simulation time 396589938680 ps
CPU time 896.05 seconds
Started Jul 30 07:13:53 PM PDT 24
Finished Jul 30 07:28:49 PM PDT 24
Peak memory 201500 kb
Host smart-021f2701-c097-4353-8489-b7b5606ecc2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448231840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.448231840
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.598447888
Short name T555
Test name
Test status
Simulation time 85143534357 ps
CPU time 452.54 seconds
Started Jul 30 07:13:58 PM PDT 24
Finished Jul 30 07:21:31 PM PDT 24
Peak memory 201816 kb
Host smart-914e690a-9e88-4f38-90e5-532ca321d8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598447888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.598447888
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.126306245
Short name T2
Test name
Test status
Simulation time 22243176585 ps
CPU time 47.27 seconds
Started Jul 30 07:13:52 PM PDT 24
Finished Jul 30 07:14:40 PM PDT 24
Peak memory 201344 kb
Host smart-542e1d01-14d2-45c3-b5bd-5db5fdd5a8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126306245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.126306245
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2841172637
Short name T767
Test name
Test status
Simulation time 4969024850 ps
CPU time 5.82 seconds
Started Jul 30 07:13:53 PM PDT 24
Finished Jul 30 07:13:59 PM PDT 24
Peak memory 201348 kb
Host smart-0b7a7373-0ee5-417b-8e70-02bce584ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841172637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2841172637
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3913404886
Short name T168
Test name
Test status
Simulation time 5880112784 ps
CPU time 1.81 seconds
Started Jul 30 07:13:43 PM PDT 24
Finished Jul 30 07:13:45 PM PDT 24
Peak memory 201356 kb
Host smart-fc26a656-c848-4aac-8227-9a680d2aa555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913404886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3913404886
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.263816023
Short name T440
Test name
Test status
Simulation time 301118447241 ps
CPU time 515.06 seconds
Started Jul 30 07:14:06 PM PDT 24
Finished Jul 30 07:22:41 PM PDT 24
Peak memory 201956 kb
Host smart-4fad5ab7-7f68-4c69-b9b7-2af29b070808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263816023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
263816023
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3864627179
Short name T101
Test name
Test status
Simulation time 273526442380 ps
CPU time 141.26 seconds
Started Jul 30 07:14:02 PM PDT 24
Finished Jul 30 07:16:23 PM PDT 24
Peak memory 210184 kb
Host smart-77ba31b4-25e4-4886-8900-9f1ab9f14ea7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864627179 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3864627179
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.750547856
Short name T393
Test name
Test status
Simulation time 472860534 ps
CPU time 1.26 seconds
Started Jul 30 07:14:28 PM PDT 24
Finished Jul 30 07:14:29 PM PDT 24
Peak memory 201244 kb
Host smart-5362589c-b831-4c87-b82f-63d804f5f57c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750547856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.750547856
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3642438199
Short name T234
Test name
Test status
Simulation time 161262674912 ps
CPU time 380.1 seconds
Started Jul 30 07:14:17 PM PDT 24
Finished Jul 30 07:20:37 PM PDT 24
Peak memory 201420 kb
Host smart-8db37132-a87b-4d03-8a00-74ab01f82f7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642438199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3642438199
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3296595802
Short name T248
Test name
Test status
Simulation time 166053301989 ps
CPU time 24.97 seconds
Started Jul 30 07:14:21 PM PDT 24
Finished Jul 30 07:14:46 PM PDT 24
Peak memory 201340 kb
Host smart-4362a145-d14a-4e33-aad3-392aa39d9c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296595802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3296595802
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3955529213
Short name T107
Test name
Test status
Simulation time 156985442138 ps
CPU time 343.87 seconds
Started Jul 30 07:14:17 PM PDT 24
Finished Jul 30 07:20:01 PM PDT 24
Peak memory 201452 kb
Host smart-69a55e5a-801a-4b98-95b4-c703fc515c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955529213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3955529213
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4024795890
Short name T96
Test name
Test status
Simulation time 487177123344 ps
CPU time 1123.04 seconds
Started Jul 30 07:14:19 PM PDT 24
Finished Jul 30 07:33:02 PM PDT 24
Peak memory 201472 kb
Host smart-f0f68563-cdd6-4a3f-815c-63730638db3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024795890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.4024795890
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.685069357
Short name T412
Test name
Test status
Simulation time 492113571036 ps
CPU time 602.45 seconds
Started Jul 30 07:14:14 PM PDT 24
Finished Jul 30 07:24:16 PM PDT 24
Peak memory 201448 kb
Host smart-7d8c87e9-35c2-4a6a-a72e-3b4fd5f17a0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=685069357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.685069357
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3401822583
Short name T436
Test name
Test status
Simulation time 178546876490 ps
CPU time 216.05 seconds
Started Jul 30 07:14:17 PM PDT 24
Finished Jul 30 07:17:54 PM PDT 24
Peak memory 201472 kb
Host smart-52b26ac7-ff8f-41a4-8027-c133fac3896b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401822583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3401822583
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2313383845
Short name T337
Test name
Test status
Simulation time 585628981177 ps
CPU time 1321.31 seconds
Started Jul 30 07:14:19 PM PDT 24
Finished Jul 30 07:36:21 PM PDT 24
Peak memory 201448 kb
Host smart-6c8cc4c5-a879-4fd8-aa23-1bd16a158048
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313383845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2313383845
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.804159593
Short name T622
Test name
Test status
Simulation time 81317409643 ps
CPU time 327.8 seconds
Started Jul 30 07:14:25 PM PDT 24
Finished Jul 30 07:19:53 PM PDT 24
Peak memory 201824 kb
Host smart-d3f4adbb-fbb7-46e6-88e1-72cf7fcef0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804159593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.804159593
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.547981514
Short name T775
Test name
Test status
Simulation time 44708016495 ps
CPU time 93.41 seconds
Started Jul 30 07:14:21 PM PDT 24
Finished Jul 30 07:15:54 PM PDT 24
Peak memory 201364 kb
Host smart-4770e683-4aa9-48fe-a82b-b5e364a7a1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547981514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.547981514
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.299965688
Short name T327
Test name
Test status
Simulation time 5183662630 ps
CPU time 1.85 seconds
Started Jul 30 07:14:21 PM PDT 24
Finished Jul 30 07:14:23 PM PDT 24
Peak memory 201340 kb
Host smart-e1820569-a019-4927-bd52-ce555a251d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299965688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.299965688
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2192203160
Short name T672
Test name
Test status
Simulation time 5896407136 ps
CPU time 14.53 seconds
Started Jul 30 07:14:13 PM PDT 24
Finished Jul 30 07:14:27 PM PDT 24
Peak memory 201352 kb
Host smart-30ec5542-e8ae-4695-8a55-56d1c056b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192203160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2192203160
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.494563108
Short name T729
Test name
Test status
Simulation time 341012240890 ps
CPU time 133.54 seconds
Started Jul 30 07:14:29 PM PDT 24
Finished Jul 30 07:16:43 PM PDT 24
Peak memory 201448 kb
Host smart-e2c4dac7-f7f8-4eff-8e7e-e058ca5d6f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494563108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
494563108
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1115656033
Short name T255
Test name
Test status
Simulation time 145909801930 ps
CPU time 200.93 seconds
Started Jul 30 07:14:26 PM PDT 24
Finished Jul 30 07:17:47 PM PDT 24
Peak memory 210136 kb
Host smart-a5cf3a70-5c0e-4a03-87df-725e50bc16d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115656033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1115656033
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3609355952
Short name T401
Test name
Test status
Simulation time 325114828 ps
CPU time 0.99 seconds
Started Jul 30 07:14:57 PM PDT 24
Finished Jul 30 07:14:58 PM PDT 24
Peak memory 201228 kb
Host smart-264fa4a8-bb6b-4517-875e-f69c961bcd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609355952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3609355952
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3095936419
Short name T99
Test name
Test status
Simulation time 189491797033 ps
CPU time 77.3 seconds
Started Jul 30 07:14:42 PM PDT 24
Finished Jul 30 07:15:59 PM PDT 24
Peak memory 201504 kb
Host smart-dcd5e7af-14dd-45b2-8ad9-118dc02a35ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095936419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3095936419
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3916709749
Short name T180
Test name
Test status
Simulation time 486567455387 ps
CPU time 143.08 seconds
Started Jul 30 07:14:33 PM PDT 24
Finished Jul 30 07:16:56 PM PDT 24
Peak memory 201528 kb
Host smart-53dd0c3b-80f0-418f-8b73-22c869c5d3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916709749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3916709749
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2268947451
Short name T471
Test name
Test status
Simulation time 163790666436 ps
CPU time 171.5 seconds
Started Jul 30 07:14:34 PM PDT 24
Finished Jul 30 07:17:26 PM PDT 24
Peak memory 201552 kb
Host smart-f9e46289-b303-44a2-9aaf-16c6c84484a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268947451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2268947451
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1248693479
Short name T631
Test name
Test status
Simulation time 490803064129 ps
CPU time 269.16 seconds
Started Jul 30 07:14:34 PM PDT 24
Finished Jul 30 07:19:03 PM PDT 24
Peak memory 201396 kb
Host smart-c263b9c2-59d5-4136-8e14-32258750934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248693479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1248693479
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1121552597
Short name T377
Test name
Test status
Simulation time 159428685917 ps
CPU time 251.85 seconds
Started Jul 30 07:14:34 PM PDT 24
Finished Jul 30 07:18:45 PM PDT 24
Peak memory 201456 kb
Host smart-8f1a1087-6e1c-423a-9724-d3c91d791088
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121552597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1121552597
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1691199431
Short name T294
Test name
Test status
Simulation time 360398550397 ps
CPU time 401.4 seconds
Started Jul 30 07:14:37 PM PDT 24
Finished Jul 30 07:21:19 PM PDT 24
Peak memory 201496 kb
Host smart-0d78ba36-36fd-4889-b14e-152063ebcdeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691199431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1691199431
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3724504977
Short name T451
Test name
Test status
Simulation time 605668372890 ps
CPU time 721.8 seconds
Started Jul 30 07:14:37 PM PDT 24
Finished Jul 30 07:26:39 PM PDT 24
Peak memory 201504 kb
Host smart-ffa0fa89-f93f-427b-8cfc-6f477b1b9fd0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724504977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3724504977
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1248112588
Short name T198
Test name
Test status
Simulation time 82669491206 ps
CPU time 384.03 seconds
Started Jul 30 07:14:48 PM PDT 24
Finished Jul 30 07:21:13 PM PDT 24
Peak memory 201884 kb
Host smart-7178c120-1a28-4d8d-ba01-c8c931d2a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248112588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1248112588
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.873047586
Short name T372
Test name
Test status
Simulation time 27712652986 ps
CPU time 28.44 seconds
Started Jul 30 07:14:49 PM PDT 24
Finished Jul 30 07:15:18 PM PDT 24
Peak memory 201308 kb
Host smart-4e4f3056-3ff8-4906-947a-2c7f386491b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873047586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.873047586
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1155678423
Short name T353
Test name
Test status
Simulation time 3409198960 ps
CPU time 8.66 seconds
Started Jul 30 07:14:42 PM PDT 24
Finished Jul 30 07:14:50 PM PDT 24
Peak memory 201360 kb
Host smart-9f0f5b99-b9f4-4593-b5a3-c48c48cf8ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155678423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1155678423
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1839902958
Short name T575
Test name
Test status
Simulation time 5849781645 ps
CPU time 7.08 seconds
Started Jul 30 07:14:28 PM PDT 24
Finished Jul 30 07:14:35 PM PDT 24
Peak memory 201332 kb
Host smart-599493fb-f199-4c39-9fdc-ff90efc05cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839902958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1839902958
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3585152010
Short name T210
Test name
Test status
Simulation time 245752772760 ps
CPU time 246.03 seconds
Started Jul 30 07:14:57 PM PDT 24
Finished Jul 30 07:19:03 PM PDT 24
Peak memory 210016 kb
Host smart-06944d6a-8010-42df-9443-61dbbb515b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585152010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3585152010
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2506959365
Short name T106
Test name
Test status
Simulation time 16217582876 ps
CPU time 38.37 seconds
Started Jul 30 07:14:54 PM PDT 24
Finished Jul 30 07:15:32 PM PDT 24
Peak memory 209820 kb
Host smart-81812c8c-8749-4c43-90e7-3f5937b9d058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506959365 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2506959365
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3840436716
Short name T739
Test name
Test status
Simulation time 522635704 ps
CPU time 1.77 seconds
Started Jul 30 07:15:07 PM PDT 24
Finished Jul 30 07:15:09 PM PDT 24
Peak memory 201244 kb
Host smart-72780603-1663-403f-842f-7c2e97d97ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840436716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3840436716
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2122713819
Short name T526
Test name
Test status
Simulation time 168051313910 ps
CPU time 199.99 seconds
Started Jul 30 07:15:05 PM PDT 24
Finished Jul 30 07:18:25 PM PDT 24
Peak memory 201440 kb
Host smart-02d31c75-e940-43dd-aa88-8011d789309c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122713819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2122713819
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4043349330
Short name T34
Test name
Test status
Simulation time 161982807012 ps
CPU time 193.38 seconds
Started Jul 30 07:15:03 PM PDT 24
Finished Jul 30 07:18:16 PM PDT 24
Peak memory 201420 kb
Host smart-921626f2-267d-4e05-bfc5-0a78ff8605b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043349330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4043349330
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2221631561
Short name T146
Test name
Test status
Simulation time 335955863521 ps
CPU time 197.9 seconds
Started Jul 30 07:15:01 PM PDT 24
Finished Jul 30 07:18:19 PM PDT 24
Peak memory 201420 kb
Host smart-1125e860-4fd6-4a7f-8884-01dd2ee1d677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221631561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2221631561
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1987309566
Short name T756
Test name
Test status
Simulation time 493560020768 ps
CPU time 1162.42 seconds
Started Jul 30 07:15:02 PM PDT 24
Finished Jul 30 07:34:25 PM PDT 24
Peak memory 201488 kb
Host smart-ae6a720b-29f6-4a54-abaa-72862d81fc3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987309566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1987309566
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3954616322
Short name T419
Test name
Test status
Simulation time 326146162341 ps
CPU time 335.77 seconds
Started Jul 30 07:15:01 PM PDT 24
Finished Jul 30 07:20:37 PM PDT 24
Peak memory 201440 kb
Host smart-d6b3c663-20e2-49bb-aeb4-1eb49810bcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954616322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3954616322
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2162912742
Short name T362
Test name
Test status
Simulation time 489268773984 ps
CPU time 327.41 seconds
Started Jul 30 07:15:02 PM PDT 24
Finished Jul 30 07:20:29 PM PDT 24
Peak memory 201404 kb
Host smart-55884108-6f27-4cdb-b477-1f4df1a69292
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162912742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2162912742
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1810294185
Short name T320
Test name
Test status
Simulation time 537712542550 ps
CPU time 313.57 seconds
Started Jul 30 07:15:00 PM PDT 24
Finished Jul 30 07:20:14 PM PDT 24
Peak memory 201480 kb
Host smart-aa6604b7-413e-44e7-9800-9233891ea34b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810294185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1810294185
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2612517700
Short name T671
Test name
Test status
Simulation time 385876648875 ps
CPU time 915.3 seconds
Started Jul 30 07:15:03 PM PDT 24
Finished Jul 30 07:30:19 PM PDT 24
Peak memory 201488 kb
Host smart-eda43f48-c55e-4844-b73e-025cf4bc7202
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612517700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2612517700
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1085951848
Short name T207
Test name
Test status
Simulation time 111433436820 ps
CPU time 587.69 seconds
Started Jul 30 07:15:04 PM PDT 24
Finished Jul 30 07:24:52 PM PDT 24
Peak memory 201872 kb
Host smart-692be8e8-5fa9-401e-9dbf-160c407472a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085951848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1085951848
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1556489527
Short name T35
Test name
Test status
Simulation time 26566584875 ps
CPU time 17.62 seconds
Started Jul 30 07:15:05 PM PDT 24
Finished Jul 30 07:15:23 PM PDT 24
Peak memory 201360 kb
Host smart-58f82548-2ee7-4a3c-87ef-46b8feb4d260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556489527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1556489527
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1149873892
Short name T175
Test name
Test status
Simulation time 4022413719 ps
CPU time 3.16 seconds
Started Jul 30 07:15:04 PM PDT 24
Finished Jul 30 07:15:07 PM PDT 24
Peak memory 201360 kb
Host smart-52bf5338-fb3d-4dfd-8a37-1f36204f9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149873892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1149873892
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2064327505
Short name T513
Test name
Test status
Simulation time 5502412872 ps
CPU time 13.04 seconds
Started Jul 30 07:15:03 PM PDT 24
Finished Jul 30 07:15:16 PM PDT 24
Peak memory 201376 kb
Host smart-1d3a2685-2963-4854-bc6e-7169877f1569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064327505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2064327505
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3300736193
Short name T26
Test name
Test status
Simulation time 31890525996 ps
CPU time 37.18 seconds
Started Jul 30 07:15:08 PM PDT 24
Finished Jul 30 07:15:45 PM PDT 24
Peak memory 209784 kb
Host smart-66c75e42-0e8a-4a3a-a0d0-b4b68c1c87ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300736193 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3300736193
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3750941955
Short name T447
Test name
Test status
Simulation time 512016559 ps
CPU time 0.93 seconds
Started Jul 30 07:15:20 PM PDT 24
Finished Jul 30 07:15:21 PM PDT 24
Peak memory 201236 kb
Host smart-a4ddb528-bc07-40a7-973d-f5a49f8a341f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750941955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3750941955
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1850328649
Short name T604
Test name
Test status
Simulation time 163474245171 ps
CPU time 27.4 seconds
Started Jul 30 07:15:20 PM PDT 24
Finished Jul 30 07:15:48 PM PDT 24
Peak memory 201432 kb
Host smart-1a7e562a-dd5c-4fa2-a88a-b7f236d03c18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850328649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1850328649
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.885622267
Short name T548
Test name
Test status
Simulation time 342147581588 ps
CPU time 811.62 seconds
Started Jul 30 07:15:22 PM PDT 24
Finished Jul 30 07:28:54 PM PDT 24
Peak memory 201552 kb
Host smart-c3b66bb7-a46a-46e8-ad71-7b8952bc3532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885622267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.885622267
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.862315647
Short name T12
Test name
Test status
Simulation time 164679827326 ps
CPU time 91.27 seconds
Started Jul 30 07:15:11 PM PDT 24
Finished Jul 30 07:16:43 PM PDT 24
Peak memory 201496 kb
Host smart-6826ca31-767d-434b-b1c9-d735f7d314f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862315647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.862315647
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1660803456
Short name T673
Test name
Test status
Simulation time 330000439012 ps
CPU time 770.35 seconds
Started Jul 30 07:15:12 PM PDT 24
Finished Jul 30 07:28:03 PM PDT 24
Peak memory 201492 kb
Host smart-87f2a5fc-6182-4aab-be8f-27fe859af02d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660803456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1660803456
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4289154005
Short name T396
Test name
Test status
Simulation time 336293647926 ps
CPU time 196.55 seconds
Started Jul 30 07:15:09 PM PDT 24
Finished Jul 30 07:18:26 PM PDT 24
Peak memory 201480 kb
Host smart-f7c3554c-e608-4fb5-9ca0-eb818ce6ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289154005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4289154005
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4042709484
Short name T119
Test name
Test status
Simulation time 165651006177 ps
CPU time 50.47 seconds
Started Jul 30 07:15:11 PM PDT 24
Finished Jul 30 07:16:02 PM PDT 24
Peak memory 201456 kb
Host smart-04031153-119b-4b3f-8c76-d59a0ded3485
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042709484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4042709484
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.99930509
Short name T263
Test name
Test status
Simulation time 245871080277 ps
CPU time 481.67 seconds
Started Jul 30 07:15:12 PM PDT 24
Finished Jul 30 07:23:14 PM PDT 24
Peak memory 201416 kb
Host smart-c9ac86c2-bad1-4a7a-8333-6df2fd76ed3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99930509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_w
akeup.99930509
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.774504538
Short name T460
Test name
Test status
Simulation time 600031492983 ps
CPU time 1265.38 seconds
Started Jul 30 07:15:16 PM PDT 24
Finished Jul 30 07:36:22 PM PDT 24
Peak memory 201472 kb
Host smart-1b685697-a46e-4b0b-aaa6-cbabb2340ae5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774504538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.774504538
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3646894927
Short name T324
Test name
Test status
Simulation time 120911268714 ps
CPU time 380.56 seconds
Started Jul 30 07:15:18 PM PDT 24
Finished Jul 30 07:21:39 PM PDT 24
Peak memory 201836 kb
Host smart-cbc17d25-5b24-4fab-82e5-627f0103b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646894927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3646894927
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2814313492
Short name T710
Test name
Test status
Simulation time 30000782991 ps
CPU time 17.72 seconds
Started Jul 30 07:15:20 PM PDT 24
Finished Jul 30 07:15:37 PM PDT 24
Peak memory 201376 kb
Host smart-087285d9-7173-45f4-927f-83568c99c593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814313492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2814313492
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3642839106
Short name T784
Test name
Test status
Simulation time 3234540991 ps
CPU time 4.24 seconds
Started Jul 30 07:15:17 PM PDT 24
Finished Jul 30 07:15:21 PM PDT 24
Peak memory 201396 kb
Host smart-9309e29f-1b44-42c6-9927-34bcd63730a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642839106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3642839106
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1209127844
Short name T648
Test name
Test status
Simulation time 5968011142 ps
CPU time 8.31 seconds
Started Jul 30 07:15:09 PM PDT 24
Finished Jul 30 07:15:17 PM PDT 24
Peak memory 201404 kb
Host smart-6f74c585-f0aa-49ee-917f-0830f44226bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209127844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1209127844
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1069877401
Short name T423
Test name
Test status
Simulation time 343858096235 ps
CPU time 668.23 seconds
Started Jul 30 07:15:18 PM PDT 24
Finished Jul 30 07:26:27 PM PDT 24
Peak memory 201448 kb
Host smart-de31a191-326b-4a76-8ab8-127b382ece6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069877401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1069877401
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.4176400658
Short name T19
Test name
Test status
Simulation time 589757732517 ps
CPU time 217.13 seconds
Started Jul 30 07:15:20 PM PDT 24
Finished Jul 30 07:18:57 PM PDT 24
Peak memory 209768 kb
Host smart-946b6675-3307-4705-840d-e8c30ca1585c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176400658 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.4176400658
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3495088066
Short name T695
Test name
Test status
Simulation time 350832125 ps
CPU time 1.33 seconds
Started Jul 30 07:15:41 PM PDT 24
Finished Jul 30 07:15:42 PM PDT 24
Peak memory 201184 kb
Host smart-9fc72b0e-5641-4fde-bac4-624abcbd4af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495088066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3495088066
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.49537362
Short name T652
Test name
Test status
Simulation time 406348927263 ps
CPU time 170.83 seconds
Started Jul 30 07:15:31 PM PDT 24
Finished Jul 30 07:18:22 PM PDT 24
Peak memory 201476 kb
Host smart-bd634258-f633-4559-8abe-70200d2e09cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49537362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gatin
g.49537362
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.4064442975
Short name T95
Test name
Test status
Simulation time 166677708832 ps
CPU time 372.32 seconds
Started Jul 30 07:15:43 PM PDT 24
Finished Jul 30 07:21:55 PM PDT 24
Peak memory 201412 kb
Host smart-9c157b19-91e4-4544-9d65-5332f7c85ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064442975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4064442975
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2926434687
Short name T711
Test name
Test status
Simulation time 335107428810 ps
CPU time 788.46 seconds
Started Jul 30 07:15:27 PM PDT 24
Finished Jul 30 07:28:36 PM PDT 24
Peak memory 201408 kb
Host smart-2b0c502d-ab2f-46e0-a1f6-2da0b9273406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926434687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2926434687
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.703295574
Short name T720
Test name
Test status
Simulation time 494049728336 ps
CPU time 291.66 seconds
Started Jul 30 07:15:29 PM PDT 24
Finished Jul 30 07:20:21 PM PDT 24
Peak memory 201492 kb
Host smart-a32b3aea-d49a-4297-b97a-937c6636cd8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=703295574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.703295574
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1418138548
Short name T305
Test name
Test status
Simulation time 316055863705 ps
CPU time 727.62 seconds
Started Jul 30 07:15:23 PM PDT 24
Finished Jul 30 07:27:31 PM PDT 24
Peak memory 201556 kb
Host smart-14ab17ef-4eac-4164-8970-aba0fddde729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418138548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1418138548
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.413908380
Short name T718
Test name
Test status
Simulation time 490800580828 ps
CPU time 288.14 seconds
Started Jul 30 07:15:22 PM PDT 24
Finished Jul 30 07:20:10 PM PDT 24
Peak memory 201412 kb
Host smart-07ee4f6d-2c16-4280-8bd3-0efa686e3f55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=413908380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.413908380
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.113792242
Short name T13
Test name
Test status
Simulation time 176554227686 ps
CPU time 112.67 seconds
Started Jul 30 07:15:30 PM PDT 24
Finished Jul 30 07:17:23 PM PDT 24
Peak memory 201352 kb
Host smart-3c6a6823-23c0-4f60-a84a-e1094a019d60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113792242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.113792242
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3001575138
Short name T483
Test name
Test status
Simulation time 193518006075 ps
CPU time 83.01 seconds
Started Jul 30 07:15:29 PM PDT 24
Finished Jul 30 07:16:52 PM PDT 24
Peak memory 201424 kb
Host smart-cbde2581-ef20-4304-a0a9-5bd047e5b2a8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001575138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3001575138
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2918830291
Short name T201
Test name
Test status
Simulation time 100929841895 ps
CPU time 362.26 seconds
Started Jul 30 07:15:38 PM PDT 24
Finished Jul 30 07:21:40 PM PDT 24
Peak memory 201812 kb
Host smart-1322b6cf-a0ad-4728-8a31-a6ebae93925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918830291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2918830291
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2660973124
Short name T446
Test name
Test status
Simulation time 26354008988 ps
CPU time 11.79 seconds
Started Jul 30 07:15:38 PM PDT 24
Finished Jul 30 07:15:50 PM PDT 24
Peak memory 201304 kb
Host smart-30bc15d2-ca8d-49d0-969a-4cc683a46de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660973124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2660973124
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3323217296
Short name T601
Test name
Test status
Simulation time 4265386782 ps
CPU time 5.45 seconds
Started Jul 30 07:15:35 PM PDT 24
Finished Jul 30 07:15:41 PM PDT 24
Peak memory 201340 kb
Host smart-64d0402f-6942-42de-a1a5-b1beede6a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323217296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3323217296
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2512135769
Short name T536
Test name
Test status
Simulation time 5875722589 ps
CPU time 13.71 seconds
Started Jul 30 07:15:22 PM PDT 24
Finished Jul 30 07:15:36 PM PDT 24
Peak memory 201392 kb
Host smart-b15d55de-ea04-4f50-bc08-2c44f2e4d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512135769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2512135769
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1000784502
Short name T494
Test name
Test status
Simulation time 109254813257 ps
CPU time 206.24 seconds
Started Jul 30 07:15:38 PM PDT 24
Finished Jul 30 07:19:04 PM PDT 24
Peak memory 218428 kb
Host smart-3291f459-2992-4570-80cc-ae977da7b416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000784502 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1000784502
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1559172646
Short name T647
Test name
Test status
Simulation time 324701616 ps
CPU time 0.78 seconds
Started Jul 30 07:15:55 PM PDT 24
Finished Jul 30 07:15:56 PM PDT 24
Peak memory 201076 kb
Host smart-1d9a8a0a-e0cb-4480-b174-a99129812a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559172646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1559172646
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3116018555
Short name T296
Test name
Test status
Simulation time 337660437695 ps
CPU time 410.3 seconds
Started Jul 30 07:15:55 PM PDT 24
Finished Jul 30 07:22:45 PM PDT 24
Peak memory 201444 kb
Host smart-564f78ae-de8b-482e-9a74-2785240eeb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116018555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3116018555
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1218842101
Short name T509
Test name
Test status
Simulation time 164919090818 ps
CPU time 78.66 seconds
Started Jul 30 07:15:46 PM PDT 24
Finished Jul 30 07:17:05 PM PDT 24
Peak memory 201400 kb
Host smart-9806d117-e61e-44c8-ad4e-ef3fcb8801ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218842101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1218842101
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.136171340
Short name T489
Test name
Test status
Simulation time 161769820640 ps
CPU time 176.63 seconds
Started Jul 30 07:15:45 PM PDT 24
Finished Jul 30 07:18:42 PM PDT 24
Peak memory 201428 kb
Host smart-aea33772-fdbd-4a8e-a9b0-c961a7ec85f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136171340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.136171340
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.444970396
Short name T499
Test name
Test status
Simulation time 494980282328 ps
CPU time 603.96 seconds
Started Jul 30 07:15:45 PM PDT 24
Finished Jul 30 07:25:49 PM PDT 24
Peak memory 201452 kb
Host smart-f6c7c2c9-3884-42f2-b4e3-19b0291a2ea7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=444970396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.444970396
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3518114005
Short name T309
Test name
Test status
Simulation time 353744351178 ps
CPU time 838.52 seconds
Started Jul 30 07:15:49 PM PDT 24
Finished Jul 30 07:29:48 PM PDT 24
Peak memory 201452 kb
Host smart-a2ca3a73-030a-4ca9-a115-38230dae5991
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518114005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3518114005
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1067453950
Short name T665
Test name
Test status
Simulation time 602408677825 ps
CPU time 1404.66 seconds
Started Jul 30 07:15:51 PM PDT 24
Finished Jul 30 07:39:16 PM PDT 24
Peak memory 201416 kb
Host smart-37af2a4b-1812-4a65-bca1-b544428ef3d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067453950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1067453950
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.276358511
Short name T61
Test name
Test status
Simulation time 77938985635 ps
CPU time 328.76 seconds
Started Jul 30 07:15:52 PM PDT 24
Finished Jul 30 07:21:21 PM PDT 24
Peak memory 201832 kb
Host smart-24289b8d-0ca4-479c-9e20-b28bd7d80f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276358511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.276358511
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2582762610
Short name T557
Test name
Test status
Simulation time 31947506575 ps
CPU time 16.25 seconds
Started Jul 30 07:15:54 PM PDT 24
Finished Jul 30 07:16:10 PM PDT 24
Peak memory 201376 kb
Host smart-18d41a81-53e6-432d-b38e-50486da110f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582762610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2582762610
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3611391719
Short name T7
Test name
Test status
Simulation time 3299392798 ps
CPU time 2.88 seconds
Started Jul 30 07:15:53 PM PDT 24
Finished Jul 30 07:15:56 PM PDT 24
Peak memory 201312 kb
Host smart-1eb4c4f6-83e4-474e-9746-4f2a6fe3a0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611391719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3611391719
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2448067528
Short name T670
Test name
Test status
Simulation time 6062679920 ps
CPU time 13.66 seconds
Started Jul 30 07:15:47 PM PDT 24
Finished Jul 30 07:16:01 PM PDT 24
Peak memory 201396 kb
Host smart-82b4c04d-b915-4b08-99d4-08c93106ee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448067528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2448067528
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2537486979
Short name T284
Test name
Test status
Simulation time 210081849988 ps
CPU time 471.14 seconds
Started Jul 30 07:15:52 PM PDT 24
Finished Jul 30 07:23:44 PM PDT 24
Peak memory 201516 kb
Host smart-ab5a3a48-d9ee-4b9e-9a32-ba406d8a23b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537486979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2537486979
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.90450349
Short name T539
Test name
Test status
Simulation time 303253949 ps
CPU time 0.81 seconds
Started Jul 30 07:07:24 PM PDT 24
Finished Jul 30 07:07:25 PM PDT 24
Peak memory 201244 kb
Host smart-7bf96575-607b-4a8c-abc4-9f1d12b0fca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90450349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.90450349
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3515099507
Short name T173
Test name
Test status
Simulation time 365868757241 ps
CPU time 79.28 seconds
Started Jul 30 07:07:15 PM PDT 24
Finished Jul 30 07:08:34 PM PDT 24
Peak memory 201488 kb
Host smart-03a28596-5a49-4eef-a9bd-639058d26659
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515099507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3515099507
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.371252901
Short name T52
Test name
Test status
Simulation time 342061650742 ps
CPU time 283.77 seconds
Started Jul 30 07:07:07 PM PDT 24
Finished Jul 30 07:11:51 PM PDT 24
Peak memory 201444 kb
Host smart-d568c0fa-2af2-4c29-9f73-f29175152e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371252901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.371252901
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3281383226
Short name T639
Test name
Test status
Simulation time 327226959739 ps
CPU time 94.3 seconds
Started Jul 30 07:07:10 PM PDT 24
Finished Jul 30 07:08:44 PM PDT 24
Peak memory 201488 kb
Host smart-9df07193-c859-486f-83c4-bb58bf92df79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281383226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3281383226
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4243607224
Short name T316
Test name
Test status
Simulation time 331677887451 ps
CPU time 710.71 seconds
Started Jul 30 07:07:06 PM PDT 24
Finished Jul 30 07:18:57 PM PDT 24
Peak memory 201436 kb
Host smart-20f21b33-0e4e-4a08-bc79-47fa8c1fc462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243607224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4243607224
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1270431778
Short name T545
Test name
Test status
Simulation time 164246132953 ps
CPU time 66.07 seconds
Started Jul 30 07:07:05 PM PDT 24
Finished Jul 30 07:08:11 PM PDT 24
Peak memory 201440 kb
Host smart-26141555-b24c-4686-bdaf-1eb6adaac287
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270431778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1270431778
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3524422992
Short name T117
Test name
Test status
Simulation time 359393019981 ps
CPU time 197.01 seconds
Started Jul 30 07:07:11 PM PDT 24
Finished Jul 30 07:10:29 PM PDT 24
Peak memory 201400 kb
Host smart-517cbc7f-af24-4485-9e4d-d9500dd32181
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524422992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3524422992
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.504355894
Short name T383
Test name
Test status
Simulation time 602354964718 ps
CPU time 359.91 seconds
Started Jul 30 07:07:17 PM PDT 24
Finished Jul 30 07:13:17 PM PDT 24
Peak memory 201416 kb
Host smart-7d845cff-acd1-48fb-9d41-c20dd606c65a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504355894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.504355894
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2432975390
Short name T203
Test name
Test status
Simulation time 117876421106 ps
CPU time 611.82 seconds
Started Jul 30 07:07:21 PM PDT 24
Finished Jul 30 07:17:33 PM PDT 24
Peak memory 201848 kb
Host smart-95d3d1d6-31da-4e18-9899-a522d5ef36dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432975390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2432975390
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3472714343
Short name T416
Test name
Test status
Simulation time 32080634201 ps
CPU time 18.32 seconds
Started Jul 30 07:07:17 PM PDT 24
Finished Jul 30 07:07:35 PM PDT 24
Peak memory 201400 kb
Host smart-80b3728e-b871-41ae-a7fb-d9e9656d1c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472714343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3472714343
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3093315987
Short name T681
Test name
Test status
Simulation time 3165503380 ps
CPU time 4.8 seconds
Started Jul 30 07:07:15 PM PDT 24
Finished Jul 30 07:07:20 PM PDT 24
Peak memory 201516 kb
Host smart-b0da491c-b69e-49c9-8dcf-b742c850c189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093315987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3093315987
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3598963798
Short name T94
Test name
Test status
Simulation time 8245053914 ps
CPU time 20.36 seconds
Started Jul 30 07:07:23 PM PDT 24
Finished Jul 30 07:07:44 PM PDT 24
Peak memory 218232 kb
Host smart-d52621fd-091b-4d18-896f-77c1533eab10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598963798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3598963798
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1314394109
Short name T620
Test name
Test status
Simulation time 6018880068 ps
CPU time 14.58 seconds
Started Jul 30 07:07:05 PM PDT 24
Finished Jul 30 07:07:20 PM PDT 24
Peak memory 201400 kb
Host smart-31c3a2e3-ad34-4611-9293-ba1627d37278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314394109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1314394109
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2493326753
Short name T37
Test name
Test status
Simulation time 17590050089 ps
CPU time 20.71 seconds
Started Jul 30 07:07:20 PM PDT 24
Finished Jul 30 07:07:40 PM PDT 24
Peak memory 201428 kb
Host smart-be3c74a9-c67b-4289-8835-b787b9e9169a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493326753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2493326753
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3816379081
Short name T20
Test name
Test status
Simulation time 39405726481 ps
CPU time 116.1 seconds
Started Jul 30 07:07:18 PM PDT 24
Finished Jul 30 07:09:14 PM PDT 24
Peak memory 210216 kb
Host smart-56b03648-8e02-4f42-a6cb-cb39add70555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816379081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3816379081
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1098622286
Short name T473
Test name
Test status
Simulation time 379259057 ps
CPU time 0.88 seconds
Started Jul 30 07:16:16 PM PDT 24
Finished Jul 30 07:16:17 PM PDT 24
Peak memory 201184 kb
Host smart-472a4610-e1b2-48c8-a8e6-d44c416e2e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098622286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1098622286
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2541054371
Short name T253
Test name
Test status
Simulation time 165742720821 ps
CPU time 101.71 seconds
Started Jul 30 07:16:08 PM PDT 24
Finished Jul 30 07:17:50 PM PDT 24
Peak memory 201504 kb
Host smart-056fda1b-530e-416d-9785-c6b3019b8da5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541054371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2541054371
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3135159953
Short name T280
Test name
Test status
Simulation time 342292658703 ps
CPU time 206.16 seconds
Started Jul 30 07:16:08 PM PDT 24
Finished Jul 30 07:19:34 PM PDT 24
Peak memory 201460 kb
Host smart-2888512c-d2d2-4fb6-8dc6-9a5fb9b09b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135159953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3135159953
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3859910996
Short name T776
Test name
Test status
Simulation time 492167461796 ps
CPU time 1103.42 seconds
Started Jul 30 07:16:04 PM PDT 24
Finished Jul 30 07:34:27 PM PDT 24
Peak memory 201460 kb
Host smart-5451a529-5a2e-42cd-ae5a-eea1791abaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859910996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3859910996
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1361801683
Short name T754
Test name
Test status
Simulation time 322945112694 ps
CPU time 175.22 seconds
Started Jul 30 07:16:04 PM PDT 24
Finished Jul 30 07:19:00 PM PDT 24
Peak memory 201496 kb
Host smart-7df5d6f0-c7ef-4031-a3ae-3cc3474f7e31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361801683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1361801683
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2638344821
Short name T580
Test name
Test status
Simulation time 162714077398 ps
CPU time 157.2 seconds
Started Jul 30 07:16:04 PM PDT 24
Finished Jul 30 07:18:42 PM PDT 24
Peak memory 201496 kb
Host smart-539f3bf2-7856-4ba2-9b3f-1eccbd2bcb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638344821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2638344821
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2957502702
Short name T439
Test name
Test status
Simulation time 492561748888 ps
CPU time 1133.76 seconds
Started Jul 30 07:16:04 PM PDT 24
Finished Jul 30 07:34:58 PM PDT 24
Peak memory 201460 kb
Host smart-fba9c1fa-9e4d-420b-8834-c15752ed275c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957502702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2957502702
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1832809417
Short name T400
Test name
Test status
Simulation time 198336167106 ps
CPU time 111.96 seconds
Started Jul 30 07:16:08 PM PDT 24
Finished Jul 30 07:18:00 PM PDT 24
Peak memory 201456 kb
Host smart-3a14c2fe-9a62-45b9-91e2-c70ac5f48ad0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832809417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1832809417
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2693993393
Short name T527
Test name
Test status
Simulation time 207452717562 ps
CPU time 458.38 seconds
Started Jul 30 07:16:06 PM PDT 24
Finished Jul 30 07:23:45 PM PDT 24
Peak memory 201372 kb
Host smart-5dadd92b-6677-47d0-b976-db807f9301da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693993393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2693993393
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1491675945
Short name T64
Test name
Test status
Simulation time 96708904160 ps
CPU time 480.74 seconds
Started Jul 30 07:16:13 PM PDT 24
Finished Jul 30 07:24:14 PM PDT 24
Peak memory 201836 kb
Host smart-c61f61c2-c35b-489c-b62d-e1093b02b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491675945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1491675945
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2138689398
Short name T734
Test name
Test status
Simulation time 39048213672 ps
CPU time 47.96 seconds
Started Jul 30 07:16:13 PM PDT 24
Finished Jul 30 07:17:01 PM PDT 24
Peak memory 201348 kb
Host smart-1afbb7f8-d98c-4462-82cd-59bf4df8f707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138689398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2138689398
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1657063893
Short name T188
Test name
Test status
Simulation time 3697223377 ps
CPU time 3.43 seconds
Started Jul 30 07:16:09 PM PDT 24
Finished Jul 30 07:16:12 PM PDT 24
Peak memory 201364 kb
Host smart-c98ebe05-6d9e-43f9-8245-1c8f45b80e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657063893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1657063893
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3454691888
Short name T459
Test name
Test status
Simulation time 5977632391 ps
CPU time 14.83 seconds
Started Jul 30 07:16:03 PM PDT 24
Finished Jul 30 07:16:18 PM PDT 24
Peak memory 201368 kb
Host smart-28e179d0-8ba8-480f-910f-117496ca976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454691888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3454691888
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2996701403
Short name T38
Test name
Test status
Simulation time 227894842420 ps
CPU time 503.21 seconds
Started Jul 30 07:16:16 PM PDT 24
Finished Jul 30 07:24:39 PM PDT 24
Peak memory 201476 kb
Host smart-e84f0fa9-f99b-4b81-b1c1-67cb0ee8fcfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996701403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2996701403
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2773500297
Short name T115
Test name
Test status
Simulation time 53020535720 ps
CPU time 123.29 seconds
Started Jul 30 07:16:11 PM PDT 24
Finished Jul 30 07:18:15 PM PDT 24
Peak memory 201612 kb
Host smart-0ae97a95-d74b-4446-80b8-6e4f8a32b514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773500297 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2773500297
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.811293608
Short name T781
Test name
Test status
Simulation time 337117174 ps
CPU time 1.32 seconds
Started Jul 30 07:16:31 PM PDT 24
Finished Jul 30 07:16:32 PM PDT 24
Peak memory 201232 kb
Host smart-9202ac3e-3ab8-44d0-974a-ea54e5f9b0d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811293608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.811293608
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2693761643
Short name T468
Test name
Test status
Simulation time 319547441480 ps
CPU time 190.29 seconds
Started Jul 30 07:16:23 PM PDT 24
Finished Jul 30 07:19:33 PM PDT 24
Peak memory 201440 kb
Host smart-647650b6-015c-4e0e-8b5a-8faf152c1e27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693761643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2693761643
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2540005295
Short name T124
Test name
Test status
Simulation time 334358917427 ps
CPU time 749.49 seconds
Started Jul 30 07:16:23 PM PDT 24
Finished Jul 30 07:28:53 PM PDT 24
Peak memory 201380 kb
Host smart-a6443cf9-7366-49df-8e17-149ef7aa3c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540005295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2540005295
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4014701851
Short name T726
Test name
Test status
Simulation time 325993973055 ps
CPU time 808.44 seconds
Started Jul 30 07:16:19 PM PDT 24
Finished Jul 30 07:29:48 PM PDT 24
Peak memory 201440 kb
Host smart-fa1f304e-555d-418e-9ee7-4126b7ff9493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014701851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4014701851
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2316279635
Short name T556
Test name
Test status
Simulation time 337174510858 ps
CPU time 73.31 seconds
Started Jul 30 07:16:22 PM PDT 24
Finished Jul 30 07:17:36 PM PDT 24
Peak memory 201472 kb
Host smart-72c3f802-7151-415b-bed6-3bedfb0ac5d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316279635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2316279635
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2234155666
Short name T185
Test name
Test status
Simulation time 328669098658 ps
CPU time 799.41 seconds
Started Jul 30 07:16:20 PM PDT 24
Finished Jul 30 07:29:40 PM PDT 24
Peak memory 201460 kb
Host smart-7865c175-2bb0-4c7e-a376-4afa91a74ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234155666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2234155666
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.273599660
Short name T638
Test name
Test status
Simulation time 163404893489 ps
CPU time 96.85 seconds
Started Jul 30 07:16:21 PM PDT 24
Finished Jul 30 07:17:58 PM PDT 24
Peak memory 201444 kb
Host smart-00e1b25a-107d-47df-a298-1cda59b2dd43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=273599660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.273599660
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1669779115
Short name T259
Test name
Test status
Simulation time 179939788293 ps
CPU time 410.09 seconds
Started Jul 30 07:16:23 PM PDT 24
Finished Jul 30 07:23:14 PM PDT 24
Peak memory 201416 kb
Host smart-801aea35-8a6d-4d32-a387-c7c7f7e31127
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669779115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1669779115
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3513259532
Short name T402
Test name
Test status
Simulation time 382134700292 ps
CPU time 879.59 seconds
Started Jul 30 07:16:22 PM PDT 24
Finished Jul 30 07:31:02 PM PDT 24
Peak memory 201444 kb
Host smart-94b3e470-9d7a-4eb3-ba3a-4ba64c963786
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513259532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3513259532
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3924732648
Short name T529
Test name
Test status
Simulation time 87014293586 ps
CPU time 458.55 seconds
Started Jul 30 07:16:26 PM PDT 24
Finished Jul 30 07:24:05 PM PDT 24
Peak memory 201780 kb
Host smart-7ff69274-772d-4026-8e2a-ae07855e888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924732648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3924732648
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2306571992
Short name T696
Test name
Test status
Simulation time 36879370324 ps
CPU time 23.33 seconds
Started Jul 30 07:16:27 PM PDT 24
Finished Jul 30 07:16:51 PM PDT 24
Peak memory 201368 kb
Host smart-6d16fbf3-e994-43fa-be1f-368448521c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306571992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2306571992
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2475407229
Short name T549
Test name
Test status
Simulation time 3948224819 ps
CPU time 1.71 seconds
Started Jul 30 07:16:22 PM PDT 24
Finished Jul 30 07:16:24 PM PDT 24
Peak memory 201336 kb
Host smart-85bcba65-a239-4b39-b0c8-e0c095c33a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475407229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2475407229
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.4035654584
Short name T764
Test name
Test status
Simulation time 5857792912 ps
CPU time 8.18 seconds
Started Jul 30 07:16:16 PM PDT 24
Finished Jul 30 07:16:25 PM PDT 24
Peak memory 201356 kb
Host smart-a80b48da-aa61-4b6d-8a09-6722db30cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035654584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.4035654584
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2439872091
Short name T679
Test name
Test status
Simulation time 10030955756 ps
CPU time 11.33 seconds
Started Jul 30 07:16:25 PM PDT 24
Finished Jul 30 07:16:37 PM PDT 24
Peak memory 201356 kb
Host smart-823c5513-1822-4023-a1f4-7bc1bf8a1900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439872091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2439872091
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.349242067
Short name T581
Test name
Test status
Simulation time 14119405007 ps
CPU time 27.92 seconds
Started Jul 30 07:16:29 PM PDT 24
Finished Jul 30 07:16:57 PM PDT 24
Peak memory 210168 kb
Host smart-0a28b26a-86df-441d-8c70-fa50f3e9606a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349242067 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.349242067
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1436520780
Short name T486
Test name
Test status
Simulation time 413652583 ps
CPU time 1.45 seconds
Started Jul 30 07:16:55 PM PDT 24
Finished Jul 30 07:16:57 PM PDT 24
Peak memory 201224 kb
Host smart-03faea28-0e2a-48e8-b385-6867a5149551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436520780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1436520780
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.236276429
Short name T170
Test name
Test status
Simulation time 519877462512 ps
CPU time 518.48 seconds
Started Jul 30 07:16:46 PM PDT 24
Finished Jul 30 07:25:25 PM PDT 24
Peak memory 201504 kb
Host smart-4e2997cc-8b7a-437c-b096-2c139164f985
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236276429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.236276429
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2391295234
Short name T786
Test name
Test status
Simulation time 341157361355 ps
CPU time 72.03 seconds
Started Jul 30 07:16:47 PM PDT 24
Finished Jul 30 07:17:59 PM PDT 24
Peak memory 201452 kb
Host smart-05a32f4e-2fbb-4555-bd9e-9cdcb4dfe2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391295234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2391295234
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3230557380
Short name T492
Test name
Test status
Simulation time 167933751789 ps
CPU time 203.41 seconds
Started Jul 30 07:16:34 PM PDT 24
Finished Jul 30 07:19:57 PM PDT 24
Peak memory 201464 kb
Host smart-5c69243d-8cdb-4e66-baa9-0012e7f4ade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230557380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3230557380
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1413545813
Short name T547
Test name
Test status
Simulation time 334018072947 ps
CPU time 778.45 seconds
Started Jul 30 07:16:32 PM PDT 24
Finished Jul 30 07:29:31 PM PDT 24
Peak memory 201484 kb
Host smart-1f23f0ea-42f1-4b95-944a-d3a7f8519600
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413545813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1413545813
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3155183377
Short name T347
Test name
Test status
Simulation time 165768394199 ps
CPU time 60.56 seconds
Started Jul 30 07:16:33 PM PDT 24
Finished Jul 30 07:17:34 PM PDT 24
Peak memory 201436 kb
Host smart-c2037eca-8340-4ced-b8ee-661790f1d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155183377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3155183377
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.74784512
Short name T351
Test name
Test status
Simulation time 167376825110 ps
CPU time 103.37 seconds
Started Jul 30 07:16:33 PM PDT 24
Finished Jul 30 07:18:16 PM PDT 24
Peak memory 201420 kb
Host smart-c5ed5522-c213-4f19-ac69-8737fca00134
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74784512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed
.74784512
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.343955396
Short name T735
Test name
Test status
Simulation time 202335511739 ps
CPU time 121.52 seconds
Started Jul 30 07:16:45 PM PDT 24
Finished Jul 30 07:18:47 PM PDT 24
Peak memory 201432 kb
Host smart-402eafb0-ffcf-47ca-b639-a4a742c804b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343955396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.343955396
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3900430867
Short name T503
Test name
Test status
Simulation time 101883276938 ps
CPU time 571.21 seconds
Started Jul 30 07:16:52 PM PDT 24
Finished Jul 30 07:26:24 PM PDT 24
Peak memory 201920 kb
Host smart-c97303b2-bb73-4fd1-8e9f-45596c0415bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900430867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3900430867
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1887092867
Short name T777
Test name
Test status
Simulation time 25323737286 ps
CPU time 57.45 seconds
Started Jul 30 07:16:49 PM PDT 24
Finished Jul 30 07:17:47 PM PDT 24
Peak memory 201404 kb
Host smart-40114bf4-f636-4ffc-b9af-d8c5e7aa7408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887092867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1887092867
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2639592483
Short name T789
Test name
Test status
Simulation time 3588165072 ps
CPU time 8.3 seconds
Started Jul 30 07:16:47 PM PDT 24
Finished Jul 30 07:16:55 PM PDT 24
Peak memory 201196 kb
Host smart-c7722bf5-5b9d-4f6d-8873-b43b5b936619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639592483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2639592483
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.240529186
Short name T586
Test name
Test status
Simulation time 6032996346 ps
CPU time 7.8 seconds
Started Jul 30 07:16:29 PM PDT 24
Finished Jul 30 07:16:37 PM PDT 24
Peak memory 201380 kb
Host smart-f2089ebe-2e7c-4b0a-a7e3-d907d4722d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240529186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.240529186
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1983158316
Short name T755
Test name
Test status
Simulation time 315153841279 ps
CPU time 1133.16 seconds
Started Jul 30 07:16:52 PM PDT 24
Finished Jul 30 07:35:45 PM PDT 24
Peak memory 210116 kb
Host smart-854fd486-56a4-4639-ad17-cc009f28b7ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983158316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1983158316
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2567625941
Short name T637
Test name
Test status
Simulation time 16504068719 ps
CPU time 61.57 seconds
Started Jul 30 07:16:51 PM PDT 24
Finished Jul 30 07:17:53 PM PDT 24
Peak memory 210136 kb
Host smart-02a8e794-5196-4f06-889c-22e0d62be382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567625941 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2567625941
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2749047603
Short name T176
Test name
Test status
Simulation time 460554475 ps
CPU time 0.87 seconds
Started Jul 30 07:17:10 PM PDT 24
Finished Jul 30 07:17:11 PM PDT 24
Peak memory 201236 kb
Host smart-29238fcf-2e72-4f9f-a1c7-d3884ad9287a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749047603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2749047603
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1122235829
Short name T319
Test name
Test status
Simulation time 526162635089 ps
CPU time 1284.85 seconds
Started Jul 30 07:17:03 PM PDT 24
Finished Jul 30 07:38:28 PM PDT 24
Peak memory 201476 kb
Host smart-db70ca66-90d1-4b2e-b9fe-114e04bd877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122235829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1122235829
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1460214979
Short name T279
Test name
Test status
Simulation time 167868148081 ps
CPU time 80.77 seconds
Started Jul 30 07:17:01 PM PDT 24
Finished Jul 30 07:18:22 PM PDT 24
Peak memory 201408 kb
Host smart-0709da10-bb7c-4ed7-b401-f9e34befd417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460214979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1460214979
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2397705043
Short name T712
Test name
Test status
Simulation time 330337709518 ps
CPU time 752.92 seconds
Started Jul 30 07:17:01 PM PDT 24
Finished Jul 30 07:29:34 PM PDT 24
Peak memory 201472 kb
Host smart-3b657595-c5d0-4bbe-b4e6-8d6cd48a0684
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397705043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2397705043
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3548764108
Short name T235
Test name
Test status
Simulation time 495490601536 ps
CPU time 1152.18 seconds
Started Jul 30 07:16:55 PM PDT 24
Finished Jul 30 07:36:08 PM PDT 24
Peak memory 201412 kb
Host smart-d4fbf217-d806-4877-8eba-461c93bf0ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548764108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3548764108
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1783353345
Short name T538
Test name
Test status
Simulation time 325103699129 ps
CPU time 335.13 seconds
Started Jul 30 07:17:01 PM PDT 24
Finished Jul 30 07:22:36 PM PDT 24
Peak memory 201440 kb
Host smart-9516bb50-157d-4f86-a233-eca993e9af1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783353345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1783353345
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2664739125
Short name T772
Test name
Test status
Simulation time 529751264394 ps
CPU time 309.39 seconds
Started Jul 30 07:17:04 PM PDT 24
Finished Jul 30 07:22:14 PM PDT 24
Peak memory 201500 kb
Host smart-93c749bd-06ed-4cb6-b959-607f743cad68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664739125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2664739125
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1669630578
Short name T782
Test name
Test status
Simulation time 406243824097 ps
CPU time 156.67 seconds
Started Jul 30 07:17:03 PM PDT 24
Finished Jul 30 07:19:40 PM PDT 24
Peak memory 201448 kb
Host smart-1601613b-8e92-4ef6-ada8-10a01774659e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669630578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1669630578
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2786235046
Short name T702
Test name
Test status
Simulation time 70117097164 ps
CPU time 257.33 seconds
Started Jul 30 07:17:06 PM PDT 24
Finished Jul 30 07:21:23 PM PDT 24
Peak memory 201868 kb
Host smart-c18c9d96-54dc-47c0-a71c-98ff4f1d3418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786235046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2786235046
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.329717762
Short name T774
Test name
Test status
Simulation time 42270590059 ps
CPU time 39.98 seconds
Started Jul 30 07:17:05 PM PDT 24
Finished Jul 30 07:17:45 PM PDT 24
Peak memory 201396 kb
Host smart-9d946ec6-c816-4708-91ff-d0a9bb267e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329717762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.329717762
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2646389478
Short name T743
Test name
Test status
Simulation time 2835908764 ps
CPU time 8.04 seconds
Started Jul 30 07:17:03 PM PDT 24
Finished Jul 30 07:17:11 PM PDT 24
Peak memory 201344 kb
Host smart-c47f2727-ab18-469c-8d3d-d60ecacbb4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646389478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2646389478
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2828721605
Short name T661
Test name
Test status
Simulation time 5901457748 ps
CPU time 6.56 seconds
Started Jul 30 07:16:55 PM PDT 24
Finished Jul 30 07:17:02 PM PDT 24
Peak memory 201400 kb
Host smart-2adf0a96-2b06-4eef-99c7-117981577868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828721605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2828721605
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3307143960
Short name T500
Test name
Test status
Simulation time 151230162688 ps
CPU time 522.43 seconds
Started Jul 30 07:17:10 PM PDT 24
Finished Jul 30 07:25:52 PM PDT 24
Peak memory 201796 kb
Host smart-c9149148-f195-476c-b058-18af2cdb67a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307143960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3307143960
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1960151182
Short name T645
Test name
Test status
Simulation time 360685440 ps
CPU time 1.46 seconds
Started Jul 30 07:17:28 PM PDT 24
Finished Jul 30 07:17:29 PM PDT 24
Peak memory 201176 kb
Host smart-818cd484-97a3-472c-b6f5-96f14a8535b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960151182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1960151182
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.4194798586
Short name T194
Test name
Test status
Simulation time 169074660201 ps
CPU time 30.91 seconds
Started Jul 30 07:17:17 PM PDT 24
Finished Jul 30 07:17:48 PM PDT 24
Peak memory 201404 kb
Host smart-31323675-28d6-45fb-81d7-dca961ac694f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194798586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.4194798586
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.851944356
Short name T794
Test name
Test status
Simulation time 176150924572 ps
CPU time 197.21 seconds
Started Jul 30 07:17:23 PM PDT 24
Finished Jul 30 07:20:40 PM PDT 24
Peak memory 201440 kb
Host smart-8da2e6c6-61c7-4168-9879-4358487e4787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851944356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.851944356
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.230661373
Short name T365
Test name
Test status
Simulation time 164618702616 ps
CPU time 93.19 seconds
Started Jul 30 07:17:17 PM PDT 24
Finished Jul 30 07:18:50 PM PDT 24
Peak memory 201460 kb
Host smart-87754d3e-b5ab-470e-89fa-248d26bd5803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230661373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.230661373
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4106979702
Short name T336
Test name
Test status
Simulation time 483255725809 ps
CPU time 397.74 seconds
Started Jul 30 07:17:17 PM PDT 24
Finished Jul 30 07:23:55 PM PDT 24
Peak memory 201492 kb
Host smart-e48a475c-91dd-470e-a097-f771a2251f96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106979702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.4106979702
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4241308319
Short name T770
Test name
Test status
Simulation time 168177541072 ps
CPU time 179.92 seconds
Started Jul 30 07:17:10 PM PDT 24
Finished Jul 30 07:20:10 PM PDT 24
Peak memory 201432 kb
Host smart-275ddb79-4f22-4173-bbbc-c9aa99383c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241308319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4241308319
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1086995750
Short name T458
Test name
Test status
Simulation time 331706780036 ps
CPU time 180.74 seconds
Started Jul 30 07:17:14 PM PDT 24
Finished Jul 30 07:20:15 PM PDT 24
Peak memory 201452 kb
Host smart-57607985-3d6c-47ad-8a4f-826f299730ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086995750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1086995750
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2130284223
Short name T623
Test name
Test status
Simulation time 665958555239 ps
CPU time 773.7 seconds
Started Jul 30 07:17:15 PM PDT 24
Finished Jul 30 07:30:09 PM PDT 24
Peak memory 201460 kb
Host smart-83756b5b-cf21-43ee-a696-52e1e8370c93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130284223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2130284223
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1624325733
Short name T346
Test name
Test status
Simulation time 610598265705 ps
CPU time 1090.7 seconds
Started Jul 30 07:17:16 PM PDT 24
Finished Jul 30 07:35:27 PM PDT 24
Peak memory 201432 kb
Host smart-e32753f4-1701-468b-ac24-6cec2af3c6c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624325733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1624325733
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4004289250
Short name T437
Test name
Test status
Simulation time 114827764589 ps
CPU time 524.21 seconds
Started Jul 30 07:17:25 PM PDT 24
Finished Jul 30 07:26:10 PM PDT 24
Peak memory 201812 kb
Host smart-2f1991a7-b5fd-4225-bf2c-542f9fe822ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004289250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4004289250
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.877408527
Short name T663
Test name
Test status
Simulation time 23229460099 ps
CPU time 50.8 seconds
Started Jul 30 07:17:26 PM PDT 24
Finished Jul 30 07:18:17 PM PDT 24
Peak memory 201388 kb
Host smart-3922130b-96fd-4df2-8297-718d39ec5265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877408527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.877408527
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.404650101
Short name T537
Test name
Test status
Simulation time 4247524512 ps
CPU time 2.04 seconds
Started Jul 30 07:17:22 PM PDT 24
Finished Jul 30 07:17:25 PM PDT 24
Peak memory 201340 kb
Host smart-b54325fe-f605-44b8-90ae-2b5cc021ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404650101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.404650101
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1580291928
Short name T342
Test name
Test status
Simulation time 5738863343 ps
CPU time 4.13 seconds
Started Jul 30 07:17:10 PM PDT 24
Finished Jul 30 07:17:15 PM PDT 24
Peak memory 201352 kb
Host smart-54dc60d3-660b-4862-ac55-5ae9f992cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580291928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1580291928
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2588443055
Short name T242
Test name
Test status
Simulation time 657175686819 ps
CPU time 1800 seconds
Started Jul 30 07:17:29 PM PDT 24
Finished Jul 30 07:47:29 PM PDT 24
Peak memory 201868 kb
Host smart-634e9288-a056-4bc2-8820-e1098abcea5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588443055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2588443055
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4102973613
Short name T510
Test name
Test status
Simulation time 65490529086 ps
CPU time 222.94 seconds
Started Jul 30 07:17:30 PM PDT 24
Finished Jul 30 07:21:13 PM PDT 24
Peak memory 217696 kb
Host smart-c015588c-f568-4da9-963e-ea6e70712cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102973613 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4102973613
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1809329419
Short name T490
Test name
Test status
Simulation time 410433052 ps
CPU time 1.5 seconds
Started Jul 30 07:17:47 PM PDT 24
Finished Jul 30 07:17:49 PM PDT 24
Peak memory 201208 kb
Host smart-15db1346-29e1-43d5-bde9-710a5d0462d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809329419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1809329419
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.355859024
Short name T274
Test name
Test status
Simulation time 191898181389 ps
CPU time 154.88 seconds
Started Jul 30 07:17:39 PM PDT 24
Finished Jul 30 07:20:14 PM PDT 24
Peak memory 201444 kb
Host smart-622adf84-24ae-4831-8adb-96a18694dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355859024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.355859024
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1343712772
Short name T733
Test name
Test status
Simulation time 327282028592 ps
CPU time 830.12 seconds
Started Jul 30 07:17:35 PM PDT 24
Finished Jul 30 07:31:25 PM PDT 24
Peak memory 201552 kb
Host smart-b6abaa33-a780-4148-9639-b0633e0dd110
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343712772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1343712772
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4238188276
Short name T281
Test name
Test status
Simulation time 491963256986 ps
CPU time 244.18 seconds
Started Jul 30 07:17:29 PM PDT 24
Finished Jul 30 07:21:33 PM PDT 24
Peak memory 201440 kb
Host smart-36dc8ff6-cac5-4205-bdc3-8a3b95e5689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238188276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4238188276
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3354321759
Short name T773
Test name
Test status
Simulation time 489345856090 ps
CPU time 1075.94 seconds
Started Jul 30 07:17:28 PM PDT 24
Finished Jul 30 07:35:24 PM PDT 24
Peak memory 201444 kb
Host smart-59450ba2-e9de-440d-b2cb-a434f944962f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354321759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3354321759
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3664826034
Short name T599
Test name
Test status
Simulation time 341485070937 ps
CPU time 808.46 seconds
Started Jul 30 07:17:36 PM PDT 24
Finished Jul 30 07:31:05 PM PDT 24
Peak memory 201468 kb
Host smart-7a33e4b5-67f3-43aa-9511-f01534bf4925
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664826034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3664826034
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1421643475
Short name T399
Test name
Test status
Simulation time 209338464253 ps
CPU time 430.45 seconds
Started Jul 30 07:17:35 PM PDT 24
Finished Jul 30 07:24:45 PM PDT 24
Peak memory 201456 kb
Host smart-f2c0ac79-79a3-4df3-9df0-a1c85ab1b313
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421643475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1421643475
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.371212375
Short name T655
Test name
Test status
Simulation time 94060880279 ps
CPU time 335.03 seconds
Started Jul 30 07:17:42 PM PDT 24
Finished Jul 30 07:23:18 PM PDT 24
Peak memory 201860 kb
Host smart-9fd5df6e-f18f-4756-ad02-a6ee23716556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371212375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.371212375
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3173414359
Short name T574
Test name
Test status
Simulation time 41606546728 ps
CPU time 70.55 seconds
Started Jul 30 07:17:42 PM PDT 24
Finished Jul 30 07:18:53 PM PDT 24
Peak memory 201504 kb
Host smart-f53de4b7-3a48-438f-a6ad-6be3d008f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173414359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3173414359
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.188627010
Short name T475
Test name
Test status
Simulation time 2631967065 ps
CPU time 6.92 seconds
Started Jul 30 07:17:40 PM PDT 24
Finished Jul 30 07:17:47 PM PDT 24
Peak memory 201400 kb
Host smart-da2bb97f-c3a9-4972-a710-2926bef11aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188627010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.188627010
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2482357500
Short name T343
Test name
Test status
Simulation time 5694276141 ps
CPU time 13.88 seconds
Started Jul 30 07:17:28 PM PDT 24
Finished Jul 30 07:17:42 PM PDT 24
Peak memory 201332 kb
Host smart-a4532d4b-7ad5-4fbe-af61-89e94b0457f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482357500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2482357500
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1817610247
Short name T406
Test name
Test status
Simulation time 235452423427 ps
CPU time 554.93 seconds
Started Jul 30 07:17:46 PM PDT 24
Finished Jul 30 07:27:01 PM PDT 24
Peak memory 201388 kb
Host smart-f7de29ef-38d0-44d8-9ebf-934b9c27d520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817610247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1817610247
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2679833832
Short name T269
Test name
Test status
Simulation time 174331739599 ps
CPU time 211.82 seconds
Started Jul 30 07:17:48 PM PDT 24
Finished Jul 30 07:21:20 PM PDT 24
Peak memory 210124 kb
Host smart-e6c7032a-46b8-45e2-b3dc-cf150f6d066b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679833832 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2679833832
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2505831028
Short name T584
Test name
Test status
Simulation time 339063119 ps
CPU time 0.76 seconds
Started Jul 30 07:18:04 PM PDT 24
Finished Jul 30 07:18:05 PM PDT 24
Peak memory 201228 kb
Host smart-edc07049-706b-454a-b15a-80a4a4583908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505831028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2505831028
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.811519271
Short name T785
Test name
Test status
Simulation time 165833404819 ps
CPU time 31.51 seconds
Started Jul 30 07:17:52 PM PDT 24
Finished Jul 30 07:18:24 PM PDT 24
Peak memory 201428 kb
Host smart-3c53653b-80ab-4264-8ee2-be6f2d3e7019
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811519271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.811519271
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.870896828
Short name T428
Test name
Test status
Simulation time 488337942566 ps
CPU time 582.48 seconds
Started Jul 30 07:17:52 PM PDT 24
Finished Jul 30 07:27:35 PM PDT 24
Peak memory 201436 kb
Host smart-bf64ad25-17f0-4cb2-af0b-7b49e93cad57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=870896828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.870896828
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.926570208
Short name T730
Test name
Test status
Simulation time 494646643825 ps
CPU time 494.64 seconds
Started Jul 30 07:17:50 PM PDT 24
Finished Jul 30 07:26:04 PM PDT 24
Peak memory 201444 kb
Host smart-b46d8510-9143-4687-908d-251fdff9b00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926570208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.926570208
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1191299743
Short name T190
Test name
Test status
Simulation time 168648493958 ps
CPU time 95.22 seconds
Started Jul 30 07:17:50 PM PDT 24
Finished Jul 30 07:19:25 PM PDT 24
Peak memory 201448 kb
Host smart-1d0c8620-ae63-4c47-b768-2e49e27b9bc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191299743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1191299743
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2396363894
Short name T14
Test name
Test status
Simulation time 577322690757 ps
CPU time 657.2 seconds
Started Jul 30 07:17:53 PM PDT 24
Finished Jul 30 07:28:50 PM PDT 24
Peak memory 201476 kb
Host smart-8e093b8c-bc9f-4934-934c-091f3544cb50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396363894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2396363894
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3271793752
Short name T765
Test name
Test status
Simulation time 200936388457 ps
CPU time 464.76 seconds
Started Jul 30 07:17:52 PM PDT 24
Finished Jul 30 07:25:37 PM PDT 24
Peak memory 201352 kb
Host smart-3c6858b2-8eff-46ed-90b2-ee3800b0f487
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271793752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3271793752
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3741039812
Short name T452
Test name
Test status
Simulation time 77285620918 ps
CPU time 292.58 seconds
Started Jul 30 07:17:59 PM PDT 24
Finished Jul 30 07:22:52 PM PDT 24
Peak memory 201800 kb
Host smart-728a8202-29ad-4b66-9221-215cf8e2ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741039812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3741039812
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2777616953
Short name T390
Test name
Test status
Simulation time 38363529503 ps
CPU time 24.57 seconds
Started Jul 30 07:17:57 PM PDT 24
Finished Jul 30 07:18:22 PM PDT 24
Peak memory 201344 kb
Host smart-9583f92c-998f-48ed-96eb-8a9b64d5f518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777616953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2777616953
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.865795085
Short name T625
Test name
Test status
Simulation time 4368771744 ps
CPU time 2.98 seconds
Started Jul 30 07:17:56 PM PDT 24
Finished Jul 30 07:17:59 PM PDT 24
Peak memory 201316 kb
Host smart-0461ab5d-c10a-4498-82bf-0752461b1eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865795085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.865795085
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.322629562
Short name T569
Test name
Test status
Simulation time 6205084485 ps
CPU time 4.24 seconds
Started Jul 30 07:17:45 PM PDT 24
Finished Jul 30 07:17:50 PM PDT 24
Peak memory 201400 kb
Host smart-07e05acb-0e0d-4bc6-b896-56bb94c3e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322629562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.322629562
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2706995617
Short name T114
Test name
Test status
Simulation time 764039352924 ps
CPU time 229.89 seconds
Started Jul 30 07:18:01 PM PDT 24
Finished Jul 30 07:21:51 PM PDT 24
Peak memory 218204 kb
Host smart-3a1c83d0-0168-43fc-ac6a-1eaac53db838
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706995617 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2706995617
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.662308472
Short name T163
Test name
Test status
Simulation time 343020025 ps
CPU time 1.42 seconds
Started Jul 30 07:18:10 PM PDT 24
Finished Jul 30 07:18:11 PM PDT 24
Peak memory 201176 kb
Host smart-ff57ed81-75a9-4957-9cde-74d6967b6feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662308472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.662308472
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.962924732
Short name T301
Test name
Test status
Simulation time 496017116721 ps
CPU time 1199.03 seconds
Started Jul 30 07:18:06 PM PDT 24
Finished Jul 30 07:38:06 PM PDT 24
Peak memory 201492 kb
Host smart-7b7a757f-0557-4cdc-a096-8020369dd87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962924732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.962924732
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3561332030
Short name T421
Test name
Test status
Simulation time 490312829401 ps
CPU time 756.95 seconds
Started Jul 30 07:18:07 PM PDT 24
Finished Jul 30 07:30:44 PM PDT 24
Peak memory 201484 kb
Host smart-3df9f98a-e417-4f05-92ea-78bd3f061ef4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561332030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3561332030
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3658586401
Short name T619
Test name
Test status
Simulation time 161304541680 ps
CPU time 344.77 seconds
Started Jul 30 07:18:08 PM PDT 24
Finished Jul 30 07:23:53 PM PDT 24
Peak memory 201504 kb
Host smart-3ca95dff-6576-4fc4-8d8a-f05996e05a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658586401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3658586401
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1854997223
Short name T768
Test name
Test status
Simulation time 325276048429 ps
CPU time 173.74 seconds
Started Jul 30 07:18:04 PM PDT 24
Finished Jul 30 07:20:58 PM PDT 24
Peak memory 201432 kb
Host smart-f74e171d-17d5-4013-bd8a-965cca0d72dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854997223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1854997223
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3596608421
Short name T192
Test name
Test status
Simulation time 544901043247 ps
CPU time 309.65 seconds
Started Jul 30 07:18:06 PM PDT 24
Finished Jul 30 07:23:16 PM PDT 24
Peak memory 201440 kb
Host smart-f3eed277-9bef-4915-9dfa-afeec1a50f0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596608421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3596608421
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.870185046
Short name T753
Test name
Test status
Simulation time 191335774774 ps
CPU time 470.77 seconds
Started Jul 30 07:18:06 PM PDT 24
Finished Jul 30 07:25:56 PM PDT 24
Peak memory 201460 kb
Host smart-76ed5489-45f1-4588-87f9-c84ac452b14e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870185046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.870185046
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2852774758
Short name T752
Test name
Test status
Simulation time 100740093372 ps
CPU time 489.83 seconds
Started Jul 30 07:18:09 PM PDT 24
Finished Jul 30 07:26:19 PM PDT 24
Peak memory 201872 kb
Host smart-b0573a10-1907-4f2d-9354-6831310a41a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852774758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2852774758
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.4003390205
Short name T433
Test name
Test status
Simulation time 36363483391 ps
CPU time 86.7 seconds
Started Jul 30 07:18:07 PM PDT 24
Finished Jul 30 07:19:34 PM PDT 24
Peak memory 201344 kb
Host smart-700475f8-f70c-4a4c-b295-337a79eecbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003390205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.4003390205
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2126418651
Short name T687
Test name
Test status
Simulation time 2754995863 ps
CPU time 6.41 seconds
Started Jul 30 07:18:07 PM PDT 24
Finished Jul 30 07:18:13 PM PDT 24
Peak memory 201308 kb
Host smart-d5e39ef0-d728-4d87-a7ea-4c9117351ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126418651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2126418651
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.690155096
Short name T474
Test name
Test status
Simulation time 5675892394 ps
CPU time 3.48 seconds
Started Jul 30 07:18:04 PM PDT 24
Finished Jul 30 07:18:08 PM PDT 24
Peak memory 201364 kb
Host smart-032b94f8-e5cb-4fc7-8109-3689e19fae0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690155096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.690155096
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.268747896
Short name T378
Test name
Test status
Simulation time 11708866258 ps
CPU time 15.86 seconds
Started Jul 30 07:18:09 PM PDT 24
Finished Jul 30 07:18:25 PM PDT 24
Peak memory 201492 kb
Host smart-ba08a674-667b-4a11-83b6-ec52d408d9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268747896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
268747896
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.761939153
Short name T716
Test name
Test status
Simulation time 61119289186 ps
CPU time 129.56 seconds
Started Jul 30 07:18:07 PM PDT 24
Finished Jul 30 07:20:17 PM PDT 24
Peak memory 211180 kb
Host smart-11533a7f-3967-4c6d-a168-75a7f6b31747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761939153 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.761939153
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1271529162
Short name T495
Test name
Test status
Simulation time 323780770 ps
CPU time 0.79 seconds
Started Jul 30 07:18:20 PM PDT 24
Finished Jul 30 07:18:21 PM PDT 24
Peak memory 201240 kb
Host smart-f49f7b4d-7eab-4cbb-88f5-019e7050a0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271529162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1271529162
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.197539115
Short name T692
Test name
Test status
Simulation time 360094684914 ps
CPU time 735.82 seconds
Started Jul 30 07:18:21 PM PDT 24
Finished Jul 30 07:30:37 PM PDT 24
Peak memory 201444 kb
Host smart-9c0efbde-a817-461b-8df5-5c3a2a2fc909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197539115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.197539115
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.980896670
Short name T590
Test name
Test status
Simulation time 167793420260 ps
CPU time 96.16 seconds
Started Jul 30 07:18:14 PM PDT 24
Finished Jul 30 07:19:50 PM PDT 24
Peak memory 201456 kb
Host smart-8a932e1a-dad5-452b-a979-c3cae6572453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980896670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.980896670
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3263938008
Short name T540
Test name
Test status
Simulation time 489114322352 ps
CPU time 287.09 seconds
Started Jul 30 07:18:18 PM PDT 24
Finished Jul 30 07:23:05 PM PDT 24
Peak memory 201520 kb
Host smart-b471bb8e-f1ff-4034-93a4-d25591fc69b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263938008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3263938008
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3189629727
Short name T183
Test name
Test status
Simulation time 325934278027 ps
CPU time 194.89 seconds
Started Jul 30 07:18:15 PM PDT 24
Finished Jul 30 07:21:30 PM PDT 24
Peak memory 201568 kb
Host smart-48854217-6b47-4a12-b5e7-a8ce0b545706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189629727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3189629727
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2459820521
Short name T329
Test name
Test status
Simulation time 493812993128 ps
CPU time 315.95 seconds
Started Jul 30 07:18:14 PM PDT 24
Finished Jul 30 07:23:30 PM PDT 24
Peak memory 201484 kb
Host smart-8a8b69de-3de4-4f08-a1a8-df0b2f3c880d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459820521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2459820521
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4048987659
Short name T230
Test name
Test status
Simulation time 202012756677 ps
CPU time 374.19 seconds
Started Jul 30 07:18:18 PM PDT 24
Finished Jul 30 07:24:33 PM PDT 24
Peak memory 201480 kb
Host smart-77ce778f-522e-43d5-8cbb-61e805f58594
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048987659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4048987659
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1852828836
Short name T59
Test name
Test status
Simulation time 603938033909 ps
CPU time 1418.8 seconds
Started Jul 30 07:18:22 PM PDT 24
Finished Jul 30 07:42:01 PM PDT 24
Peak memory 201508 kb
Host smart-d7419bc6-8f99-4fd1-af38-b612d619a8cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852828836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1852828836
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.364790380
Short name T790
Test name
Test status
Simulation time 117426656685 ps
CPU time 512.45 seconds
Started Jul 30 07:18:21 PM PDT 24
Finished Jul 30 07:26:53 PM PDT 24
Peak memory 201888 kb
Host smart-e6388f8c-aff1-47b3-ba32-d12b96071a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364790380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.364790380
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.842126566
Short name T674
Test name
Test status
Simulation time 40300674411 ps
CPU time 25.46 seconds
Started Jul 30 07:18:20 PM PDT 24
Finished Jul 30 07:18:46 PM PDT 24
Peak memory 201300 kb
Host smart-3790b7cb-40e0-4ffe-8cab-c127f7ae60fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842126566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.842126566
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1987070280
Short name T476
Test name
Test status
Simulation time 4717224418 ps
CPU time 6.14 seconds
Started Jul 30 07:18:20 PM PDT 24
Finished Jul 30 07:18:26 PM PDT 24
Peak memory 201360 kb
Host smart-d0f51f5a-0139-4b82-bce1-bb0b71aaa60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987070280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1987070280
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3791006769
Short name T392
Test name
Test status
Simulation time 6056694484 ps
CPU time 13.45 seconds
Started Jul 30 07:18:12 PM PDT 24
Finished Jul 30 07:18:25 PM PDT 24
Peak memory 201352 kb
Host smart-254a10a0-deae-4aba-b9ec-b4889c82bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791006769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3791006769
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.686964348
Short name T60
Test name
Test status
Simulation time 98603412424 ps
CPU time 527.97 seconds
Started Jul 30 07:18:21 PM PDT 24
Finished Jul 30 07:27:09 PM PDT 24
Peak memory 201896 kb
Host smart-0e272a70-91a5-40fb-b87a-9e38ec2f174a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686964348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
686964348
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3176648596
Short name T780
Test name
Test status
Simulation time 79475122850 ps
CPU time 201.89 seconds
Started Jul 30 07:18:20 PM PDT 24
Finished Jul 30 07:21:42 PM PDT 24
Peak memory 218220 kb
Host smart-952bb71b-fbe6-4142-bfaa-f4f6e1b5428e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176648596 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3176648596
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3874530736
Short name T643
Test name
Test status
Simulation time 474430074 ps
CPU time 0.87 seconds
Started Jul 30 07:18:38 PM PDT 24
Finished Jul 30 07:18:39 PM PDT 24
Peak memory 201228 kb
Host smart-bf524a75-1c17-4d95-8c95-333b6e12d40f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874530736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3874530736
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1644475259
Short name T109
Test name
Test status
Simulation time 163204159429 ps
CPU time 99.6 seconds
Started Jul 30 07:18:31 PM PDT 24
Finished Jul 30 07:20:11 PM PDT 24
Peak memory 201488 kb
Host smart-a410075e-0e1c-41cf-b78a-b2df5c80c6d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644475259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1644475259
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3211608105
Short name T5
Test name
Test status
Simulation time 172669577090 ps
CPU time 65.5 seconds
Started Jul 30 07:18:31 PM PDT 24
Finished Jul 30 07:19:37 PM PDT 24
Peak memory 201496 kb
Host smart-aca5fa92-a7ed-4687-a935-0aad481d968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211608105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3211608105
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1395386091
Short name T578
Test name
Test status
Simulation time 490206683544 ps
CPU time 554.79 seconds
Started Jul 30 07:18:29 PM PDT 24
Finished Jul 30 07:27:44 PM PDT 24
Peak memory 201448 kb
Host smart-f4543f44-81fd-45ae-b2b2-3e31bc8e23d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395386091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1395386091
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1774678105
Short name T333
Test name
Test status
Simulation time 328876098362 ps
CPU time 782.59 seconds
Started Jul 30 07:18:30 PM PDT 24
Finished Jul 30 07:31:32 PM PDT 24
Peak memory 201432 kb
Host smart-5bd794d0-f3c3-4c1c-bfe9-1a66cfef3e14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774678105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1774678105
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3438324496
Short name T704
Test name
Test status
Simulation time 165165698474 ps
CPU time 102.79 seconds
Started Jul 30 07:18:28 PM PDT 24
Finished Jul 30 07:20:11 PM PDT 24
Peak memory 201428 kb
Host smart-3680d6b7-d4fb-4558-8f36-790e789e1c76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438324496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3438324496
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2731772083
Short name T156
Test name
Test status
Simulation time 557497343656 ps
CPU time 635.18 seconds
Started Jul 30 07:18:29 PM PDT 24
Finished Jul 30 07:29:05 PM PDT 24
Peak memory 201492 kb
Host smart-c173f041-4c82-43e5-94d4-21de5cb286a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731772083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2731772083
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2486884166
Short name T455
Test name
Test status
Simulation time 615269999733 ps
CPU time 1097.14 seconds
Started Jul 30 07:18:29 PM PDT 24
Finished Jul 30 07:36:47 PM PDT 24
Peak memory 201480 kb
Host smart-d0ad44f3-77f3-4032-9d7d-ba0fd59ee569
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486884166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2486884166
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.315741626
Short name T589
Test name
Test status
Simulation time 86022833434 ps
CPU time 278.11 seconds
Started Jul 30 07:18:32 PM PDT 24
Finished Jul 30 07:23:11 PM PDT 24
Peak memory 201828 kb
Host smart-b0946189-623d-4cf6-a351-0f0acd064a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315741626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.315741626
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3124746612
Short name T706
Test name
Test status
Simulation time 31905161638 ps
CPU time 34.85 seconds
Started Jul 30 07:18:32 PM PDT 24
Finished Jul 30 07:19:07 PM PDT 24
Peak memory 201372 kb
Host smart-706c83cd-76f6-4352-8aa9-1af873f5ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124746612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3124746612
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4053262091
Short name T667
Test name
Test status
Simulation time 3991159466 ps
CPU time 2.82 seconds
Started Jul 30 07:18:38 PM PDT 24
Finished Jul 30 07:18:41 PM PDT 24
Peak memory 201368 kb
Host smart-99c804cf-fac4-43f1-b9bd-f54bd90e7b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053262091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4053262091
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2541627218
Short name T375
Test name
Test status
Simulation time 5773549975 ps
CPU time 4.14 seconds
Started Jul 30 07:18:25 PM PDT 24
Finished Jul 30 07:18:29 PM PDT 24
Peak memory 201392 kb
Host smart-a80a38f5-d008-4533-bc14-e80d3c279dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541627218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2541627218
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.349112964
Short name T461
Test name
Test status
Simulation time 43891900178 ps
CPU time 28.94 seconds
Started Jul 30 07:18:34 PM PDT 24
Finished Jul 30 07:19:03 PM PDT 24
Peak memory 201340 kb
Host smart-b9796b35-b738-43a1-bb13-adb9853625b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349112964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
349112964
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2073794663
Short name T311
Test name
Test status
Simulation time 215546347705 ps
CPU time 555.46 seconds
Started Jul 30 07:18:31 PM PDT 24
Finished Jul 30 07:27:47 PM PDT 24
Peak memory 210184 kb
Host smart-2593bc9e-2543-4874-a0ff-8ee09ad3b48e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073794663 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2073794663
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1277894152
Short name T414
Test name
Test status
Simulation time 354068502 ps
CPU time 1.35 seconds
Started Jul 30 07:07:52 PM PDT 24
Finished Jul 30 07:07:54 PM PDT 24
Peak memory 201264 kb
Host smart-e474da7e-ab6c-4f8b-8603-d1da23b69bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277894152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1277894152
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.489990362
Short name T229
Test name
Test status
Simulation time 376991932296 ps
CPU time 219.38 seconds
Started Jul 30 07:07:38 PM PDT 24
Finished Jul 30 07:11:18 PM PDT 24
Peak memory 201352 kb
Host smart-74155fd4-6c81-415d-9dcf-b44f0ac416f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489990362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.489990362
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.177880220
Short name T153
Test name
Test status
Simulation time 492186713730 ps
CPU time 313.36 seconds
Started Jul 30 07:07:30 PM PDT 24
Finished Jul 30 07:12:43 PM PDT 24
Peak memory 201416 kb
Host smart-82fa270c-f297-4ef8-a357-39cb1c77a8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177880220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.177880220
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.163992421
Short name T598
Test name
Test status
Simulation time 325094167455 ps
CPU time 739.7 seconds
Started Jul 30 07:07:29 PM PDT 24
Finished Jul 30 07:19:49 PM PDT 24
Peak memory 201488 kb
Host smart-a5e27961-2172-4fea-89ff-542386c7804d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=163992421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.163992421
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2660812473
Short name T531
Test name
Test status
Simulation time 498146809512 ps
CPU time 1089.97 seconds
Started Jul 30 07:07:27 PM PDT 24
Finished Jul 30 07:25:37 PM PDT 24
Peak memory 201440 kb
Host smart-99cad08c-8cb3-481b-9b44-136e8703e813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660812473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2660812473
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.4123175026
Short name T542
Test name
Test status
Simulation time 162539463058 ps
CPU time 91.99 seconds
Started Jul 30 07:07:26 PM PDT 24
Finished Jul 30 07:08:59 PM PDT 24
Peak memory 201376 kb
Host smart-b58932b3-6ce7-4018-bbd5-112c034996f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123175026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.4123175026
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3688891284
Short name T791
Test name
Test status
Simulation time 535999581035 ps
CPU time 687.48 seconds
Started Jul 30 07:07:29 PM PDT 24
Finished Jul 30 07:18:57 PM PDT 24
Peak memory 201528 kb
Host smart-980d679e-d068-4738-9928-e483b63a4083
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688891284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3688891284
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.218799502
Short name T533
Test name
Test status
Simulation time 413961868209 ps
CPU time 879.37 seconds
Started Jul 30 07:07:33 PM PDT 24
Finished Jul 30 07:22:13 PM PDT 24
Peak memory 201472 kb
Host smart-3ea7d4aa-a10f-4ecc-b1e4-e7a262c785de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218799502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.218799502
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3069678344
Short name T657
Test name
Test status
Simulation time 141229054167 ps
CPU time 446.18 seconds
Started Jul 30 07:07:41 PM PDT 24
Finished Jul 30 07:15:07 PM PDT 24
Peak memory 201872 kb
Host smart-bdd05289-fc48-4f6c-8884-c28a4b218dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069678344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3069678344
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1705441002
Short name T793
Test name
Test status
Simulation time 40180525865 ps
CPU time 22.05 seconds
Started Jul 30 07:07:40 PM PDT 24
Finished Jul 30 07:08:02 PM PDT 24
Peak memory 201204 kb
Host smart-42768235-7daf-442a-9d6a-2b4e390d86f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705441002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1705441002
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.102043207
Short name T445
Test name
Test status
Simulation time 2847112649 ps
CPU time 7.76 seconds
Started Jul 30 07:07:36 PM PDT 24
Finished Jul 30 07:07:44 PM PDT 24
Peak memory 201304 kb
Host smart-6d5030f0-6391-46e4-8560-74fa54cf59d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102043207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.102043207
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3009610805
Short name T28
Test name
Test status
Simulation time 4335801776 ps
CPU time 10.27 seconds
Started Jul 30 07:07:54 PM PDT 24
Finished Jul 30 07:08:05 PM PDT 24
Peak memory 217060 kb
Host smart-8b7f519b-8321-4ece-a5e1-3cafc073b97b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009610805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3009610805
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2934317049
Short name T769
Test name
Test status
Simulation time 5706610590 ps
CPU time 7.47 seconds
Started Jul 30 07:07:23 PM PDT 24
Finished Jul 30 07:07:31 PM PDT 24
Peak memory 201364 kb
Host smart-8431c202-2892-4e2e-9d02-9ade5d7348d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934317049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2934317049
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2373336330
Short name T708
Test name
Test status
Simulation time 211542450886 ps
CPU time 498.66 seconds
Started Jul 30 07:07:40 PM PDT 24
Finished Jul 30 07:15:59 PM PDT 24
Peak memory 201432 kb
Host smart-48939e2e-7a41-4246-bff1-1a5653cef29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373336330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2373336330
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2139447991
Short name T313
Test name
Test status
Simulation time 594783001003 ps
CPU time 600.9 seconds
Started Jul 30 07:07:41 PM PDT 24
Finished Jul 30 07:17:42 PM PDT 24
Peak memory 210132 kb
Host smart-74264c5c-1763-43b3-8048-f13b25fba348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139447991 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2139447991
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.924316960
Short name T415
Test name
Test status
Simulation time 362583098 ps
CPU time 1.43 seconds
Started Jul 30 07:18:49 PM PDT 24
Finished Jul 30 07:18:50 PM PDT 24
Peak memory 201280 kb
Host smart-ccd43fe1-9e52-4dd7-a6bc-7ba9c21471ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924316960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.924316960
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.10237091
Short name T649
Test name
Test status
Simulation time 447543012151 ps
CPU time 1029.45 seconds
Started Jul 30 07:18:44 PM PDT 24
Finished Jul 30 07:35:54 PM PDT 24
Peak memory 201492 kb
Host smart-0c8d5a0a-7f60-47be-a84b-98accae4980e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10237091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.10237091
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1067220518
Short name T405
Test name
Test status
Simulation time 489114996901 ps
CPU time 307.24 seconds
Started Jul 30 07:18:43 PM PDT 24
Finished Jul 30 07:23:50 PM PDT 24
Peak memory 201452 kb
Host smart-c96e42b0-8939-4da3-977a-023e71f67b75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067220518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1067220518
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3207487970
Short name T250
Test name
Test status
Simulation time 334611052888 ps
CPU time 196.19 seconds
Started Jul 30 07:18:39 PM PDT 24
Finished Jul 30 07:21:55 PM PDT 24
Peak memory 201440 kb
Host smart-d04f273a-aa35-4b72-8d22-9a50653751d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207487970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3207487970
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2704530879
Short name T441
Test name
Test status
Simulation time 162470447597 ps
CPU time 97.04 seconds
Started Jul 30 07:18:43 PM PDT 24
Finished Jul 30 07:20:21 PM PDT 24
Peak memory 201452 kb
Host smart-672de900-95b4-40f6-8cd3-b82d990f363d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704530879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2704530879
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1661052395
Short name T669
Test name
Test status
Simulation time 372287218186 ps
CPU time 216.28 seconds
Started Jul 30 07:18:42 PM PDT 24
Finished Jul 30 07:22:18 PM PDT 24
Peak memory 201448 kb
Host smart-74d2fd8b-820e-4c43-bbf3-c28b40ea671e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661052395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1661052395
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.462116743
Short name T187
Test name
Test status
Simulation time 600252815771 ps
CPU time 1396.33 seconds
Started Jul 30 07:18:46 PM PDT 24
Finished Jul 30 07:42:03 PM PDT 24
Peak memory 201452 kb
Host smart-61efc63b-98de-44c3-b078-0664317db4ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462116743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.462116743
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.479946115
Short name T554
Test name
Test status
Simulation time 132208969222 ps
CPU time 688.99 seconds
Started Jul 30 07:18:49 PM PDT 24
Finished Jul 30 07:30:18 PM PDT 24
Peak memory 201768 kb
Host smart-7395ba78-5ba4-48e8-9814-39b61d049530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479946115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.479946115
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3759604123
Short name T502
Test name
Test status
Simulation time 29395283681 ps
CPU time 15.07 seconds
Started Jul 30 07:18:45 PM PDT 24
Finished Jul 30 07:19:00 PM PDT 24
Peak memory 201416 kb
Host smart-2fba4ab1-51fd-4106-85f1-dd60337fb4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759604123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3759604123
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3753966360
Short name T385
Test name
Test status
Simulation time 3934669120 ps
CPU time 5.34 seconds
Started Jul 30 07:18:47 PM PDT 24
Finished Jul 30 07:18:52 PM PDT 24
Peak memory 201404 kb
Host smart-b95b4b00-7e54-4010-b90f-fe80ada7cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753966360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3753966360
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.620628035
Short name T559
Test name
Test status
Simulation time 5762787140 ps
CPU time 14.79 seconds
Started Jul 30 07:18:42 PM PDT 24
Finished Jul 30 07:18:57 PM PDT 24
Peak memory 201372 kb
Host smart-ee0eb022-4ded-4b38-8899-e0483f1cdebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620628035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.620628035
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1569555967
Short name T290
Test name
Test status
Simulation time 340459737059 ps
CPU time 202.78 seconds
Started Jul 30 07:18:50 PM PDT 24
Finished Jul 30 07:22:13 PM PDT 24
Peak memory 201432 kb
Host smart-6b7089ac-525b-4d59-9249-8baee476f968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569555967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1569555967
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1856552441
Short name T21
Test name
Test status
Simulation time 86646185396 ps
CPU time 99 seconds
Started Jul 30 07:18:51 PM PDT 24
Finished Jul 30 07:20:30 PM PDT 24
Peak memory 210116 kb
Host smart-697fa263-f409-4ae0-ab37-23e80ebe13f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856552441 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1856552441
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.916877096
Short name T553
Test name
Test status
Simulation time 550047306 ps
CPU time 0.9 seconds
Started Jul 30 07:18:58 PM PDT 24
Finished Jul 30 07:19:00 PM PDT 24
Peak memory 201288 kb
Host smart-1255e36e-861b-4cde-811b-1526afde9ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916877096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.916877096
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1520736017
Short name T261
Test name
Test status
Simulation time 160608847526 ps
CPU time 340.89 seconds
Started Jul 30 07:19:00 PM PDT 24
Finished Jul 30 07:24:41 PM PDT 24
Peak memory 201504 kb
Host smart-b7e8faee-9918-4995-b045-1087b29f55fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520736017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1520736017
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2594232911
Short name T151
Test name
Test status
Simulation time 330717313473 ps
CPU time 190.25 seconds
Started Jul 30 07:18:57 PM PDT 24
Finished Jul 30 07:22:07 PM PDT 24
Peak memory 201428 kb
Host smart-64fb79fd-41dd-460e-b78b-f6b8c51abda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594232911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2594232911
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2618068273
Short name T700
Test name
Test status
Simulation time 319539747423 ps
CPU time 211.07 seconds
Started Jul 30 07:18:53 PM PDT 24
Finished Jul 30 07:22:25 PM PDT 24
Peak memory 201492 kb
Host smart-b0bbe636-2d83-4e76-84b5-58b10876452d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618068273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2618068273
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.128068493
Short name T725
Test name
Test status
Simulation time 480436943941 ps
CPU time 259.21 seconds
Started Jul 30 07:18:49 PM PDT 24
Finished Jul 30 07:23:08 PM PDT 24
Peak memory 201444 kb
Host smart-7025b10a-a142-47a4-a593-22bfd8c81df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128068493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.128068493
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1654325348
Short name T434
Test name
Test status
Simulation time 163096560359 ps
CPU time 187.93 seconds
Started Jul 30 07:18:53 PM PDT 24
Finished Jul 30 07:22:01 PM PDT 24
Peak memory 201460 kb
Host smart-27f58445-01c4-4d42-b1f5-74c8cddbec49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654325348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1654325348
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1374945374
Short name T33
Test name
Test status
Simulation time 342909155200 ps
CPU time 101.45 seconds
Started Jul 30 07:18:52 PM PDT 24
Finished Jul 30 07:20:34 PM PDT 24
Peak memory 201452 kb
Host smart-22a491a2-e5e8-4d8c-8ac1-a40b1497f6a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374945374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1374945374
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1071307587
Short name T566
Test name
Test status
Simulation time 203310383006 ps
CPU time 107.87 seconds
Started Jul 30 07:18:52 PM PDT 24
Finished Jul 30 07:20:40 PM PDT 24
Peak memory 201404 kb
Host smart-65c761c1-d66b-4f81-b6c8-d9ac2b083de1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071307587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1071307587
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1114726190
Short name T211
Test name
Test status
Simulation time 142215626570 ps
CPU time 475.21 seconds
Started Jul 30 07:19:00 PM PDT 24
Finished Jul 30 07:26:55 PM PDT 24
Peak memory 201836 kb
Host smart-d077e8c2-995a-4974-8dfe-46d56a437208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114726190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1114726190
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1231369940
Short name T723
Test name
Test status
Simulation time 25297574999 ps
CPU time 29.47 seconds
Started Jul 30 07:18:56 PM PDT 24
Finished Jul 30 07:19:26 PM PDT 24
Peak memory 201304 kb
Host smart-979e1a34-b432-4c25-83d9-f082310fb08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231369940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1231369940
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3841659708
Short name T116
Test name
Test status
Simulation time 4730572696 ps
CPU time 6.34 seconds
Started Jul 30 07:19:00 PM PDT 24
Finished Jul 30 07:19:06 PM PDT 24
Peak memory 201364 kb
Host smart-75e99e70-04f1-40a8-a496-697f16ed31d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841659708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3841659708
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2672303603
Short name T27
Test name
Test status
Simulation time 5780629624 ps
CPU time 2.55 seconds
Started Jul 30 07:18:49 PM PDT 24
Finished Jul 30 07:18:52 PM PDT 24
Peak memory 201348 kb
Host smart-95aba9c4-bbc8-4ddc-b966-774d4d33c7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672303603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2672303603
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.4083128751
Short name T167
Test name
Test status
Simulation time 515809219276 ps
CPU time 1108.92 seconds
Started Jul 30 07:18:56 PM PDT 24
Finished Jul 30 07:37:25 PM PDT 24
Peak memory 201412 kb
Host smart-2b228255-73a8-42cf-a562-6383959187ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083128751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.4083128751
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2373322478
Short name T17
Test name
Test status
Simulation time 273186424072 ps
CPU time 129.36 seconds
Started Jul 30 07:19:00 PM PDT 24
Finished Jul 30 07:21:10 PM PDT 24
Peak memory 209836 kb
Host smart-dd11cb25-9102-463e-a4b4-7c0490b3c823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373322478 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2373322478
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3340566623
Short name T397
Test name
Test status
Simulation time 502625358 ps
CPU time 1.74 seconds
Started Jul 30 07:19:14 PM PDT 24
Finished Jul 30 07:19:16 PM PDT 24
Peak memory 201296 kb
Host smart-55a400b0-e4dc-45e1-aecc-90c63a871f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340566623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3340566623
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1274301710
Short name T664
Test name
Test status
Simulation time 166530031430 ps
CPU time 102.36 seconds
Started Jul 30 07:19:03 PM PDT 24
Finished Jul 30 07:20:46 PM PDT 24
Peak memory 201440 kb
Host smart-27d3dc78-5de5-41c6-bd4d-3674873949c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274301710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1274301710
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2484141370
Short name T572
Test name
Test status
Simulation time 165442672799 ps
CPU time 176.22 seconds
Started Jul 30 07:19:01 PM PDT 24
Finished Jul 30 07:21:57 PM PDT 24
Peak memory 201464 kb
Host smart-8893cb63-a9fe-4bc7-a05e-be1c413baee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484141370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2484141370
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1803899748
Short name T731
Test name
Test status
Simulation time 485550256542 ps
CPU time 295.55 seconds
Started Jul 30 07:19:00 PM PDT 24
Finished Jul 30 07:23:56 PM PDT 24
Peak memory 201396 kb
Host smart-5fc30cc0-6447-4d3b-848b-d437bdee50b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803899748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1803899748
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3936148105
Short name T751
Test name
Test status
Simulation time 159426641749 ps
CPU time 88.72 seconds
Started Jul 30 07:18:59 PM PDT 24
Finished Jul 30 07:20:28 PM PDT 24
Peak memory 201408 kb
Host smart-df3aaa9f-27f8-4bbc-b354-0e525d877687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936148105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3936148105
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2928916117
Short name T550
Test name
Test status
Simulation time 332548525857 ps
CPU time 175.17 seconds
Started Jul 30 07:18:59 PM PDT 24
Finished Jul 30 07:21:55 PM PDT 24
Peak memory 201412 kb
Host smart-5d134c28-6ac1-4542-be84-0b38453f58ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928916117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2928916117
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.410147140
Short name T424
Test name
Test status
Simulation time 351239766289 ps
CPU time 224.32 seconds
Started Jul 30 07:19:01 PM PDT 24
Finished Jul 30 07:22:46 PM PDT 24
Peak memory 201436 kb
Host smart-a601dd7a-a254-44f7-bcfe-8ee8d268203d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410147140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.410147140
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3344224649
Short name T523
Test name
Test status
Simulation time 409692560405 ps
CPU time 959.67 seconds
Started Jul 30 07:19:02 PM PDT 24
Finished Jul 30 07:35:02 PM PDT 24
Peak memory 201408 kb
Host smart-c4c51b82-fb9c-478d-a4b9-8f8e2708473a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344224649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3344224649
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3028104945
Short name T62
Test name
Test status
Simulation time 81524785981 ps
CPU time 411.21 seconds
Started Jul 30 07:19:12 PM PDT 24
Finished Jul 30 07:26:03 PM PDT 24
Peak memory 201876 kb
Host smart-ee677af9-7a79-439f-af31-39c47189bb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028104945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3028104945
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3691236013
Short name T456
Test name
Test status
Simulation time 26233527572 ps
CPU time 28.62 seconds
Started Jul 30 07:19:12 PM PDT 24
Finished Jul 30 07:19:40 PM PDT 24
Peak memory 201352 kb
Host smart-d4aee7d3-d345-4945-b320-a189fd593f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691236013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3691236013
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1459791466
Short name T466
Test name
Test status
Simulation time 3083283051 ps
CPU time 4.59 seconds
Started Jul 30 07:19:07 PM PDT 24
Finished Jul 30 07:19:11 PM PDT 24
Peak memory 201364 kb
Host smart-4f414920-7b1d-4e07-a89f-8e9ff3b8228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459791466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1459791466
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1067777635
Short name T4
Test name
Test status
Simulation time 5998565977 ps
CPU time 1.77 seconds
Started Jul 30 07:19:00 PM PDT 24
Finished Jul 30 07:19:02 PM PDT 24
Peak memory 201332 kb
Host smart-d923a5e4-8c68-432f-8767-29d8f4243cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067777635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1067777635
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4032401240
Short name T612
Test name
Test status
Simulation time 459304517 ps
CPU time 0.73 seconds
Started Jul 30 07:19:26 PM PDT 24
Finished Jul 30 07:19:27 PM PDT 24
Peak memory 201244 kb
Host smart-f6460bab-3437-4b87-bb44-19ea739e4599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032401240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4032401240
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3201416099
Short name T662
Test name
Test status
Simulation time 329674995741 ps
CPU time 190.93 seconds
Started Jul 30 07:19:21 PM PDT 24
Finished Jul 30 07:22:32 PM PDT 24
Peak memory 201440 kb
Host smart-7d2acac7-583b-4be0-9de7-f71b86e3e18c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201416099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3201416099
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3211278285
Short name T246
Test name
Test status
Simulation time 553571523379 ps
CPU time 327.06 seconds
Started Jul 30 07:19:22 PM PDT 24
Finished Jul 30 07:24:49 PM PDT 24
Peak memory 201440 kb
Host smart-585053d5-baef-46d0-88e0-9a7692763a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211278285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3211278285
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.725653589
Short name T288
Test name
Test status
Simulation time 164557765771 ps
CPU time 24.43 seconds
Started Jul 30 07:19:20 PM PDT 24
Finished Jul 30 07:19:44 PM PDT 24
Peak memory 201512 kb
Host smart-32186ca7-5f0d-4f81-ba06-527ee824bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725653589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.725653589
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1871368159
Short name T571
Test name
Test status
Simulation time 163928617593 ps
CPU time 96.71 seconds
Started Jul 30 07:19:18 PM PDT 24
Finished Jul 30 07:20:55 PM PDT 24
Peak memory 201492 kb
Host smart-d3974f8e-fad5-4309-8a7c-068a6394d12c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871368159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1871368159
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2026345776
Short name T307
Test name
Test status
Simulation time 159521498855 ps
CPU time 96.37 seconds
Started Jul 30 07:19:18 PM PDT 24
Finished Jul 30 07:20:55 PM PDT 24
Peak memory 201432 kb
Host smart-6c078340-ab22-4c72-8b75-60ae88b24488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026345776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2026345776
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2708019909
Short name T368
Test name
Test status
Simulation time 162841075504 ps
CPU time 183.35 seconds
Started Jul 30 07:19:18 PM PDT 24
Finished Jul 30 07:22:22 PM PDT 24
Peak memory 201456 kb
Host smart-7cfdfafc-7eeb-4c5c-82f9-a50c37b02cc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708019909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2708019909
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1628369935
Short name T178
Test name
Test status
Simulation time 341892289853 ps
CPU time 71.57 seconds
Started Jul 30 07:19:17 PM PDT 24
Finished Jul 30 07:20:29 PM PDT 24
Peak memory 201476 kb
Host smart-9004aad6-d9e0-4e6d-bc10-cb6e0d8aafdf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628369935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1628369935
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.116646168
Short name T587
Test name
Test status
Simulation time 612725751273 ps
CPU time 321.33 seconds
Started Jul 30 07:19:22 PM PDT 24
Finished Jul 30 07:24:43 PM PDT 24
Peak memory 201436 kb
Host smart-9868c615-f5ce-4666-8696-78ce79eae3bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116646168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.116646168
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1887611939
Short name T668
Test name
Test status
Simulation time 113991620774 ps
CPU time 614.37 seconds
Started Jul 30 07:19:22 PM PDT 24
Finished Jul 30 07:29:37 PM PDT 24
Peak memory 201820 kb
Host smart-0c45da8c-bc32-47fb-9dc5-2d9c325bfe6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887611939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1887611939
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.468425909
Short name T701
Test name
Test status
Simulation time 23544765917 ps
CPU time 56.54 seconds
Started Jul 30 07:19:23 PM PDT 24
Finished Jul 30 07:20:20 PM PDT 24
Peak memory 201380 kb
Host smart-ae0049f1-5ecb-4c1c-b721-61043a0cf241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468425909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.468425909
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.468029306
Short name T488
Test name
Test status
Simulation time 3727366709 ps
CPU time 10.09 seconds
Started Jul 30 07:19:21 PM PDT 24
Finished Jul 30 07:19:31 PM PDT 24
Peak memory 201336 kb
Host smart-2451907e-6b4c-4970-9207-b232a8ec0ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468029306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.468029306
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2076894859
Short name T379
Test name
Test status
Simulation time 5861684435 ps
CPU time 14.74 seconds
Started Jul 30 07:19:14 PM PDT 24
Finished Jul 30 07:19:29 PM PDT 24
Peak memory 201364 kb
Host smart-b6459b0e-b9f9-4d7c-ab58-11280a3345f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076894859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2076894859
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2291817343
Short name T478
Test name
Test status
Simulation time 498255014360 ps
CPU time 294.13 seconds
Started Jul 30 07:19:26 PM PDT 24
Finished Jul 30 07:24:20 PM PDT 24
Peak memory 201416 kb
Host smart-fb6c8c3c-db7b-42f4-a04d-88090728d323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291817343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2291817343
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.576225631
Short name T480
Test name
Test status
Simulation time 403435279 ps
CPU time 1.17 seconds
Started Jul 30 07:19:38 PM PDT 24
Finished Jul 30 07:19:39 PM PDT 24
Peak memory 201240 kb
Host smart-cad7731c-600d-46c9-a49e-13c6889bd55b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576225631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.576225631
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.188522175
Short name T528
Test name
Test status
Simulation time 290796530894 ps
CPU time 80.03 seconds
Started Jul 30 07:19:31 PM PDT 24
Finished Jul 30 07:20:51 PM PDT 24
Peak memory 201504 kb
Host smart-9dddf783-71a9-4c7e-9428-cb0a6dd9cef9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188522175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.188522175
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2716838791
Short name T608
Test name
Test status
Simulation time 323387946816 ps
CPU time 380.18 seconds
Started Jul 30 07:19:30 PM PDT 24
Finished Jul 30 07:25:50 PM PDT 24
Peak memory 201480 kb
Host smart-b99e1492-83ac-4b74-91cc-58695a07880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716838791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2716838791
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1434544869
Short name T386
Test name
Test status
Simulation time 329307942266 ps
CPU time 742.06 seconds
Started Jul 30 07:19:29 PM PDT 24
Finished Jul 30 07:31:51 PM PDT 24
Peak memory 201456 kb
Host smart-1aa05ad9-7afd-45bb-8d44-139eebbc3d52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434544869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1434544869
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.360694037
Short name T714
Test name
Test status
Simulation time 324668430617 ps
CPU time 742.2 seconds
Started Jul 30 07:19:25 PM PDT 24
Finished Jul 30 07:31:47 PM PDT 24
Peak memory 201440 kb
Host smart-26a70751-1405-45d5-8dd1-265e64ca4ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360694037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.360694037
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2152860063
Short name T611
Test name
Test status
Simulation time 496254973896 ps
CPU time 428.03 seconds
Started Jul 30 07:19:25 PM PDT 24
Finished Jul 30 07:26:33 PM PDT 24
Peak memory 201420 kb
Host smart-ec301227-672f-40a4-a48f-ae243f3c512b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152860063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2152860063
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1475513878
Short name T241
Test name
Test status
Simulation time 539212034910 ps
CPU time 621.95 seconds
Started Jul 30 07:19:30 PM PDT 24
Finished Jul 30 07:29:52 PM PDT 24
Peak memory 201596 kb
Host smart-3e56bb8b-7dac-487b-be82-f83ec7e4ad4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475513878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1475513878
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.7036163
Short name T713
Test name
Test status
Simulation time 69212400910 ps
CPU time 308.47 seconds
Started Jul 30 07:19:33 PM PDT 24
Finished Jul 30 07:24:41 PM PDT 24
Peak memory 201936 kb
Host smart-b7fb21ec-97b8-4f34-a377-358972252e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7036163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.7036163
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1176914169
Short name T613
Test name
Test status
Simulation time 37086961389 ps
CPU time 23.43 seconds
Started Jul 30 07:19:33 PM PDT 24
Finished Jul 30 07:19:56 PM PDT 24
Peak memory 201396 kb
Host smart-396c8101-c2a0-44ac-9be0-c03667bb6f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176914169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1176914169
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2262585690
Short name T427
Test name
Test status
Simulation time 3370326186 ps
CPU time 4.46 seconds
Started Jul 30 07:19:35 PM PDT 24
Finished Jul 30 07:19:40 PM PDT 24
Peak memory 201412 kb
Host smart-b4bed983-826e-4df8-8bec-62e5dcf687f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262585690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2262585690
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.114103148
Short name T543
Test name
Test status
Simulation time 5743313038 ps
CPU time 8.76 seconds
Started Jul 30 07:19:28 PM PDT 24
Finished Jul 30 07:19:37 PM PDT 24
Peak memory 201512 kb
Host smart-9be0ff31-d324-4ea6-be18-b72f1a5e87d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114103148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.114103148
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.971147539
Short name T36
Test name
Test status
Simulation time 79761494095 ps
CPU time 104.52 seconds
Started Jul 30 07:19:37 PM PDT 24
Finished Jul 30 07:21:22 PM PDT 24
Peak memory 209848 kb
Host smart-f018b614-71bf-420c-bcf7-8c9fe1e5b38e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971147539 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.971147539
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3100772815
Short name T344
Test name
Test status
Simulation time 396975677 ps
CPU time 0.67 seconds
Started Jul 30 07:20:07 PM PDT 24
Finished Jul 30 07:20:08 PM PDT 24
Peak memory 201184 kb
Host smart-b9d65795-7ff3-4de5-b62e-e9ddbf79331d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100772815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3100772815
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2798595673
Short name T430
Test name
Test status
Simulation time 356363980315 ps
CPU time 416.15 seconds
Started Jul 30 07:19:49 PM PDT 24
Finished Jul 30 07:26:45 PM PDT 24
Peak memory 201380 kb
Host smart-684ead89-7035-4b33-a5bc-c5cb982254f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798595673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2798595673
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.4028202343
Short name T161
Test name
Test status
Simulation time 483364158729 ps
CPU time 1105.12 seconds
Started Jul 30 07:19:40 PM PDT 24
Finished Jul 30 07:38:05 PM PDT 24
Peak memory 201512 kb
Host smart-7bdfda87-8cbb-474e-aada-83e5851519c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028202343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4028202343
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1514133811
Short name T449
Test name
Test status
Simulation time 166303282576 ps
CPU time 372.13 seconds
Started Jul 30 07:19:41 PM PDT 24
Finished Jul 30 07:25:53 PM PDT 24
Peak memory 201476 kb
Host smart-ab42b8f4-7716-4b67-91a7-864b485a062b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514133811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1514133811
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3224087743
Short name T450
Test name
Test status
Simulation time 332843610411 ps
CPU time 683.26 seconds
Started Jul 30 07:19:38 PM PDT 24
Finished Jul 30 07:31:01 PM PDT 24
Peak memory 201500 kb
Host smart-32e3ffb0-b616-4730-9f65-c185e8566d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224087743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3224087743
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2263958619
Short name T462
Test name
Test status
Simulation time 330136075924 ps
CPU time 195.35 seconds
Started Jul 30 07:19:38 PM PDT 24
Finished Jul 30 07:22:54 PM PDT 24
Peak memory 201284 kb
Host smart-461c7662-189e-4038-901a-3db5bdb4a82a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263958619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2263958619
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3142224348
Short name T685
Test name
Test status
Simulation time 519571194694 ps
CPU time 280.02 seconds
Started Jul 30 07:19:41 PM PDT 24
Finished Jul 30 07:24:21 PM PDT 24
Peak memory 201480 kb
Host smart-170bc520-be11-48e2-8dec-6c8729f53ed8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142224348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3142224348
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4149301751
Short name T123
Test name
Test status
Simulation time 611430942978 ps
CPU time 1157.12 seconds
Started Jul 30 07:19:43 PM PDT 24
Finished Jul 30 07:39:00 PM PDT 24
Peak memory 201456 kb
Host smart-694c5250-86ac-4d18-b676-4be96e363833
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149301751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4149301751
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4073210292
Short name T684
Test name
Test status
Simulation time 120069705254 ps
CPU time 571.34 seconds
Started Jul 30 07:19:49 PM PDT 24
Finished Jul 30 07:29:20 PM PDT 24
Peak memory 201836 kb
Host smart-2d9a8d24-d27f-459e-8ba8-c856e0c5b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073210292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4073210292
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2596797783
Short name T30
Test name
Test status
Simulation time 26450881865 ps
CPU time 15.75 seconds
Started Jul 30 07:19:50 PM PDT 24
Finished Jul 30 07:20:05 PM PDT 24
Peak memory 201508 kb
Host smart-0c4c177a-aa9c-4e6c-896b-b5be5c1db275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596797783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2596797783
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3085148981
Short name T666
Test name
Test status
Simulation time 4565123132 ps
CPU time 3.12 seconds
Started Jul 30 07:19:49 PM PDT 24
Finished Jul 30 07:19:52 PM PDT 24
Peak memory 201388 kb
Host smart-b8ce0863-4841-435f-9418-623e9615550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085148981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3085148981
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3144303470
Short name T381
Test name
Test status
Simulation time 5573569284 ps
CPU time 12.87 seconds
Started Jul 30 07:19:39 PM PDT 24
Finished Jul 30 07:19:51 PM PDT 24
Peak memory 201192 kb
Host smart-69f9d7e5-ef0b-476b-b3e4-8208535ccd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144303470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3144303470
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3640300302
Short name T256
Test name
Test status
Simulation time 429005678352 ps
CPU time 615.43 seconds
Started Jul 30 07:20:06 PM PDT 24
Finished Jul 30 07:30:22 PM PDT 24
Peak memory 210028 kb
Host smart-3a301311-1013-4e8c-ab17-7adcaa648ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640300302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3640300302
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3575419388
Short name T42
Test name
Test status
Simulation time 56559180133 ps
CPU time 30.7 seconds
Started Jul 30 07:19:53 PM PDT 24
Finished Jul 30 07:20:23 PM PDT 24
Peak memory 210792 kb
Host smart-36a058ff-5f28-4083-a083-32aac4e6a7d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575419388 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3575419388
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2504070437
Short name T120
Test name
Test status
Simulation time 366984066 ps
CPU time 0.82 seconds
Started Jul 30 07:20:14 PM PDT 24
Finished Jul 30 07:20:15 PM PDT 24
Peak memory 201240 kb
Host smart-4a3448bc-b082-4dfe-83e8-0d12cec34645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504070437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2504070437
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.567190321
Short name T635
Test name
Test status
Simulation time 173716444594 ps
CPU time 101.06 seconds
Started Jul 30 07:20:06 PM PDT 24
Finished Jul 30 07:21:48 PM PDT 24
Peak memory 201428 kb
Host smart-b4926ffb-8f57-4f40-99a6-4e4bebcc5c02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567190321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.567190321
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3668741859
Short name T497
Test name
Test status
Simulation time 162860059895 ps
CPU time 355.82 seconds
Started Jul 30 07:20:08 PM PDT 24
Finished Jul 30 07:26:04 PM PDT 24
Peak memory 201428 kb
Host smart-fb0a59dc-1df2-4403-a935-33a58d8b3604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668741859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3668741859
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1410431148
Short name T626
Test name
Test status
Simulation time 485677442908 ps
CPU time 1097.9 seconds
Started Jul 30 07:20:06 PM PDT 24
Finished Jul 30 07:38:24 PM PDT 24
Peak memory 201368 kb
Host smart-19f4c1c2-5e95-4db8-848e-ab473b3aa48f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410431148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1410431148
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2514720311
Short name T1
Test name
Test status
Simulation time 325951804947 ps
CPU time 177.81 seconds
Started Jul 30 07:20:05 PM PDT 24
Finished Jul 30 07:23:03 PM PDT 24
Peak memory 201508 kb
Host smart-693c441c-520d-4f19-83e4-769619e18fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514720311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2514720311
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2667962868
Short name T596
Test name
Test status
Simulation time 489105186723 ps
CPU time 263.29 seconds
Started Jul 30 07:20:05 PM PDT 24
Finished Jul 30 07:24:29 PM PDT 24
Peak memory 201396 kb
Host smart-e6e9bcdc-9a77-4309-88db-4a9834e6dae8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667962868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2667962868
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1418122251
Short name T760
Test name
Test status
Simulation time 195482045776 ps
CPU time 373.4 seconds
Started Jul 30 07:20:06 PM PDT 24
Finished Jul 30 07:26:20 PM PDT 24
Peak memory 201420 kb
Host smart-6c00ccdb-728a-4272-a2b9-295d4fd894e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418122251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1418122251
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.576310386
Short name T51
Test name
Test status
Simulation time 204325780807 ps
CPU time 459.34 seconds
Started Jul 30 07:20:06 PM PDT 24
Finished Jul 30 07:27:45 PM PDT 24
Peak memory 201444 kb
Host smart-85a3e1c3-dc3b-4c20-815f-e8cf85889c35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576310386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.576310386
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.80058039
Short name T511
Test name
Test status
Simulation time 74613615145 ps
CPU time 386.24 seconds
Started Jul 30 07:20:12 PM PDT 24
Finished Jul 30 07:26:38 PM PDT 24
Peak memory 201884 kb
Host smart-a6154e8c-bd4d-4110-aaa0-1e306325a7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80058039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.80058039
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1334669762
Short name T443
Test name
Test status
Simulation time 48224177366 ps
CPU time 11.01 seconds
Started Jul 30 07:20:10 PM PDT 24
Finished Jul 30 07:20:21 PM PDT 24
Peak memory 201364 kb
Host smart-5fc1644f-ef18-4f1f-9d4d-31e4fdabcebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334669762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1334669762
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1206564628
Short name T629
Test name
Test status
Simulation time 3281509344 ps
CPU time 8.97 seconds
Started Jul 30 07:20:06 PM PDT 24
Finished Jul 30 07:20:15 PM PDT 24
Peak memory 201340 kb
Host smart-d83ae828-ad30-495b-a93c-be5d147aa27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206564628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1206564628
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.240298830
Short name T516
Test name
Test status
Simulation time 5721549253 ps
CPU time 14.76 seconds
Started Jul 30 07:20:06 PM PDT 24
Finished Jul 30 07:20:20 PM PDT 24
Peak memory 201340 kb
Host smart-d733da03-748e-48fa-a358-7cac9d0c9a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240298830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.240298830
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2041536233
Short name T650
Test name
Test status
Simulation time 181297361902 ps
CPU time 470.9 seconds
Started Jul 30 07:20:11 PM PDT 24
Finished Jul 30 07:28:02 PM PDT 24
Peak memory 210020 kb
Host smart-b8630722-c31e-41d3-902e-da2ecd8f95a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041536233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2041536233
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3487764652
Short name T641
Test name
Test status
Simulation time 31926051133 ps
CPU time 97.75 seconds
Started Jul 30 07:20:11 PM PDT 24
Finished Jul 30 07:21:49 PM PDT 24
Peak memory 217932 kb
Host smart-4c59058d-d308-437e-8b6d-7e2504199c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487764652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3487764652
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.617462369
Short name T376
Test name
Test status
Simulation time 525587730 ps
CPU time 1.87 seconds
Started Jul 30 07:20:29 PM PDT 24
Finished Jul 30 07:20:31 PM PDT 24
Peak memory 201236 kb
Host smart-10afcfc3-0736-4ede-944c-b4624a99405a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617462369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.617462369
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.568166308
Short name T270
Test name
Test status
Simulation time 370199440283 ps
CPU time 223.82 seconds
Started Jul 30 07:20:20 PM PDT 24
Finished Jul 30 07:24:04 PM PDT 24
Peak memory 201520 kb
Host smart-ac62246d-360a-4488-a80c-930785f0093f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568166308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.568166308
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3435582534
Short name T218
Test name
Test status
Simulation time 172689043804 ps
CPU time 411.63 seconds
Started Jul 30 07:20:25 PM PDT 24
Finished Jul 30 07:27:17 PM PDT 24
Peak memory 201440 kb
Host smart-443c5d41-8a6f-4f8c-af62-971673563989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435582534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3435582534
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2911346443
Short name T308
Test name
Test status
Simulation time 158090268881 ps
CPU time 339.39 seconds
Started Jul 30 07:20:19 PM PDT 24
Finished Jul 30 07:25:58 PM PDT 24
Peak memory 201496 kb
Host smart-1b55516f-3b4d-4769-adab-4882834bb97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911346443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2911346443
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3038262471
Short name T693
Test name
Test status
Simulation time 495705585366 ps
CPU time 1089.37 seconds
Started Jul 30 07:20:22 PM PDT 24
Finished Jul 30 07:38:32 PM PDT 24
Peak memory 201500 kb
Host smart-26abc58b-7c60-4a37-8563-6ebe011ba2a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038262471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3038262471
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3216973390
Short name T602
Test name
Test status
Simulation time 326827205273 ps
CPU time 157.29 seconds
Started Jul 30 07:20:15 PM PDT 24
Finished Jul 30 07:22:52 PM PDT 24
Peak memory 201500 kb
Host smart-3bb6a548-eecb-49ba-b2d6-a71b096d874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216973390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3216973390
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2538219215
Short name T618
Test name
Test status
Simulation time 165748702231 ps
CPU time 93.42 seconds
Started Jul 30 07:20:18 PM PDT 24
Finished Jul 30 07:21:52 PM PDT 24
Peak memory 201432 kb
Host smart-ce27b862-0d44-4007-b751-82c93a0d6ec1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538219215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2538219215
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.604937646
Short name T244
Test name
Test status
Simulation time 458262641550 ps
CPU time 959.23 seconds
Started Jul 30 07:20:21 PM PDT 24
Finished Jul 30 07:36:20 PM PDT 24
Peak memory 201428 kb
Host smart-1b1d179f-6e8f-4f22-8cee-6bc6ad9f819b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604937646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.604937646
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3298434549
Short name T582
Test name
Test status
Simulation time 407398546769 ps
CPU time 231.73 seconds
Started Jul 30 07:20:22 PM PDT 24
Finished Jul 30 07:24:14 PM PDT 24
Peak memory 201600 kb
Host smart-d59fc766-350b-48b0-bab6-68f862f1f8e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298434549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3298434549
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3616043107
Short name T166
Test name
Test status
Simulation time 119998520113 ps
CPU time 458.74 seconds
Started Jul 30 07:20:26 PM PDT 24
Finished Jul 30 07:28:05 PM PDT 24
Peak memory 201896 kb
Host smart-fa8b8a17-aae6-4183-8125-76c541873d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616043107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3616043107
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3438906498
Short name T477
Test name
Test status
Simulation time 22964926631 ps
CPU time 14.86 seconds
Started Jul 30 07:20:25 PM PDT 24
Finished Jul 30 07:20:40 PM PDT 24
Peak memory 201356 kb
Host smart-81de270d-c5d7-48e7-b67a-00e43a4baa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438906498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3438906498
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3247546400
Short name T573
Test name
Test status
Simulation time 3243722743 ps
CPU time 8.16 seconds
Started Jul 30 07:20:26 PM PDT 24
Finished Jul 30 07:20:34 PM PDT 24
Peak memory 201340 kb
Host smart-348b96e9-df81-4d7c-b9e0-f7da301177d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247546400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3247546400
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3167383656
Short name T467
Test name
Test status
Simulation time 5808491546 ps
CPU time 14.55 seconds
Started Jul 30 07:20:16 PM PDT 24
Finished Jul 30 07:20:30 PM PDT 24
Peak memory 201376 kb
Host smart-f2dc5547-2f83-4bf7-b136-364239db67fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167383656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3167383656
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.131549341
Short name T534
Test name
Test status
Simulation time 403071716064 ps
CPU time 410.69 seconds
Started Jul 30 07:20:33 PM PDT 24
Finished Jul 30 07:27:24 PM PDT 24
Peak memory 211904 kb
Host smart-c67dff76-b9e1-4bb6-8d38-8066d1149f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131549341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
131549341
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1615913182
Short name T237
Test name
Test status
Simulation time 399658938494 ps
CPU time 375.29 seconds
Started Jul 30 07:20:33 PM PDT 24
Finished Jul 30 07:26:49 PM PDT 24
Peak memory 209624 kb
Host smart-849364c1-14c3-4369-96c9-e3a953da2b8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615913182 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1615913182
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2322088359
Short name T524
Test name
Test status
Simulation time 304850012 ps
CPU time 1.3 seconds
Started Jul 30 07:20:44 PM PDT 24
Finished Jul 30 07:20:46 PM PDT 24
Peak memory 201260 kb
Host smart-90f3ec3d-84e8-4b9e-bab0-08b3721b4d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322088359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2322088359
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1522278900
Short name T97
Test name
Test status
Simulation time 162359122527 ps
CPU time 88.3 seconds
Started Jul 30 07:20:33 PM PDT 24
Finished Jul 30 07:22:01 PM PDT 24
Peak memory 201552 kb
Host smart-7e1841fb-e384-47a5-a8fe-ee5dc8d9835d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522278900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1522278900
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4016929997
Short name T551
Test name
Test status
Simulation time 326703581379 ps
CPU time 439.96 seconds
Started Jul 30 07:20:29 PM PDT 24
Finished Jul 30 07:27:49 PM PDT 24
Peak memory 201480 kb
Host smart-f265d165-2fd5-410c-886b-b085496451d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016929997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4016929997
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3593219995
Short name T719
Test name
Test status
Simulation time 170460318372 ps
CPU time 87.24 seconds
Started Jul 30 07:20:34 PM PDT 24
Finished Jul 30 07:22:02 PM PDT 24
Peak memory 201276 kb
Host smart-a480809f-457a-4510-b194-5cf801db17cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593219995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3593219995
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.653740991
Short name T265
Test name
Test status
Simulation time 162740779654 ps
CPU time 333.91 seconds
Started Jul 30 07:20:34 PM PDT 24
Finished Jul 30 07:26:08 PM PDT 24
Peak memory 201276 kb
Host smart-4e8977ec-4cd3-450d-a575-1cbbde3d1d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653740991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.653740991
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.583979889
Short name T796
Test name
Test status
Simulation time 491047390576 ps
CPU time 1073.82 seconds
Started Jul 30 07:20:30 PM PDT 24
Finished Jul 30 07:38:24 PM PDT 24
Peak memory 201452 kb
Host smart-03bbf72b-efef-4ecd-a7f1-79921e674e8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=583979889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.583979889
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3737832774
Short name T442
Test name
Test status
Simulation time 340382535809 ps
CPU time 771.48 seconds
Started Jul 30 07:20:33 PM PDT 24
Finished Jul 30 07:33:25 PM PDT 24
Peak memory 201384 kb
Host smart-666f1d64-10c7-4e7b-bbc1-f7fd1647d98b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737832774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3737832774
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.333090805
Short name T338
Test name
Test status
Simulation time 196350178679 ps
CPU time 98.34 seconds
Started Jul 30 07:20:34 PM PDT 24
Finished Jul 30 07:22:12 PM PDT 24
Peak memory 201456 kb
Host smart-81d2624b-b97d-4d6a-896a-5784781dc4f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333090805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.333090805
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1171647775
Short name T206
Test name
Test status
Simulation time 72043641622 ps
CPU time 258.95 seconds
Started Jul 30 07:20:41 PM PDT 24
Finished Jul 30 07:25:00 PM PDT 24
Peak memory 201836 kb
Host smart-b30fa3d2-e316-4a1d-9e8f-1644e20ce0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171647775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1171647775
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2713790176
Short name T761
Test name
Test status
Simulation time 30437899138 ps
CPU time 73.42 seconds
Started Jul 30 07:20:41 PM PDT 24
Finished Jul 30 07:21:55 PM PDT 24
Peak memory 201412 kb
Host smart-cafebae4-73ca-40b6-a7a5-a3a77cc15433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713790176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2713790176
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2152879734
Short name T610
Test name
Test status
Simulation time 4845358213 ps
CPU time 5.62 seconds
Started Jul 30 07:20:37 PM PDT 24
Finished Jul 30 07:20:43 PM PDT 24
Peak memory 201372 kb
Host smart-b0ee0b0d-ae6f-4985-98ab-ef8a3d417626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152879734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2152879734
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3161014600
Short name T408
Test name
Test status
Simulation time 5808078261 ps
CPU time 1.83 seconds
Started Jul 30 07:20:29 PM PDT 24
Finished Jul 30 07:20:31 PM PDT 24
Peak memory 201364 kb
Host smart-978aa3d7-2ae8-4ab1-8c94-21a726ab3f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161014600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3161014600
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1997555412
Short name T268
Test name
Test status
Simulation time 569705896753 ps
CPU time 1251.71 seconds
Started Jul 30 07:20:46 PM PDT 24
Finished Jul 30 07:41:38 PM PDT 24
Peak memory 201484 kb
Host smart-aba23e2e-cabc-4aee-ba7e-705fc82659e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997555412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1997555412
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4197567936
Short name T25
Test name
Test status
Simulation time 65176128748 ps
CPU time 40.26 seconds
Started Jul 30 07:20:44 PM PDT 24
Finished Jul 30 07:21:25 PM PDT 24
Peak memory 209756 kb
Host smart-c0b95a4c-d31a-40ae-bf62-3f4fa3fedcb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197567936 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4197567936
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1258369570
Short name T532
Test name
Test status
Simulation time 383257702 ps
CPU time 0.82 seconds
Started Jul 30 07:20:55 PM PDT 24
Finished Jul 30 07:20:56 PM PDT 24
Peak memory 201248 kb
Host smart-7ad65939-049c-40ea-ba11-b0f2d4305ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258369570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1258369570
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2264249625
Short name T266
Test name
Test status
Simulation time 158587007167 ps
CPU time 70.94 seconds
Started Jul 30 07:20:51 PM PDT 24
Finished Jul 30 07:22:02 PM PDT 24
Peak memory 201492 kb
Host smart-68710d8d-8870-4405-9eed-a9bd27fbf29c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264249625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2264249625
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4020948031
Short name T303
Test name
Test status
Simulation time 495690341763 ps
CPU time 1069.22 seconds
Started Jul 30 07:20:51 PM PDT 24
Finished Jul 30 07:38:40 PM PDT 24
Peak memory 201444 kb
Host smart-b9453e1d-ad42-473c-8d95-7f331707e0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020948031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4020948031
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1596901477
Short name T778
Test name
Test status
Simulation time 160108150176 ps
CPU time 100.52 seconds
Started Jul 30 07:20:47 PM PDT 24
Finished Jul 30 07:22:28 PM PDT 24
Peak memory 201476 kb
Host smart-15005951-51be-4327-ab1b-62ee21a1fe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596901477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1596901477
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3573588438
Short name T690
Test name
Test status
Simulation time 502961086500 ps
CPU time 1116.83 seconds
Started Jul 30 07:20:48 PM PDT 24
Finished Jul 30 07:39:25 PM PDT 24
Peak memory 201476 kb
Host smart-fcc48dcb-cd68-4c01-b655-0e74c62a5ec3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573588438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3573588438
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2322155061
Short name T688
Test name
Test status
Simulation time 320756761834 ps
CPU time 62.34 seconds
Started Jul 30 07:20:47 PM PDT 24
Finished Jul 30 07:21:50 PM PDT 24
Peak memory 201436 kb
Host smart-f00d2f04-eca7-4f32-8537-b14011edbd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322155061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2322155061
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.564872438
Short name T435
Test name
Test status
Simulation time 165334371891 ps
CPU time 391.4 seconds
Started Jul 30 07:20:50 PM PDT 24
Finished Jul 30 07:27:22 PM PDT 24
Peak memory 201436 kb
Host smart-2350f46d-b40a-4be0-a6f5-712be5e9ba5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=564872438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.564872438
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2500545860
Short name T160
Test name
Test status
Simulation time 364502334534 ps
CPU time 864.27 seconds
Started Jul 30 07:20:47 PM PDT 24
Finished Jul 30 07:35:11 PM PDT 24
Peak memory 201416 kb
Host smart-bdabcf22-82b5-4023-9fed-9bff26323274
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500545860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2500545860
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2495373272
Short name T717
Test name
Test status
Simulation time 596155677010 ps
CPU time 165.95 seconds
Started Jul 30 07:20:46 PM PDT 24
Finished Jul 30 07:23:33 PM PDT 24
Peak memory 201440 kb
Host smart-2065887a-eb75-44ed-bb9b-3d840e48303b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495373272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2495373272
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1518357244
Short name T493
Test name
Test status
Simulation time 65719159288 ps
CPU time 367.41 seconds
Started Jul 30 07:20:50 PM PDT 24
Finished Jul 30 07:26:58 PM PDT 24
Peak memory 201804 kb
Host smart-43efaad7-a564-4a7a-a958-2529ad1621aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518357244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1518357244
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1876694039
Short name T32
Test name
Test status
Simulation time 35585207562 ps
CPU time 19.49 seconds
Started Jul 30 07:20:50 PM PDT 24
Finished Jul 30 07:21:10 PM PDT 24
Peak memory 201356 kb
Host smart-d85b8702-1ddd-45e6-a574-f1eb683b1aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876694039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1876694039
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1572894358
Short name T568
Test name
Test status
Simulation time 2874381453 ps
CPU time 7.46 seconds
Started Jul 30 07:20:51 PM PDT 24
Finished Jul 30 07:20:59 PM PDT 24
Peak memory 201376 kb
Host smart-da3ed97d-9ddb-4ab0-b044-de07f3fac2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572894358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1572894358
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3086277408
Short name T472
Test name
Test status
Simulation time 6006596470 ps
CPU time 4.33 seconds
Started Jul 30 07:20:43 PM PDT 24
Finished Jul 30 07:20:48 PM PDT 24
Peak memory 201360 kb
Host smart-2e53f6e5-d5b8-49e0-ada6-57893ceab524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086277408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3086277408
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2927869958
Short name T312
Test name
Test status
Simulation time 495237162845 ps
CPU time 1169.66 seconds
Started Jul 30 07:20:56 PM PDT 24
Finished Jul 30 07:40:26 PM PDT 24
Peak memory 201424 kb
Host smart-6a32e16e-6b54-465b-a784-7eea3a18d517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927869958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2927869958
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3106926081
Short name T369
Test name
Test status
Simulation time 529097378 ps
CPU time 1.25 seconds
Started Jul 30 07:08:17 PM PDT 24
Finished Jul 30 07:08:18 PM PDT 24
Peak memory 201232 kb
Host smart-d2c4538a-ffcb-4e3a-aa78-02ef396c319b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106926081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3106926081
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2585120735
Short name T29
Test name
Test status
Simulation time 169751144932 ps
CPU time 26.43 seconds
Started Jul 30 07:08:03 PM PDT 24
Finished Jul 30 07:08:30 PM PDT 24
Peak memory 201472 kb
Host smart-576b2229-8ca7-4798-9773-0dc8ab8f47da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585120735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2585120735
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.71741412
Short name T228
Test name
Test status
Simulation time 160266275125 ps
CPU time 272.27 seconds
Started Jul 30 07:08:02 PM PDT 24
Finished Jul 30 07:12:35 PM PDT 24
Peak memory 201440 kb
Host smart-8f4fe4b2-4c25-4738-bf23-c74e65d91399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71741412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.71741412
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1962638634
Short name T295
Test name
Test status
Simulation time 498460103913 ps
CPU time 92.1 seconds
Started Jul 30 07:07:56 PM PDT 24
Finished Jul 30 07:09:28 PM PDT 24
Peak memory 201476 kb
Host smart-f97f270d-5ef3-47b1-896c-815318f294e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962638634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1962638634
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1016646864
Short name T148
Test name
Test status
Simulation time 165267095764 ps
CPU time 56.14 seconds
Started Jul 30 07:07:57 PM PDT 24
Finished Jul 30 07:08:53 PM PDT 24
Peak memory 201420 kb
Host smart-b8bd54bd-bde6-4d45-b249-b63196ee6874
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016646864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1016646864
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3635474995
Short name T676
Test name
Test status
Simulation time 490421247865 ps
CPU time 1060.03 seconds
Started Jul 30 07:07:57 PM PDT 24
Finished Jul 30 07:25:37 PM PDT 24
Peak memory 201560 kb
Host smart-623db2be-5d48-4035-94f5-e6c5291e4367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635474995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3635474995
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.4261799403
Short name T507
Test name
Test status
Simulation time 495053851702 ps
CPU time 288.27 seconds
Started Jul 30 07:07:57 PM PDT 24
Finished Jul 30 07:12:46 PM PDT 24
Peak memory 201432 kb
Host smart-da30203a-f9a2-44f0-b538-5f918852d88d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261799403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.4261799403
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3686103393
Short name T425
Test name
Test status
Simulation time 172346383210 ps
CPU time 229.08 seconds
Started Jul 30 07:07:59 PM PDT 24
Finished Jul 30 07:11:48 PM PDT 24
Peak memory 201492 kb
Host smart-a9b903b9-bbd1-4611-b5ee-9f1ed4a81cc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686103393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3686103393
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2302266448
Short name T501
Test name
Test status
Simulation time 590717738476 ps
CPU time 1460.59 seconds
Started Jul 30 07:07:59 PM PDT 24
Finished Jul 30 07:32:20 PM PDT 24
Peak memory 201364 kb
Host smart-8443cb9a-5b43-4373-83da-6c6c41076994
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302266448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2302266448
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1447159175
Short name T552
Test name
Test status
Simulation time 79344217762 ps
CPU time 301.56 seconds
Started Jul 30 07:08:15 PM PDT 24
Finished Jul 30 07:13:17 PM PDT 24
Peak memory 201832 kb
Host smart-da9b99cc-2530-46a2-8a88-25eecf5afa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447159175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1447159175
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.199344115
Short name T593
Test name
Test status
Simulation time 33501616894 ps
CPU time 76.63 seconds
Started Jul 30 07:08:09 PM PDT 24
Finished Jul 30 07:09:25 PM PDT 24
Peak memory 201504 kb
Host smart-a4f7f11b-106f-4fb5-808a-23d5be071a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199344115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.199344115
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1166094195
Short name T398
Test name
Test status
Simulation time 4971548556 ps
CPU time 11.54 seconds
Started Jul 30 07:08:10 PM PDT 24
Finished Jul 30 07:08:21 PM PDT 24
Peak memory 201336 kb
Host smart-f283bc6b-9d39-4e51-9a61-b097b3ccd9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166094195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1166094195
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1260782138
Short name T348
Test name
Test status
Simulation time 5555626589 ps
CPU time 4.22 seconds
Started Jul 30 07:07:53 PM PDT 24
Finished Jul 30 07:07:57 PM PDT 24
Peak memory 201392 kb
Host smart-ea0e5c2e-12a5-49d0-8444-34d0f6818d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260782138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1260782138
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3246383278
Short name T481
Test name
Test status
Simulation time 526540268 ps
CPU time 1.75 seconds
Started Jul 30 07:08:30 PM PDT 24
Finished Jul 30 07:08:32 PM PDT 24
Peak memory 201228 kb
Host smart-805d20ed-f37c-4c37-bb6c-1b0302e043aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246383278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3246383278
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.714285742
Short name T512
Test name
Test status
Simulation time 358758975230 ps
CPU time 590.96 seconds
Started Jul 30 07:08:25 PM PDT 24
Finished Jul 30 07:18:16 PM PDT 24
Peak memory 201484 kb
Host smart-f40ff28a-4eea-467b-935e-301c98b13723
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714285742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.714285742
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3400248810
Short name T738
Test name
Test status
Simulation time 384197408798 ps
CPU time 894.08 seconds
Started Jul 30 07:08:25 PM PDT 24
Finished Jul 30 07:23:19 PM PDT 24
Peak memory 201448 kb
Host smart-a24e86af-213a-4454-b494-ea5e8b2adce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400248810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3400248810
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1194155293
Short name T358
Test name
Test status
Simulation time 498099786969 ps
CPU time 1065.1 seconds
Started Jul 30 07:08:26 PM PDT 24
Finished Jul 30 07:26:11 PM PDT 24
Peak memory 201432 kb
Host smart-142af2f5-2f5b-4e46-81ce-8a11ffcc2311
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194155293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1194155293
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.4198716865
Short name T8
Test name
Test status
Simulation time 165031060662 ps
CPU time 185.4 seconds
Started Jul 30 07:08:20 PM PDT 24
Finished Jul 30 07:11:25 PM PDT 24
Peak memory 201484 kb
Host smart-cf19d30d-f33f-4854-8b30-c5fd85be9c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198716865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4198716865
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1261258952
Short name T454
Test name
Test status
Simulation time 495249319835 ps
CPU time 620.06 seconds
Started Jul 30 07:08:25 PM PDT 24
Finished Jul 30 07:18:45 PM PDT 24
Peak memory 201432 kb
Host smart-1c96434e-5cc3-4d77-a6f8-c80dc945ca0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261258952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1261258952
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2611119643
Short name T506
Test name
Test status
Simulation time 412692604360 ps
CPU time 445.75 seconds
Started Jul 30 07:08:25 PM PDT 24
Finished Jul 30 07:15:51 PM PDT 24
Peak memory 201432 kb
Host smart-923051c8-6671-4a1c-9b13-f4510ae05b2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611119643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2611119643
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1509006255
Short name T169
Test name
Test status
Simulation time 108506273302 ps
CPU time 366.85 seconds
Started Jul 30 07:08:26 PM PDT 24
Finished Jul 30 07:14:33 PM PDT 24
Peak memory 201828 kb
Host smart-20eba2c9-6457-4068-b62e-bd2d327c6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509006255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1509006255
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4257379365
Short name T779
Test name
Test status
Simulation time 27778039856 ps
CPU time 16.75 seconds
Started Jul 30 07:08:26 PM PDT 24
Finished Jul 30 07:08:43 PM PDT 24
Peak memory 201360 kb
Host smart-d5f70bf7-acf2-404c-a844-137975705ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257379365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4257379365
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4058198950
Short name T350
Test name
Test status
Simulation time 4957668552 ps
CPU time 3.53 seconds
Started Jul 30 07:08:27 PM PDT 24
Finished Jul 30 07:08:31 PM PDT 24
Peak memory 201356 kb
Host smart-c5d796e1-854f-4a78-9596-90da0ab7ec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058198950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4058198950
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3403873005
Short name T359
Test name
Test status
Simulation time 5969325727 ps
CPU time 13.39 seconds
Started Jul 30 07:08:22 PM PDT 24
Finished Jul 30 07:08:35 PM PDT 24
Peak memory 201368 kb
Host smart-934de203-73d7-47f7-8f39-2e9dcbae67bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403873005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3403873005
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.136156746
Short name T221
Test name
Test status
Simulation time 334705575023 ps
CPU time 200.59 seconds
Started Jul 30 07:08:28 PM PDT 24
Finished Jul 30 07:11:49 PM PDT 24
Peak memory 201428 kb
Host smart-5a0b0aec-7ed4-4689-813f-0cf406373091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136156746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.136156746
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4194875045
Short name T787
Test name
Test status
Simulation time 126211644763 ps
CPU time 135.62 seconds
Started Jul 30 07:08:27 PM PDT 24
Finished Jul 30 07:10:43 PM PDT 24
Peak memory 209756 kb
Host smart-2df1243c-ca2f-4110-ba30-a8b4da951dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194875045 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4194875045
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1683479261
Short name T387
Test name
Test status
Simulation time 411470154 ps
CPU time 1.06 seconds
Started Jul 30 07:08:53 PM PDT 24
Finished Jul 30 07:08:54 PM PDT 24
Peak memory 201236 kb
Host smart-c287ab25-d6eb-4640-8e93-ded2f2b1d9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683479261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1683479261
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2219357188
Short name T394
Test name
Test status
Simulation time 174092158433 ps
CPU time 365.62 seconds
Started Jul 30 07:08:41 PM PDT 24
Finished Jul 30 07:14:47 PM PDT 24
Peak memory 201452 kb
Host smart-95a83329-b918-40a8-b4e7-c0c3e9f566bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219357188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2219357188
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3568267934
Short name T286
Test name
Test status
Simulation time 544275419324 ps
CPU time 628.78 seconds
Started Jul 30 07:08:47 PM PDT 24
Finished Jul 30 07:19:16 PM PDT 24
Peak memory 201472 kb
Host smart-47b0ab82-1c75-422b-8ef3-edec60cf1574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568267934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3568267934
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3486591656
Short name T544
Test name
Test status
Simulation time 324511410820 ps
CPU time 430.38 seconds
Started Jul 30 07:08:38 PM PDT 24
Finished Jul 30 07:15:49 PM PDT 24
Peak memory 201444 kb
Host smart-5347f192-567d-4475-b9a4-f76650028a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486591656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3486591656
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3366064394
Short name T371
Test name
Test status
Simulation time 334893162185 ps
CPU time 190.87 seconds
Started Jul 30 07:08:39 PM PDT 24
Finished Jul 30 07:11:50 PM PDT 24
Peak memory 201480 kb
Host smart-fba6cd08-c9c2-4e47-8c2d-906adf08848a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366064394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3366064394
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1047211177
Short name T232
Test name
Test status
Simulation time 327807503274 ps
CPU time 761.57 seconds
Started Jul 30 07:08:30 PM PDT 24
Finished Jul 30 07:21:12 PM PDT 24
Peak memory 201448 kb
Host smart-7b3347b6-af56-4357-800e-810fd843831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047211177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1047211177
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3980729894
Short name T546
Test name
Test status
Simulation time 323789763999 ps
CPU time 193.95 seconds
Started Jul 30 07:08:36 PM PDT 24
Finished Jul 30 07:11:50 PM PDT 24
Peak memory 201480 kb
Host smart-21e88c38-7d73-44be-ad48-a421c604bc6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980729894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3980729894
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2829041099
Short name T47
Test name
Test status
Simulation time 354420584577 ps
CPU time 424.72 seconds
Started Jul 30 07:08:40 PM PDT 24
Finished Jul 30 07:15:45 PM PDT 24
Peak memory 201444 kb
Host smart-2e281fcc-8ba4-4e55-a1d7-1b5e2ae770f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829041099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2829041099
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3803646964
Short name T422
Test name
Test status
Simulation time 208210602028 ps
CPU time 133.47 seconds
Started Jul 30 07:08:44 PM PDT 24
Finished Jul 30 07:10:57 PM PDT 24
Peak memory 201440 kb
Host smart-2f3a3a76-2ef7-47b3-98ba-ce5f28c10b24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803646964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3803646964
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3060849456
Short name T485
Test name
Test status
Simulation time 126506956881 ps
CPU time 666.22 seconds
Started Jul 30 07:08:48 PM PDT 24
Finished Jul 30 07:19:55 PM PDT 24
Peak memory 201888 kb
Host smart-93125671-0973-4b8e-b41e-70ee1a8e5714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060849456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3060849456
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2068950727
Short name T356
Test name
Test status
Simulation time 24738308128 ps
CPU time 58.46 seconds
Started Jul 30 07:08:48 PM PDT 24
Finished Jul 30 07:09:46 PM PDT 24
Peak memory 201376 kb
Host smart-c7a91038-8708-4fa7-b5ae-460d4be8f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068950727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2068950727
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2469080121
Short name T520
Test name
Test status
Simulation time 3278712269 ps
CPU time 8.24 seconds
Started Jul 30 07:08:47 PM PDT 24
Finished Jul 30 07:08:55 PM PDT 24
Peak memory 201284 kb
Host smart-06fd5835-980b-4d86-ab5a-d995ae740762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469080121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2469080121
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1977326569
Short name T562
Test name
Test status
Simulation time 5990991723 ps
CPU time 14.37 seconds
Started Jul 30 07:08:30 PM PDT 24
Finished Jul 30 07:08:44 PM PDT 24
Peak memory 201368 kb
Host smart-abaaf990-c18a-4ad4-b620-98f747fc7cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977326569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1977326569
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3774012843
Short name T318
Test name
Test status
Simulation time 204614425427 ps
CPU time 82.74 seconds
Started Jul 30 07:08:51 PM PDT 24
Finished Jul 30 07:10:14 PM PDT 24
Peak memory 201432 kb
Host smart-43b82f82-a1bc-4593-b23c-6e4c120778c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774012843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3774012843
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.65416539
Short name T118
Test name
Test status
Simulation time 223132277217 ps
CPU time 81.19 seconds
Started Jul 30 07:08:49 PM PDT 24
Finished Jul 30 07:10:10 PM PDT 24
Peak memory 209664 kb
Host smart-768fffb1-05f1-48f4-8845-b51e4e14609d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65416539 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.65416539
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3471470031
Short name T521
Test name
Test status
Simulation time 524212147 ps
CPU time 1.72 seconds
Started Jul 30 07:09:08 PM PDT 24
Finished Jul 30 07:09:10 PM PDT 24
Peak memory 201240 kb
Host smart-cf1c6f8a-6c3d-4861-8d3f-4297c7a703a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471470031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3471470031
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2126068101
Short name T783
Test name
Test status
Simulation time 176926850912 ps
CPU time 29.57 seconds
Started Jul 30 07:09:02 PM PDT 24
Finished Jul 30 07:09:32 PM PDT 24
Peak memory 201496 kb
Host smart-c0afa690-e0fa-41e6-b23b-beb8b8218027
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126068101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2126068101
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3685936380
Short name T162
Test name
Test status
Simulation time 350763244612 ps
CPU time 101.18 seconds
Started Jul 30 07:09:16 PM PDT 24
Finished Jul 30 07:10:57 PM PDT 24
Peak memory 201480 kb
Host smart-9e78e2d5-82e6-4f3d-81f4-a2c39c862df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685936380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3685936380
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2900722427
Short name T300
Test name
Test status
Simulation time 165158468919 ps
CPU time 101.58 seconds
Started Jul 30 07:08:54 PM PDT 24
Finished Jul 30 07:10:36 PM PDT 24
Peak memory 201508 kb
Host smart-24b03765-f972-4dc4-8334-d1b497fa3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900722427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2900722427
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2949450957
Short name T426
Test name
Test status
Simulation time 496288971748 ps
CPU time 1178.32 seconds
Started Jul 30 07:08:59 PM PDT 24
Finished Jul 30 07:28:38 PM PDT 24
Peak memory 201468 kb
Host smart-4885e0be-8dfb-4670-a54a-44d5b3853cef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949450957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2949450957
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2849041874
Short name T465
Test name
Test status
Simulation time 335443369474 ps
CPU time 395.92 seconds
Started Jul 30 07:08:54 PM PDT 24
Finished Jul 30 07:15:30 PM PDT 24
Peak memory 201456 kb
Host smart-8883e090-dad2-4398-8244-281ff33e52c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849041874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2849041874
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3292850601
Short name T632
Test name
Test status
Simulation time 325138627845 ps
CPU time 748.09 seconds
Started Jul 30 07:08:55 PM PDT 24
Finished Jul 30 07:21:23 PM PDT 24
Peak memory 201480 kb
Host smart-f64abcde-5707-4b27-b043-ad3d8a275868
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292850601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3292850601
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3799719646
Short name T310
Test name
Test status
Simulation time 585241731848 ps
CPU time 1094.25 seconds
Started Jul 30 07:09:05 PM PDT 24
Finished Jul 30 07:27:20 PM PDT 24
Peak memory 201440 kb
Host smart-b96f00c5-807e-4510-921c-b2bc1ccb5557
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799719646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3799719646
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.146209974
Short name T165
Test name
Test status
Simulation time 603358442650 ps
CPU time 388.67 seconds
Started Jul 30 07:09:01 PM PDT 24
Finished Jul 30 07:15:30 PM PDT 24
Peak memory 201512 kb
Host smart-6eb73720-8d15-4481-889c-e2de05f18481
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146209974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.146209974
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.324743235
Short name T788
Test name
Test status
Simulation time 105021600678 ps
CPU time 543.13 seconds
Started Jul 30 07:09:07 PM PDT 24
Finished Jul 30 07:18:10 PM PDT 24
Peak memory 201808 kb
Host smart-c9c52f33-384f-4be8-9bcf-2d9ef8ca6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324743235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.324743235
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.835165015
Short name T525
Test name
Test status
Simulation time 38457476899 ps
CPU time 7.24 seconds
Started Jul 30 07:09:06 PM PDT 24
Finished Jul 30 07:09:13 PM PDT 24
Peak memory 201356 kb
Host smart-7d27a52e-288a-48e7-a213-88dd3ba63a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835165015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.835165015
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.462690341
Short name T111
Test name
Test status
Simulation time 4642652986 ps
CPU time 12.01 seconds
Started Jul 30 07:09:06 PM PDT 24
Finished Jul 30 07:09:19 PM PDT 24
Peak memory 201408 kb
Host smart-7d7418d2-9c25-49f7-8d9a-fdafa4511fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462690341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.462690341
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2639774202
Short name T349
Test name
Test status
Simulation time 5919783651 ps
CPU time 13.09 seconds
Started Jul 30 07:08:56 PM PDT 24
Finished Jul 30 07:09:09 PM PDT 24
Peak memory 201352 kb
Host smart-c9ed8248-7cda-41e7-9610-8746101d1547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639774202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2639774202
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2739144682
Short name T23
Test name
Test status
Simulation time 364019727892 ps
CPU time 238.78 seconds
Started Jul 30 07:09:06 PM PDT 24
Finished Jul 30 07:13:04 PM PDT 24
Peak memory 210152 kb
Host smart-09f13f41-4b4f-4334-aced-3f74c3f87a53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739144682 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2739144682
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3326924095
Short name T84
Test name
Test status
Simulation time 397532892 ps
CPU time 0.99 seconds
Started Jul 30 07:09:23 PM PDT 24
Finished Jul 30 07:09:24 PM PDT 24
Peak memory 201184 kb
Host smart-0d290fab-857c-4e1c-b3f2-b259300e0466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326924095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3326924095
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2624579654
Short name T750
Test name
Test status
Simulation time 165439451464 ps
CPU time 4.04 seconds
Started Jul 30 07:09:16 PM PDT 24
Finished Jul 30 07:09:20 PM PDT 24
Peak memory 201452 kb
Host smart-c2532e20-f900-4f02-a82d-b8baec1dea85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624579654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2624579654
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2399561083
Short name T262
Test name
Test status
Simulation time 324465764911 ps
CPU time 108.23 seconds
Started Jul 30 07:09:18 PM PDT 24
Finished Jul 30 07:11:06 PM PDT 24
Peak memory 201508 kb
Host smart-b4bbb1fb-3e9a-4660-bf50-cc3954e87216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399561083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2399561083
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1936204314
Short name T607
Test name
Test status
Simulation time 163139170234 ps
CPU time 382.26 seconds
Started Jul 30 07:09:13 PM PDT 24
Finished Jul 30 07:15:36 PM PDT 24
Peak memory 201436 kb
Host smart-9063fa83-4b1d-4ce0-8499-bfe40eccd31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936204314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1936204314
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.622213283
Short name T418
Test name
Test status
Simulation time 325492661012 ps
CPU time 204.99 seconds
Started Jul 30 07:09:16 PM PDT 24
Finished Jul 30 07:12:41 PM PDT 24
Peak memory 201432 kb
Host smart-5dbc396a-26f8-40ad-b53c-99e63e221f73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=622213283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.622213283
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2707882692
Short name T736
Test name
Test status
Simulation time 334298964735 ps
CPU time 712.98 seconds
Started Jul 30 07:09:11 PM PDT 24
Finished Jul 30 07:21:04 PM PDT 24
Peak memory 201500 kb
Host smart-67147921-97b6-439e-a960-715441b42955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707882692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2707882692
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.342208455
Short name T197
Test name
Test status
Simulation time 321660358793 ps
CPU time 339.76 seconds
Started Jul 30 07:09:14 PM PDT 24
Finished Jul 30 07:14:54 PM PDT 24
Peak memory 201376 kb
Host smart-76ca9b5d-e02d-4271-8adc-268805224ae2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=342208455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.342208455
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3163573657
Short name T653
Test name
Test status
Simulation time 189031788919 ps
CPU time 112.89 seconds
Started Jul 30 07:09:17 PM PDT 24
Finished Jul 30 07:11:10 PM PDT 24
Peak memory 201428 kb
Host smart-5f6d146a-6c5f-4ee2-9291-f7c9c37e77d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163573657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3163573657
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2566609929
Short name T389
Test name
Test status
Simulation time 198779294369 ps
CPU time 125.32 seconds
Started Jul 30 07:09:16 PM PDT 24
Finished Jul 30 07:11:22 PM PDT 24
Peak memory 201468 kb
Host smart-f8d669f7-f687-4197-8d46-1db8db88cbdd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566609929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2566609929
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3688387097
Short name T214
Test name
Test status
Simulation time 100232025262 ps
CPU time 523.33 seconds
Started Jul 30 07:09:18 PM PDT 24
Finished Jul 30 07:18:01 PM PDT 24
Peak memory 201884 kb
Host smart-404223fd-0080-4f18-aa61-7088dd42a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688387097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3688387097
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.920936259
Short name T407
Test name
Test status
Simulation time 38924775801 ps
CPU time 30.02 seconds
Started Jul 30 07:09:17 PM PDT 24
Finished Jul 30 07:09:47 PM PDT 24
Peak memory 201400 kb
Host smart-a3b1029f-4c99-470e-abb7-a2fa2c983c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920936259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.920936259
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1335163059
Short name T697
Test name
Test status
Simulation time 3592038616 ps
CPU time 2.98 seconds
Started Jul 30 07:09:18 PM PDT 24
Finished Jul 30 07:09:21 PM PDT 24
Peak memory 201344 kb
Host smart-40f1fdc5-7412-4551-9cf7-94efd15e3553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335163059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1335163059
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2072010636
Short name T121
Test name
Test status
Simulation time 5960629971 ps
CPU time 3.35 seconds
Started Jul 30 07:09:10 PM PDT 24
Finished Jul 30 07:09:14 PM PDT 24
Peak memory 201368 kb
Host smart-62104481-2f83-4f64-a5ef-36944beb641f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072010636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2072010636
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1036610272
Short name T636
Test name
Test status
Simulation time 185483468669 ps
CPU time 388.22 seconds
Started Jul 30 07:09:25 PM PDT 24
Finished Jul 30 07:15:53 PM PDT 24
Peak memory 201496 kb
Host smart-c384860d-a523-46ae-9a9d-d37704e08372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036610272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1036610272
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2624764288
Short name T594
Test name
Test status
Simulation time 18383218060 ps
CPU time 37.49 seconds
Started Jul 30 07:09:24 PM PDT 24
Finished Jul 30 07:10:01 PM PDT 24
Peak memory 211028 kb
Host smart-b7834df9-e209-434e-b5cc-072109eb9753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624764288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2624764288
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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