Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6289	1			T1	57		T8	40		T9	10
testmodes[AdcCtrlTestmodeNormal]	5092	1			T1	66		T2	1		T3	1
testmodes[AdcCtrlTestmodeLowpower]	5502	1			T1	58		T2	1		T5	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3358	1			T1	20		T8	12		T9	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1581	1			T1	21		T8	12		T9	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1241	1			T1	15		T8	16		T15	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1604	1			T1	17		T8	19		T9	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1843	1			T1	26		T7	1		T8	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1298	1			T1	23		T2	1		T8	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1215	1			T1	19		T8	9		T15	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1318	1			T1	19		T8	19		T15	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2729	1			T1	20		T5	2		T8	22