Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21385

1

T1

181

T3

1

T5

21

auto[ADC_CTRL_FILTER_COND_OUT]

3582

1

T2

21

T6

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18921

1

T1

181

T2

21

T6

1

auto[1]

6046

1

T3

1

T5

21

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T180	1		-	-		-	-
values[0]	62	1			T221	1		T161	9		T174	24
values[1]	635	1			T53	18		T70	9		T149	12
values[2]	749	1			T70	6		T148	30		T41	1
values[3]	748	1			T7	1		T145	22		T147	1
values[4]	627	1			T2	6		T152	1		T157	1
values[5]	2886	1			T3	1		T5	21		T6	1
values[6]	645	1			T7	1		T59	6		T46	16
values[7]	625	1			T39	19		T156	11		T146	1
values[8]	617	1			T57	1		T50	14		T153	10
values[9]	1394	1			T2	15		T13	28		T58	29
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	912	1			T53	18		T221	1		T70	9
values[1]	742	1			T157	1		T70	13		T148	30
values[2]	623	1			T2	6		T7	1		T152	1
values[3]	2894	1			T3	1		T5	21		T11	10
values[4]	757	1			T6	1		T52	13		T222	18
values[5]	643	1			T7	1		T59	6		T46	16
values[6]	506	1			T39	19		T156	11		T147	1
values[7]	777	1			T57	1		T59	18		T50	14
values[8]	1007	1			T2	15		T13	28		T58	29
values[9]	128	1			T148	3		T43	4		T164	1
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T223	12		T171	11		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T53	14		T221	1		T70	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	7		T148	5		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T157	1		T70	2		T148	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	1		T152	1		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T2	1		T147	1		T196	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T3	1		T5	21		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T57	17		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T222	16		T199	22		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T52	13		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T59	6		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	9		T146	1		T154	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T39	10		T156	3		T203	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T147	1		T159	5		T224	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T50	1		T40	8		T151	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T57	1		T59	18		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T147	1		T196	1		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T2	7		T13	15		T58	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T148	3		T43	2		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T164	1		T111	14		T226	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T172	16		T227	2		T228	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T53	4		T70	6		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T148	15		T149	15		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T70	4		T148	1		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T145	11		T69	8		T199	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	5		T196	4		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T11	9		T49	22		T69	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T57	16		T229	18		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T222	2		T199	22		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T145	4		T231	2		T232	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T69	5		T233	11		T174	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	7		T154	10		T162	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T39	9		T156	8		T203	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T234	7		T235	2		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T50	13		T40	20		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T145	7		T165	3		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T172	8		T237	7		T170	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T2	8		T13	13		T58	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T43	2		T238	5		T239	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T111	12		T226	10		T240	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T174	14		T177	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T221	1		T161	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T62	1		T172	1		T227	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	14		T70	3		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T148	5		T41	1		T149	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T70	2		T148	9		T242	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	1		T145	11		T69	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T147	1		T157	1		T196	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T152	1		T224	8		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T157	1		T171	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T3	1		T5	21		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	1		T12	1		T57	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T59	6		T222	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	9		T52	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	10		T156	3		T69	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	1		T159	5		T224	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	1		T151	18		T227	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T57	1		T153	10		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T40	8		T147	1		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	476	1			T2	7		T13	15		T58	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T174	10		T177	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T161	8		T241	7		T114	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T172	16		T227	2		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T53	4		T70	6		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	15		T149	15		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T70	4		T148	1		T242	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T145	11		T69	8		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T196	4		T229	18		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T172	8		T243	6		T94	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T2	5		T29	10		T244	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T11	9		T49	22		T69	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T57	16		T145	4		T16	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T222	2		T199	22		T245	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T46	7		T154	10		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	9		T156	8		T69	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T234	7		T235	2		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T50	13		T151	17		T227	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T246	12		T162	2		T247	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T40	20		T43	2		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T2	8		T13	13		T58	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T223	1		T171	1		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T53	5		T221	1		T70	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T70	1		T148	16		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T157	1		T70	5		T148	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T152	1		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	6		T147	1		T196	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T3	1		T5	3		T11	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T57	17		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T222	3		T199	24		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	1		T52	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	1		T59	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	8		T146	1		T154	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	15		T156	9		T203	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T147	1		T159	1		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T50	14		T40	26		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T57	1		T59	1		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T147	1		T196	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T2	9		T13	14		T58	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T148	1		T43	4		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T164	1		T111	13		T226	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T223	11		T171	10		T227	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	13		T70	2		T242	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T70	6		T148	4		T149	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T70	1		T148	8		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T145	10		T69	2		T199	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T196	6		T92	11		T248	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T5	18		T45	14		T47	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T57	16		T229	11		T171	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T222	15		T199	20		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T52	12		T145	2		T236	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T59	5		T69	9		T233	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T46	8		T154	7		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T39	4		T156	2		T203	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T159	4		T224	12		T234	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	2		T151	14		T227	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T59	17		T145	9		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T159	13		T250	10		T189	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	6		T13	14		T58	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T148	2		T238	5		T239	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T111	13		T226	10		T251	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T174	11		T177	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T221	1		T161	9		T241	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T62	1		T172	17		T227	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T53	5		T70	7		T149	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T148	16		T41	1		T149	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T70	5		T148	2		T242	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T145	12		T69	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T147	1		T157	1		T196	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T152	1		T224	1		T172	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	6		T157	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T3	1		T5	3		T11	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T12	1		T57	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T59	1		T222	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T46	8		T52	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	15		T156	9		T69	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T146	1		T159	1		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	14		T151	19		T227	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T57	1		T153	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T40	26		T147	1		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	451	1			T2	9		T13	14		T58	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T174	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T114	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T227	13		T228	2		T252	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T53	13		T70	2		T253	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T148	4		T149	17		T223	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T70	1		T148	8		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T145	10		T69	2		T70	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T196	6		T229	11		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T224	7		T254	12		T255	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T171	8		T189	10		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T5	18		T45	14		T47	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T57	16		T145	2		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T59	5		T222	15		T199	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	8		T52	12		T154	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	4		T156	2		T69	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T159	4		T224	12		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T151	16		T227	15		T169	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T153	9		T234	11		T246	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T40	2		T148	2		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T2	6		T13	14		T58	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19372

1

T1

181

T2

15

T6

1

auto[ADC_CTRL_FILTER_COND_OUT]

5595

1

T2

6

T3

1

T5

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18986

1

T1

181

T2

6

T6

1

auto[1]

5981

1

T2

15

T3

1

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T256	25		T257	5		-	-
values[0]	39	1			T258	10		T259	28		T260	1
values[1]	730	1			T6	1		T57	33		T53	16
values[2]	715	1			T7	1		T57	1		T39	19
values[3]	743	1			T7	1		T59	18		T222	18
values[4]	768	1			T2	15		T152	1		T145	7
values[5]	528	1			T12	1		T156	11		T69	11
values[6]	574	1			T57	1		T59	6		T152	1
values[7]	796	1			T2	6		T50	14		T40	28
values[8]	605	1			T13	28		T58	29		T53	18
values[9]	3461	1			T3	1		T5	21		T11	10
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	819	1			T6	1		T57	33		T39	19
values[1]	3132	1			T3	1		T5	21		T7	1
values[2]	693	1			T7	1		T59	18		T222	18
values[3]	675	1			T2	15		T152	1		T156	11
values[4]	573	1			T12	1		T57	1		T69	11
values[5]	658	1			T2	6		T59	6		T152	1
values[6]	715	1			T50	14		T40	28		T154	18
values[7]	616	1			T13	28		T58	29		T53	18
values[8]	877	1			T52	13		T145	17		T196	12
values[9]	202	1			T153	10		T243	7		T162	3
minimum	16007	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	1		T57	17		T145	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	10		T53	8		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T147	2		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1751	1			T3	1		T5	21		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T7	1		T59	18		T222	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	1		T234	7		T32	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	7		T156	3		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T152	1		T221	1		T70	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T69	3		T41	4		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T57	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T59	6		T156	11		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	1		T152	1		T159	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T50	1		T40	8		T149	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T154	8		T69	4		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	15		T58	17		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	14		T230	13		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T145	10		T159	8		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T52	13		T196	8		T199	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T153	10		T243	1		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T262	7		T252	5		T263	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T242	10		T264	1		T260	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	16		T145	11		T199	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	9		T53	8		T203	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T235	2		T233	18		T174	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1039	1			T11	9		T46	7		T49	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T222	2		T145	4		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T234	7		T32	6		T161	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	8		T156	8		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T70	4		T199	11		T148	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T69	8		T41	1		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T246	12		T236	14		T265	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T156	15		T158	4		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	5		T229	18		T237	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	13		T40	20		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T154	10		T69	6		T245	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	13		T58	12		T36	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T53	4		T230	12		T244	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T145	7		T149	11		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T196	4		T199	9		T235	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T243	6		T162	2		T255	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T262	6		T263	18		T114	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T242	17		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T256	13		T257	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T258	1		T259	20		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	1		T57	17		T145	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T53	8		T242	10		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	1		T147	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T57	1		T39	10		T46	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	1		T59	18		T222	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T146	1		T69	10		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	7		T145	3		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T152	1		T221	1		T70	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T156	3		T69	3		T70	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	1		T157	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T59	6		T158	1		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T57	1		T152	1		T159	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T50	1		T40	8		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T2	1		T154	8		T69	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	15		T58	17		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	14		T148	3		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T145	10		T153	10		T159	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1789	1			T3	1		T5	21		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T256	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T258	9		T259	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T57	16		T145	11		T199	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	8		T242	17		T203	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T235	2		T174	10		T177	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T39	9		T46	7		T70	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T222	2		T148	1		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T69	5		T234	7		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	8		T145	4		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T70	4		T199	11		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T156	8		T69	8		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T246	12		T266	7		T267	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T158	4		T230	12		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T237	7		T236	14		T265	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T50	13		T40	20		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	5		T154	10		T69	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	13		T58	12		T44	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	4		T230	12		T244	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T145	7		T149	11		T229	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1062	1			T11	9		T49	22		T195	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1