Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21533

1

T1

181

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3434

1

T2

6

T6

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18552

1

T1

181

T2

21

T7

2

auto[1]

6415

1

T3

1

T5

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	272	1			T12	1		T151	28		T235	29
values[0]	90	1			T226	21		T316	28		T317	1
values[1]	720	1			T6	1		T46	16		T50	14
values[2]	711	1			T57	33		T146	2		T196	1
values[3]	758	1			T152	1		T70	9		T199	23
values[4]	2966	1			T2	6		T3	1		T5	21
values[5]	596	1			T146	1		T70	6		T41	1
values[6]	614	1			T7	1		T57	1		T59	24
values[7]	736	1			T13	28		T145	7		T156	26
values[8]	699	1			T2	15		T53	18		T156	11
values[9]	827	1			T7	1		T58	29		T222	18
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	630	1			T6	1		T50	14		T145	17
values[1]	756	1			T57	33		T146	1		T148	3
values[2]	661	1			T57	1		T53	16		T152	1
values[3]	3012	1			T2	6		T3	1		T5	21
values[4]	603	1			T57	1		T59	6		T146	1
values[5]	548	1			T7	1		T59	18		T39	19
values[6]	812	1			T2	15		T13	28		T53	18
values[7]	706	1			T58	29		T222	18		T156	11
values[8]	742	1			T7	1		T152	1		T199	21
values[9]	170	1			T12	1		T172	9		T233	26
minimum	16327	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	1		T146	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	1		T145	10		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T146	1		T148	3		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T57	17		T242	10		T171	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T57	1		T53	8		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T199	12		T43	2		T234	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1696	1			T3	1		T5	21		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	1		T40	8		T153	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T221	1		T231	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T57	1		T59	6		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T39	10		T145	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T59	18		T145	11		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	7		T53	14		T156	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	15		T69	10		T171	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T156	3		T69	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	17		T222	16		T154	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T152	1		T199	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T234	8		T44	6		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T247	10		T254	13		T205	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T12	1		T172	1		T233	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15885	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T196	7		T203	3		T229	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T50	13		T247	11		T236	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T145	7		T30	2		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T165	1		T272	2		T246	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T57	16		T242	17		T232	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T53	8		T70	6		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T199	11		T43	2		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T11	9		T49	22		T195	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	5		T40	20		T199	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T231	2		T228	12		T279	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T70	4		T29	10		T246	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	9		T145	4		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T145	11		T16	6		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	8		T53	4		T156	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	13		T69	5		T172	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T156	8		T69	8		T149	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T58	12		T222	2		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T199	11		T148	15		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T234	6		T44	4		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T247	9		T205	3		T302	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T172	8		T233	11		T318	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	1		T46	7		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T196	4		T203	14		T229	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T235	16		T247	10		T92	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T12	1		T151	15		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T226	11		T316	15		T298	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T317	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	9		T50	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	1		T145	10		T196	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T146	2		T148	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T57	17		T196	1		T171	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	1		T70	3		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T199	12		T43	2		T242	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T3	1		T5	21		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T40	8		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T231	1		T33	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T146	1		T70	2		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	1		T39	10		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T57	1		T59	24		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T145	3		T156	11		T148	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	15		T157	1		T171	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	7		T53	14		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T154	8		T69	10		T159	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	1		T152	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T58	17		T222	16		T234	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T235	13		T247	9		T302	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T151	13		T168	9		T170	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T226	10		T316	13		T298	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T46	7		T50	13		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T145	7		T196	4		T203	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T272	2		T246	12		T268	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T57	16		T232	12		T301	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T70	6		T30	11		T165	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T199	11		T43	2		T242	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T11	9		T49	22		T53	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	5		T40	20		T199	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T231	2		T228	10		T279	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T70	4		T29	10		T32	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T39	9		T158	4		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T145	11		T16	6		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T145	4		T156	15		T148	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	13		T172	16		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	8		T53	4		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T154	10		T69	5		T235	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T199	11		T148	15		T234	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T58	12		T222	2		T234	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T50	14		T146	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	1		T145	8		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	1		T148	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T57	17		T242	18		T171	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T57	1		T53	9		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T199	12		T43	4		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T3	1		T5	3		T11	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	6		T40	26		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T221	1		T231	3		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T57	1		T59	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T39	15		T145	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T59	1		T145	12		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	9		T53	5		T156	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	14		T69	6		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T156	9		T69	9		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T58	13		T222	3		T154	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	1		T152	1		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T234	7		T44	7		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T247	10		T254	1		T205	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T12	1		T172	9		T233	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16030	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T196	5		T203	15		T229	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T249	6		T247	13		T236	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T145	9		T56	2		T319	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T148	2		T246	16		T174	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T57	16		T242	9		T171	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T53	7		T70	2		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T199	11		T234	11		T230	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T5	18		T45	14		T47	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	2		T153	9		T199	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T228	17		T279	8		T254	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T59	5		T70	1		T246	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T39	4		T145	2		T189	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T59	17		T145	10		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	6		T53	13		T156	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	14		T69	9		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T156	2		T69	2		T70	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T58	16		T222	15		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T199	9		T148	4		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T234	7		T44	3		T151	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T247	9		T254	12		T205	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T233	14		T318	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T46	8		T41	1		T229	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T196	6		T203	2		T229	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T235	14		T247	10		T92	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T12	1		T151	14		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T226	11		T316	14		T298	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T317	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T46	8		T50	14		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T145	8		T196	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T146	2		T148	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T57	17		T196	1		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T152	1		T70	7		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T199	12		T43	4		T242	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T3	1		T5	3		T11	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	6		T40	26		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T231	3		T33	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T146	1		T70	5		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T39	15		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T57	1		T59	2		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T145	5		T156	16		T148	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	14		T157	1		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	9		T53	5		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T154	11		T69	6		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	1		T152	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T58	13		T222	3		T234	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T235	15		T247	9		T92	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T151	14		T170	6		T318	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T226	10		T316	14		T298	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	8		T41	1		T229	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T145	9		T196	6		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T148	2		T246	16		T249	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T57	16		T171	8		T301	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T70	2		T250	10		T249	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T199	11		T242	9		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T5	18		T45	14		T47	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	2		T153	9		T199	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T228	2		T252	4		T279	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T70	1		T32	9		T246	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	4		T189	13		T228	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T59	22		T145	10		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T145	2		T156	10		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	14		T171	10		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	6		T53	13		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T154	7		T69	9		T159	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T199	9		T148	4		T223	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	16		T222	15		T234	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14