Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19336

1

T1

181

T2

15

T7

2

auto[ADC_CTRL_FILTER_COND_OUT]

5631

1

T2

6

T3

1

T5

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18975

1

T1

181

T2

6

T7

1

auto[1]

5992

1

T2

15

T3

1

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T52	13		T145	17		T159	5
values[0]	23	1			T264	1		T320	12		T304	1
values[1]	685	1			T6	1		T57	33		T53	16
values[2]	818	1			T7	1		T57	1		T39	19
values[3]	699	1			T7	1		T59	18		T222	18
values[4]	740	1			T2	15		T152	1		T145	7
values[5]	580	1			T12	1		T156	11		T69	11
values[6]	617	1			T57	1		T59	6		T152	1
values[7]	765	1			T2	6		T50	14		T40	28
values[8]	614	1			T13	28		T58	29		T53	18
values[9]	3206	1			T3	1		T5	21		T11	10
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T6	1		T57	33		T39	19
values[1]	3071	1			T3	1		T5	21		T7	1
values[2]	697	1			T7	1		T59	18		T222	18
values[3]	727	1			T2	15		T152	1		T156	11
values[4]	532	1			T12	1		T152	1		T69	11
values[5]	725	1			T2	6		T57	1		T59	6
values[6]	647	1			T50	14		T40	28		T154	18
values[7]	664	1			T13	28		T58	29		T53	18
values[8]	930	1			T52	13		T145	17		T196	1
values[9]	121	1			T153	10		T229	8		T243	7
minimum	16216	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T57	17		T145	11		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	1		T39	10		T53	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	1		T147	1		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1742	1			T3	1		T5	21		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	1		T59	18		T222	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T146	1		T234	7		T32	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	7		T156	3		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T152	1		T221	1		T70	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T69	3		T41	4		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T152	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T59	6		T156	11		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	1		T57	1		T229	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	1		T40	8		T149	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T154	8		T69	4		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	15		T58	17		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T53	14		T196	7		T230	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T145	10		T159	8		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T52	13		T196	1		T199	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T153	10		T229	6		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T252	5		T263	14		T321	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15888	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T242	10		T288	1		T264	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T57	16		T145	11		T172	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	9		T53	8		T203	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T235	2		T233	7		T174	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1011	1			T11	9		T46	7		T49	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T222	2		T145	4		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T234	7		T32	6		T161	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	8		T156	8		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T70	4		T199	11		T148	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T69	8		T41	1		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T246	12		T265	1		T255	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T156	15		T158	4		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	5		T229	18		T237	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T50	13		T40	20		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T154	10		T69	6		T245	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	13		T58	12		T44	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	4		T196	4		T230	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T145	7		T149	11		T272	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T199	9		T273	12		T232	35
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T229	2		T243	6		T162	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T263	18		T322	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T57	1		T40	1		T199	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T242	17		T323	14		T284	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T145	10		T159	5		T149	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T52	13		T232	2		T252	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T320	6		T293	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T264	1		T304	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T57	17		T145	11		T146	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	1		T53	8		T242	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T147	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T57	1		T39	10		T46	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	1		T59	18		T222	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T146	1		T147	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	7		T145	3		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T152	1		T221	1		T70	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T156	3		T69	3		T70	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T157	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T59	6		T158	1		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T57	1		T152	1		T159	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T50	1		T40	8		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	1		T154	8		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	15		T58	17		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T53	14		T69	4		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T153	10		T159	3		T224	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1743	1			T3	1		T5	21		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T145	7		T149	11		T229	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T232	27		T299	10		T307	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T320	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T57	16		T145	11		T199	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	8		T242	17		T203	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T235	2		T174	10		T177	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	9		T46	7		T69	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T222	2		T148	1		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T234	7		T161	8		T162	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	8		T145	4		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T70	4		T199	11		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T156	8		T69	8		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T246	12		T266	7		T267	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T158	4		T230	12		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T229	18		T237	7		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T50	13		T40	20		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	5		T154	10		T245	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	13		T58	12		T44	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T53	4		T69	6		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T272	2		T247	9		T170	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1005	1			T11	9		T49	22		T195	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T57	17		T145	12		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T39	15		T53	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	1		T147	1		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1346	1			T3	1		T5	3		T11	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	1		T59	1		T222	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T146	1		T234	8		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	9		T156	9		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T152	1		T221	1		T70	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T69	9		T41	4		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T12	1		T152	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T59	1		T156	16		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	6		T57	1		T229	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T50	14		T40	26		T149	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T154	11		T69	7		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	14		T58	13		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T53	5		T196	5		T230	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T145	8		T159	2		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T52	1		T196	1		T199	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T153	1		T229	3		T243	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T252	1		T263	19		T321	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16028	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T242	18		T288	1		T264	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T57	16		T145	10		T227	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T39	4		T53	7		T203	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T234	11		T235	15		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1407	1			T5	18		T45	14		T46	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T59	17		T222	15		T145	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T234	6		T32	9		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	6		T156	2		T70	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T70	1		T199	11		T148	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T69	2		T41	1		T227	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T159	13		T224	12		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T59	5		T156	10		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T229	11		T237	7		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	2		T149	17		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T154	7		T69	3		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	14		T58	16		T224	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	13		T196	6		T230	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T145	9		T159	6		T224	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T52	12		T199	10		T171	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T153	9		T229	5		T257	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T252	4		T263	13		T324	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T199	9		T171	10		T227	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T242	9		T296	7		T325	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T145	8		T159	1		T149	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T52	1		T232	29		T252	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T320	10		T293	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T264	1		T304	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T57	17		T145	12		T146	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T53	9		T242	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T147	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T57	1		T39	15		T46	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	1		T59	1		T222	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	1		T147	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	9		T145	5		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T152	1		T221	1		T70	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T156	9		T69	9		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T157	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T59	1		T158	5		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T57	1		T152	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T50	14		T40	26		T156	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	6		T154	11		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	14		T58	13		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	5		T69	7		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T153	1		T159	1		T224	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T3	1		T5	3		T11	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T145	9		T159	4		T229	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T52	12		T252	4		T326	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T320	2		T293	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T57	16		T145	10		T199	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T53	7		T242	9		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T234	11		T235	15		T174	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	4		T46	8		T69	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T59	17		T222	15		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T234	6		T268	5		T252	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	6		T145	2		T269	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T70	1		T199	11		T148	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T156	2		T69	2		T70	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T223	11		T224	12		T250	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T59	5		T230	11		T227	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T159	13		T229	11		T237	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	2		T156	10		T149	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T154	7		T245	2		T161	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	14		T58	16		T44	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T53	13		T69	3		T148	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T153	9		T159	2		T224	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1410	1			T5	18		T45	14		T47	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14