Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21478

1

T1

181

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3489

1

T2

6

T6

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19260

1

T1

181

T2

6

T7

2

auto[1]

5707

1

T2

15

T3

1

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	310	1			T145	22		T28	1		T233	26
values[0]	63	1			T94	17		T300	14		T326	31
values[1]	600	1			T59	18		T148	20		T261	1
values[2]	571	1			T13	28		T222	18		T153	10
values[3]	656	1			T147	1		T41	1		T159	5
values[4]	1034	1			T6	1		T57	33		T39	19
values[5]	2795	1			T3	1		T5	21		T11	10
values[6]	744	1			T2	21		T57	1		T58	29
values[7]	702	1			T7	1		T12	1		T57	1
values[8]	552	1			T59	6		T52	13		T196	1
values[9]	962	1			T7	1		T46	16		T50	14
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	472	1			T157	1		T149	12		T242	27
values[1]	611	1			T13	28		T222	18		T153	10
values[2]	713	1			T6	1		T39	19		T147	1
values[3]	3335	1			T3	1		T5	21		T11	10
values[4]	493	1			T57	1		T58	29		T156	26
values[5]	694	1			T2	21		T7	1		T145	7
values[6]	741	1			T12	1		T57	1		T69	15
values[7]	520	1			T7	1		T59	6		T52	13
values[8]	984	1			T46	16		T50	14		T152	1
values[9]	114	1			T152	1		T199	21		T148	3
minimum	16290	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T157	1		T149	1		T242	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T273	9		T160	1		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	15		T222	16		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T153	10		T70	10		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T231	1		T159	5		T229	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T39	10		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1720	1			T3	1		T5	21		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T57	17		T146	1		T69	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T57	1		T147	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T58	17		T156	11		T199	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	7		T7	1		T70	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T145	3		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T57	1		T196	7		T148	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	1		T69	10		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T59	6		T227	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T52	13		T53	14		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	9		T172	1		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T50	1		T152	1		T145	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T152	1		T203	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T199	10		T148	3		T246	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15914	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T148	5		T261	1		T161	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T149	11		T242	17		T229	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T273	12		T205	3		T331	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	13		T222	2		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T70	6		T44	4		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T231	2		T229	18		T245	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	9		T172	16		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T11	9		T49	22		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T57	16		T69	6		T234	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T165	3		T55	1		T268	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T58	12		T156	15		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	8		T70	4		T199	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	5		T145	4		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T196	4		T148	1		T235	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T69	5		T230	12		T244	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T227	12		T235	13		T273	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T53	4		T234	7		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T46	7		T172	8		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T50	13		T145	11		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T203	4		T192	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T199	11		T246	12		T96	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T57	1		T40	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T148	15		T161	7		T228	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T236	15		T99	19		T319	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T145	11		T28	1		T233	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T300	1		T326	19		T332	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T94	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T59	18		T229	6		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T148	5		T261	1		T273	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	15		T222	16		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T153	10		T70	10		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T159	5		T149	18		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T147	1		T41	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T53	8		T145	10		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	1		T57	17		T39	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T3	1		T5	21		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	1		T159	14		T203	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	7		T57	1		T70	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T58	17		T145	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T57	1		T196	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T69	10		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T59	6		T235	16		T273	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T52	13		T196	1		T224	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T46	9		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T50	1		T53	14		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T236	14		T99	18		T319	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T145	11		T233	12		T246	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T300	13		T326	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T94	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T229	2		T253	11		T246	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T148	15		T273	12		T161	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	13		T222	2		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T70	6		T44	4		T230	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T149	15		T245	16		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T253	10		T236	12		T267	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T53	8		T145	7		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T57	16		T39	9		T69	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T11	9		T49	22		T40	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T203	14		T301	3		T177	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	8		T70	4		T158	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	5		T58	12		T145	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T196	4		T199	9		T148	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T69	5		T230	12		T244	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T235	13		T273	7		T232	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T234	7		T30	2		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T46	7		T203	4		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T50	13		T53	4		T156	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T157	1		T149	12		T242	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T273	13		T160	1		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	14		T222	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T153	1		T70	8		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T231	3		T159	1		T229	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T39	15		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T3	1		T5	3		T11	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T57	17		T146	1		T69	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T57	1		T147	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T58	13		T156	16		T199	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	9		T7	1		T70	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	6		T145	5		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T57	1		T196	5		T148	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	1		T69	6		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	1		T59	1		T227	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T52	1		T53	5		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T46	8		T172	9		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T50	14		T152	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T152	1		T203	5		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T199	12		T148	1		T246	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16019	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T148	16		T261	1		T161	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T242	9		T229	5		T253	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T273	8		T249	6		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	14		T222	15		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T153	9		T70	8		T224	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T159	4		T229	11		T245	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	4		T302	8		T112	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T5	18		T45	14		T47	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T57	16		T69	3		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T165	5		T55	1		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T58	16		T156	10		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	6		T70	1		T199	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	2		T154	7		T69	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T196	6		T148	8		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T69	9		T230	11		T227	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T59	5		T227	11		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T52	12		T53	13		T224	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	8		T16	5		T247	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T145	10		T156	2		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T192	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T199	9		T148	2		T246	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T59	17		T22	2		T333	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T148	4		T161	8		T228	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T236	15		T99	19		T319	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T145	12		T28	1		T233	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T300	14		T326	13		T332	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T94	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T59	1		T229	3		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T148	16		T261	1		T273	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	14		T222	3		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T153	1		T70	8		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T159	1		T149	16		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	1		T41	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T53	9		T145	8		T231	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T6	1		T57	17		T39	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T3	1		T5	3		T11	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	1		T159	1		T203	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T2	9		T57	1		T70	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	6		T58	13		T145	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	1		T57	1		T196	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T69	6		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T59	1		T235	14		T273	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T52	1		T196	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	1		T46	8		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T50	14		T53	5		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T236	14		T99	18		T319	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T145	10		T233	13		T246	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T326	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T59	17		T229	5		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T148	4		T273	8		T161	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	14		T222	15		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T153	9		T70	8		T224	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T159	4		T149	17		T245	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T208	10		T236	10		T302	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T53	7		T145	9		T159	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T57	16		T39	4		T69	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T5	18		T45	14		T47	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T159	13		T203	2		T301	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	6		T70	1		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T58	16		T145	2		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T196	6		T199	10		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T69	9		T234	11		T230	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T59	5		T235	15		T273	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T52	12		T224	7		T234	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	8		T16	5		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T53	13		T156	2		T199	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14