Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21292

1

T1

181

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3675

1

T2

6

T7

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18691

1

T1

180

T2

15

T6

1

auto[1]

6276

1

T1

1

T2

6

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	388	1			T1	1		T8	7		T15	1
values[0]	40	1			T205	8		T334	17		T119	1
values[1]	578	1			T2	6		T153	10		T148	3
values[2]	3010	1			T3	1		T5	21		T11	10
values[3]	661	1			T6	1		T145	7		T147	1
values[4]	612	1			T7	1		T13	28		T57	34
values[5]	639	1			T2	15		T222	18		T147	1
values[6]	763	1			T12	1		T52	13		T152	1
values[7]	785	1			T46	16		T157	1		T159	14
values[8]	602	1			T58	29		T40	28		T152	1
values[9]	1256	1			T7	1		T59	18		T50	14
minimum	15633	1			T1	180		T8	139		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	824	1			T2	6		T39	19		T53	16
values[1]	3035	1			T3	1		T5	21		T11	10
values[2]	493	1			T6	1		T146	1		T147	1
values[3]	704	1			T13	28		T57	34		T59	6
values[4]	788	1			T2	15		T7	1		T12	1
values[5]	571	1			T52	13		T152	1		T147	1
values[6]	759	1			T46	16		T158	5		T159	14
values[7]	757	1			T58	29		T40	28		T152	1
values[8]	884	1			T59	18		T50	14		T156	26
values[9]	162	1			T7	1		T53	18		T160	1
minimum	15990	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	10		T53	8		T153	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	1		T145	10		T199	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T3	1		T5	21		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T57	1		T145	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	1		T146	1		T223	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T147	1		T30	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	15		T57	17		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T57	1		T59	6		T159	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	7		T7	1		T222	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T154	8		T70	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T147	1		T221	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T52	13		T152	1		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T229	12		T253	1		T233	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T46	9		T158	1		T159	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T152	1		T156	3		T69	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T58	17		T40	8		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T50	1		T147	1		T69	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T59	18		T156	11		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T53	14		T160	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T7	1		T162	1		T267	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15831	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T168	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	9		T53	8		T149	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	5		T145	7		T199	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T11	9		T49	22		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T145	4		T148	16		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T203	14		T16	6		T246	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T30	2		T161	7		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	13		T57	16		T172	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T32	6		T273	12		T177	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	8		T222	2		T199	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	10		T70	4		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T245	16		T161	8		T168	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T41	1		T97	8		T104	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T229	18		T253	10		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	7		T158	4		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T156	8		T69	6		T70	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T58	12		T40	20		T196	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T50	13		T69	13		T203	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T156	15		T231	2		T149	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T53	4		T96	2		T322	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T162	7		T267	13		T308	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T57	1		T40	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T168	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T1	1		T8	7		T15	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T236	8		T270	3		T335	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T334	9		T307	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T205	3		T119	1		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T153	10		T28	1		T235	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	1		T148	3		T234	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1634	1			T3	1		T5	21		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T57	1		T145	10		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T221	1		T43	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T145	3		T147	1		T148	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T13	15		T57	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T57	1		T59	6		T159	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	7		T222	16		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T230	13		T17	2		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T221	1		T157	1		T245	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	1		T52	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T157	1		T261	1		T229	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T46	9		T159	14		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	1		T156	3		T253	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T58	17		T40	8		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T50	1		T147	1		T69	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T7	1		T59	18		T156	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15480	1			T1	180		T8	139		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T53	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T270	9		T335	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T334	8		T307	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T205	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T235	9		T266	7		T305	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	5		T234	7		T172	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T11	9		T39	9		T49	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T145	7		T199	11		T148	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T43	2		T16	6		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	4		T148	15		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	13		T57	16		T203	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	2		T32	6		T273	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T2	8		T222	2		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T230	12		T237	7		T272	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T245	16		T227	14		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T154	10		T70	4		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T229	18		T161	8		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	7		T230	12		T246	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T156	8		T253	10		T162	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T58	12		T40	20		T158	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T50	13		T69	19		T70	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T156	15		T196	4		T231	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T39	15		T53	9		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	6		T145	8		T199	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T3	1		T5	3		T11	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T57	1		T145	5		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	1		T146	1		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T147	1		T30	3		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	14		T57	17		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T57	1		T59	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	9		T7	1		T222	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T154	11		T70	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T147	1		T221	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T52	1		T152	1		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T229	19		T253	11		T233	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T46	8		T158	5		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T152	1		T156	9		T69	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T58	13		T40	26		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T50	14		T147	1		T69	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T59	1		T156	16		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T53	5		T160	1		T96	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T7	1		T162	8		T267	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15984	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T168	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	4		T53	7		T153	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T145	9		T199	9		T148	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T5	18		T45	14		T47	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T145	2		T148	12		T224	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T223	11		T203	2		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T161	8		T246	16		T55	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	14		T57	16		T224	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T59	5		T159	2		T32	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	6		T222	15		T199	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T154	7		T70	1		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T245	2		T174	29		T204	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T52	12		T41	1		T159	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T229	11		T233	14		T254	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T46	8		T159	13		T224	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T156	2		T69	3		T70	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T58	16		T40	2		T196	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T69	11		T233	13		T247	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T59	17		T156	10		T70	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T53	13		T322	8		T193	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T308	11		T309	9		T322	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T104	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T1	1		T8	7		T15	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T236	1		T270	10		T335	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T334	9		T307	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T205	6		T119	1		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T153	1		T28	1		T235	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	6		T148	1		T234	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T3	1		T5	3		T11	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T57	1		T145	8		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	1		T221	1		T43	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T145	5		T147	1		T148	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T13	14		T57	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T57	1		T59	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	9		T222	3		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T230	13		T17	2		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T221	1		T157	1		T245	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	1		T52	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T157	1		T261	1		T229	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	8		T159	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	1		T156	9		T253	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T58	13		T40	26		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T50	14		T147	1		T69	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T7	1		T59	1		T156	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15633	1			T1	180		T8	139		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T53	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T236	7		T270	2		T335	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T334	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T153	9		T235	25		T266	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T148	2		T234	6		T235	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T5	18		T39	4		T45	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T145	9		T199	9		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T16	5		T246	11		T268	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T145	2		T148	4		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	14		T57	16		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T59	5		T159	2		T32	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	6		T222	15		T199	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T230	12		T237	7		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T245	2		T227	15		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T52	12		T154	7		T70	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T229	11		T233	14		T174	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T46	8		T159	13		T234	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T156	2		T247	9		T265	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T58	16		T40	2		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T69	14		T70	2		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T59	17		T156	10		T70	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14