Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21226

1

T1

181

T3

1

T5

21

auto[ADC_CTRL_FILTER_COND_OUT]

3741

1

T2

21

T6

1

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19111

1

T1

181

T2

6

T6

1

auto[1]

5856

1

T2

15

T3

1

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T145	17		T196	11		T62	1
values[0]	42	1			T285	1		T56	5		T179	5
values[1]	770	1			T2	15		T13	28		T57	1
values[2]	2839	1			T3	1		T5	21		T7	1
values[3]	761	1			T12	1		T57	33		T39	19
values[4]	503	1			T2	6		T6	1		T53	18
values[5]	799	1			T57	1		T159	5		T149	13
values[6]	703	1			T152	1		T69	15		T157	1
values[7]	606	1			T52	13		T156	11		T146	1
values[8]	790	1			T59	18		T222	18		T152	1
values[9]	926	1			T7	1		T53	16		T145	22
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	689	1			T7	1		T13	28		T57	1
values[1]	2772	1			T3	1		T5	21		T11	10
values[2]	784	1			T12	1		T57	33		T39	19
values[3]	555	1			T2	6		T6	1		T53	18
values[4]	822	1			T57	1		T152	1		T69	15
values[5]	628	1			T157	1		T70	6		T148	10
values[6]	675	1			T52	13		T156	11		T146	1
values[7]	799	1			T59	18		T222	18		T152	1
values[8]	856	1			T7	1		T53	16		T145	39
values[9]	99	1			T196	11		T165	2		T168	3
minimum	16288	1			T1	181		T2	15		T8	146

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T13	15		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T58	17		T199	11		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T3	1		T5	21		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T147	1		T69	3		T234	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T50	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T57	17		T39	10		T156	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T53	14		T159	5		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T6	1		T149	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T57	1		T152	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T69	10		T149	1		T224	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T148	9		T172	1		T340	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T157	1		T70	2		T234	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T146	1		T157	1		T70	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T52	13		T156	3		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T222	16		T152	1		T69	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T59	18		T203	3		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T146	2		T172	1		T151	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	1		T53	8		T145	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T191	1		T109	9		T275	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T196	7		T165	1		T168	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15899	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T2	7		T154	8		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	13		T145	4		T227	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T58	12		T199	9		T231	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	894	1			T11	9		T49	22		T195	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T69	8		T234	6		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T50	13		T40	20		T151	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T57	16		T39	9		T156	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T53	4		T227	12		T253	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	5		T149	15		T44	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T242	17		T229	18		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T69	5		T149	11		T234	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T148	1		T172	8		T162	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T70	4		T273	12		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T70	6		T148	15		T174	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T156	8		T199	11		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T222	2		T69	6		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T203	14		T172	8		T246	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T172	16		T151	13		T235	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	8		T145	18		T245	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T191	11		T109	2		T275	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T196	4		T165	1		T168	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T57	1		T46	7		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T2	8		T154	10		T295	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T233	14		T232	1		T268	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T145	10		T196	7		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T56	4		T179	1		T276	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T285	1		T270	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	15		T57	1		T46	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	7		T58	17		T154	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T3	1		T5	21		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T147	1		T69	3		T224	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T50	1		T40	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T57	17		T39	10		T156	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	14		T153	10		T151	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T6	1		T149	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	1		T159	5		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T149	1		T224	16		T234	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T152	1		T242	10		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T69	10		T157	1		T70	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T146	1		T157	1		T70	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T52	13		T156	3		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T222	16		T152	1		T69	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T59	18		T41	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T146	2		T41	4		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T7	1		T53	8		T145	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T233	12		T232	12		T268	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T145	7		T196	4		T30	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T56	1		T179	4		T276	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T270	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	13		T46	7		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	8		T58	12		T154	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T11	9		T49	22		T145	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T69	8		T230	24		T232	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	13		T40	20		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T57	16		T39	9		T156	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T53	4		T151	4		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	5		T149	15		T16	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T229	18		T237	7		T253	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T149	11		T234	7		T44	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T242	17		T172	8		T162	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T69	5		T70	4		T273	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T70	6		T148	16		T97	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T156	8		T199	11		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T222	2		T69	6		T158	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T246	12		T232	8		T247	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T41	1		T43	2		T172	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T53	8		T145	11		T203	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	1		T13	14		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T58	13		T199	10		T231	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T3	1		T5	3		T11	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T147	1		T69	9		T234	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	1		T50	14		T40	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T57	17		T39	15		T156	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T53	5		T159	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	6		T6	1		T149	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T57	1		T152	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T69	6		T149	12		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T148	2		T172	9		T340	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T157	1		T70	5		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T146	1		T157	1		T70	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T52	1		T156	9		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T222	3		T152	1		T69	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T59	1		T203	15		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T146	2		T172	17		T151	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	1		T53	9		T145	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T191	12		T109	3		T275	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T196	5		T165	2		T168	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16089	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	9		T154	11		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	14		T145	2		T224	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	16		T199	10		T224	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T5	18		T59	5		T45	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T69	2		T234	7		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	2		T153	9		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T57	16		T39	4		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T53	13		T159	4		T227	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T149	17		T44	3		T16	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T242	9		T229	11		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T69	9		T224	15		T234	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T148	8		T252	4		T280	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T70	1		T234	11		T189	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	2		T148	4		T174	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T52	12		T156	2		T199	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T222	15		T69	3		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T59	17		T203	2		T246	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T151	14		T235	10		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T53	7		T145	19		T250	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T109	8		T275	12		T293	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T196	6		T277	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T46	8		T70	6		T229	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T2	6		T154	7		T295	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T233	13		T232	13		T268	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T145	8		T196	5		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T56	3		T179	5		T276	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T285	1		T270	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	14		T57	1		T46	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	9		T58	13		T154	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T3	1		T5	3		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	1		T69	9		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T50	14		T40	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T57	17		T39	15		T156	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T53	5		T153	1		T151	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	6		T6	1		T149	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T57	1		T159	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T149	12		T224	1		T234	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T152	1		T242	18		T172	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T69	6		T157	1		T70	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T146	1		T157	1		T70	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T52	1		T156	9		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T222	3		T152	1		T69	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T59	1		T41	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T146	2		T41	4		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	1		T53	9		T145	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T233	13		T268	3		T255	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T145	9		T196	6		T92	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T56	2		T276	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T270	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	14		T46	8		T70	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	6		T58	16		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T5	18		T59	5		T45	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T69	2		T224	12		T230	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T40	2		T159	13		T246	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T57	16		T39	4		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T53	13		T153	9		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	17		T16	5		T235	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T159	4		T229	11		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T224	15		T234	6		T44	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T242	9		T252	4		T280	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T69	9		T70	1		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T70	2		T148	12		T204	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T52	12		T156	2		T199	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T222	15		T69	3		T223	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T59	17		T246	16		T247	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T41	1		T151	14		T235	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T53	7		T145	10		T203	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14