Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	1		T57	17		T145	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T39	15		T53	9		T203	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	1		T147	2		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1378	1			T3	1		T5	3		T11	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T59	1		T222	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	1		T234	8		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	9		T156	9		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T152	1		T221	1		T70	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T69	9		T41	4		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	1		T57	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T59	1		T156	16		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	6		T152	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	14		T40	26		T149	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T154	11		T69	7		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	14		T58	13		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T53	5		T230	13		T244	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T145	8		T159	2		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T52	1		T196	6		T199	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T153	1		T243	7		T162	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T262	7		T252	1		T263	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T242	18		T264	1		T260	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T57	16		T145	10		T199	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	4		T53	7		T203	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T234	11		T235	15		T233	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1412	1			T5	18		T45	14		T46	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T59	17		T222	15		T145	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T234	6		T32	9		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	6		T156	2		T70	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T70	1		T199	11		T148	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T69	2		T41	1		T227	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T250	10		T246	16		T236	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T59	5		T156	10		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T159	13		T224	12		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T40	2		T149	17		T44	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T154	7		T69	3		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	14		T58	16		T224	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T53	13		T230	12		T233	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T145	9		T159	6		T224	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T52	12		T196	6		T199	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T153	9		T255	21		T257	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T262	6		T252	4		T263	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T242	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T256	13		T257	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T258	10		T259	9		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T57	17		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	9		T242	18		T203	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	1		T147	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T57	1		T39	15		T46	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T7	1		T59	1		T222	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	1		T69	6		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	9		T145	5		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T152	1		T221	1		T70	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T156	9		T69	9		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T157	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T59	1		T158	5		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T57	1		T152	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T50	14		T40	26		T156	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	6		T154	11		T69	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	14		T58	13		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	5		T148	1		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T145	8		T153	1		T159	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1410	1			T3	1		T5	3		T11	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T256	12		T257	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T259	19		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T57	16		T145	10		T199	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T53	7		T242	9		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T234	11		T235	15		T174	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	4		T46	8		T70	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T59	17		T222	15		T148	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T69	9		T234	6		T268	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	6		T145	2		T269	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T70	1		T199	11		T148	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T156	2		T69	2		T70	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T223	11		T250	10		T246	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T59	5		T230	11		T227	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T159	13		T224	12		T237	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	2		T156	10		T149	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T154	7		T69	3		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	14		T58	16		T44	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	13		T148	2		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T145	9		T153	9		T159	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1441	1			T5	18		T45	14		T47	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14