Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21180

1

T1

181

T2

6

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3787

1

T2

15

T12

1

T13

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19405

1

T1

181

T2

15

T6

1

auto[1]

5562

1

T2

6

T3

1

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	226	1			T39	19		T223	12		T43	4
values[0]	1	1			T54	1		-	-		-	-
values[1]	767	1			T145	46		T147	1		T221	1
values[2]	894	1			T2	15		T152	1		T69	15
values[3]	616	1			T6	1		T222	18		T147	1
values[4]	706	1			T46	16		T53	18		T156	37
values[5]	597	1			T7	1		T53	16		T153	10
values[6]	841	1			T57	34		T59	18		T146	1
values[7]	658	1			T13	28		T58	29		T69	11
values[8]	2801	1			T3	1		T5	21		T7	1
values[9]	882	1			T2	6		T12	1		T59	6
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T152	1		T145	17		T147	1
values[1]	742	1			T2	15		T69	15		T157	1
values[2]	770	1			T6	1		T46	16		T53	18
values[3]	585	1			T7	1		T156	37		T147	1
values[4]	664	1			T53	16		T146	1		T153	10
values[5]	777	1			T57	34		T59	18		T221	1
values[6]	2974	1			T3	1		T5	21		T11	10
values[7]	552	1			T7	1		T59	6		T40	28
values[8]	767	1			T2	6		T12	1		T57	1
values[9]	145	1			T242	27		T151	7		T16	13
minimum	16268	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T70	2		T164	1		T245	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T152	1		T145	10		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T69	10		T157	1		T148	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	7		T196	1		T199	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	1		T46	9		T53	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T147	1		T148	5		T261	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T156	14		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	1		T159	14		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T53	8		T148	3		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T146	1		T153	10		T171	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T57	1		T157	1		T189	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T57	17		T59	18		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T3	1		T5	21		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	15		T58	17		T70	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T59	6		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	8		T151	15		T227	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	1		T57	1		T39	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T152	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T98	18		T109	3		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T242	10		T151	3		T16	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15891	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T159	3		T150	1		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T70	4		T245	16		T168	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T145	7		T172	8		T253	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T69	5		T148	1		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	8		T199	9		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T46	7		T53	4		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T148	15		T234	6		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T156	23		T199	11		T231	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T158	4		T172	16		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T53	8		T230	12		T273	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T44	4		T253	14		T246	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T228	2		T36	2		T55	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T57	16		T244	16		T161	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T11	9		T49	22		T69	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	13		T58	12		T199	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T30	11		T94	13		T179	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	20		T151	13		T227	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	5		T39	9		T50	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T70	6		T149	11		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T109	6		T185	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T242	17		T151	4		T16	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T57	1		T40	1		T145	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T229	18		T279	8		T205	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T39	10		T43	2		T234	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T223	12		T151	3		T272	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T54	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T145	14		T196	7		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T145	10		T147	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T69	10		T157	1		T70	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	7		T152	1		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T6	1		T222	16		T154	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T147	1		T199	11		T148	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T46	9		T53	14		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T159	14		T149	1		T224	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T53	8		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T153	10		T158	1		T171	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T57	1		T157	1		T148	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T57	17		T59	18		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T69	3		T30	1		T32	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	15		T58	17		T70	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T3	1		T5	21		T7	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	8		T151	15		T227	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T59	6		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	1		T152	1		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T39	9		T43	2		T234	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T151	4		T272	2		T247	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	15		T196	4		T245	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T145	7		T229	18		T253	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T69	5		T70	4		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	8		T172	8		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T222	2		T154	10		T69	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T199	9		T148	15		T203	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T46	7		T53	4		T156	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T234	6		T237	7		T268	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T53	8		T203	4		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T158	4		T172	16		T253	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T36	2		T55	1		T262	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T57	16		T44	4		T244	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T69	8		T30	2		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	13		T58	12		T199	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T11	9		T49	22		T195	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	20		T151	13		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	5		T50	13		T29	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T70	6		T149	11		T242	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T70	5		T164	1		T245	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T152	1		T145	8		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T69	6		T157	1		T148	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	9		T196	1		T199	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T46	8		T53	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T147	1		T148	16		T261	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T156	25		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T158	5		T159	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T53	9		T148	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T146	1		T153	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T57	1		T157	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T57	17		T59	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T3	1		T5	3		T11	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	14		T58	13		T70	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T7	1		T59	1		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	26		T151	14		T227	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	6		T57	1		T39	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	1		T152	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T98	1		T109	7		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T242	18		T151	5		T16	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16038	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T159	1		T150	1		T250	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	1		T245	2		T280	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T145	9		T253	8		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T69	9		T148	8		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	6		T199	10		T235	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	8		T53	13		T222	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	4		T234	18		T203	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T156	12		T199	9		T149	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T159	13		T224	15		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T53	7		T148	2		T230	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T153	9		T171	8		T44	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T189	3		T228	15		T55	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T57	16		T59	17		T161	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T5	18		T45	14		T47	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	14		T58	16		T70	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T59	5		T159	4		T269	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	2		T151	14		T227	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	4		T52	12		T224	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T70	2		T223	11		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T98	17		T109	2		T185	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T242	9		T151	2		T16	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T145	12		T196	6		T209	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T159	2		T250	10		T229	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T39	15		T43	4		T234	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T223	1		T151	5		T272	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T54	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T145	17		T196	5		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T145	8		T147	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T69	6		T157	1		T70	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	9		T152	1		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	1		T222	3		T154	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T147	1		T199	10		T148	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T46	8		T53	5		T156	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T159	1		T149	1		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T53	9		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T153	1		T158	5		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T57	1		T157	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T57	17		T59	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T69	9		T30	3		T32	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	14		T58	13		T70	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T3	1		T5	3		T7	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T40	26		T151	14		T227	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	6		T59	1		T50	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T12	1		T152	1		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T39	4		T234	6		T98	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T223	11		T151	2		T247	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	12		T196	6		T245	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T145	9		T159	2		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T69	9		T70	1		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	6		T235	15		T165	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T222	15		T154	7		T69	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T199	10		T148	4		T234	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	8		T53	13		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T159	13		T224	15		T234	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	7		T230	12		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T153	9		T171	8		T253	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T148	2		T55	1		T262	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T57	16		T59	17		T44	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T69	2		T32	9		T189	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	14		T58	16		T70	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T5	18		T45	14		T47	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	2		T151	14		T227	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T59	5		T52	12		T159	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T70	2		T224	12		T242	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14