Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21549

1

T1

181

T3

1

T5

21

auto[ADC_CTRL_FILTER_COND_OUT]

3418

1

T2

21

T7

1

T57

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18988

1

T1

181

T2

21

T6

1

auto[1]

5979

1

T3

1

T5

21

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	29	1			T41	1		T230	24		T96	3
values[0]	81	1			T56	5		T266	21		T177	7
values[1]	870	1			T6	1		T59	18		T50	14
values[2]	779	1			T7	1		T145	22		T221	1
values[3]	618	1			T145	7		T221	1		T154	18
values[4]	526	1			T39	19		T52	13		T40	28
values[5]	636	1			T12	1		T222	18		T146	1
values[6]	813	1			T7	1		T57	34		T53	18
values[7]	631	1			T57	1		T58	29		T156	37
values[8]	557	1			T13	28		T152	1		T69	15
values[9]	3449	1			T2	21		T3	1		T5	21
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1083	1			T59	18		T50	14		T199	20
values[1]	703	1			T6	1		T7	1		T145	22
values[2]	628	1			T52	13		T145	7		T154	18
values[3]	603	1			T39	19		T40	28		T153	10
values[4]	754	1			T12	1		T222	18		T146	2
values[5]	677	1			T7	1		T57	34		T58	29
values[6]	2895	1			T3	1		T5	21		T11	10
values[7]	536	1			T2	6		T152	1		T147	1
values[8]	853	1			T2	15		T46	16		T53	16
values[9]	245	1			T59	6		T152	1		T146	1
minimum	15990	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T59	18		T148	9		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T50	1		T199	11		T148	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	1		T7	1		T221	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	11		T69	3		T70	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T52	13		T154	8		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T145	3		T44	1		T253	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	10		T157	2		T229	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	8		T153	10		T159	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T12	1		T146	2		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T222	16		T70	7		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T57	17		T53	14		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	1		T57	1		T58	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T3	1		T5	21		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T57	1		T43	2		T224	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T152	1		T199	12		T159	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	1		T147	1		T69	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T145	10		T196	7		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	7		T46	9		T53	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T152	1		T146	1		T224	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T59	6		T160	1		T104	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15833	1			T1	181		T8	146		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T148	1		T231	2		T242	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T50	13		T199	9		T148	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T172	16		T165	3		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T145	11		T69	8		T70	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T154	10		T158	4		T203	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T145	4		T253	10		T161	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	9		T229	2		T233	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	20		T149	15		T245	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T41	1		T30	2		T227	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T222	2		T149	11		T16	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T57	16		T53	4		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T58	12		T234	7		T273	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T11	9		T13	13		T49	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	2		T233	12		T247	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T199	11		T229	18		T30	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	5		T69	5		T151	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T145	7		T196	4		T172	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	8		T46	7		T53	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T235	2		T178	9		T281	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T104	3		T282	14		T239	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T57	1		T40	1		T41	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T96	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T41	1		T230	12		T206	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T56	4		T266	14		T177	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	10		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T59	18		T148	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T50	1		T199	11		T223	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	1		T221	1		T44	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T145	11		T69	3		T70	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T221	1		T154	8		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	3		T159	5		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	10		T52	13		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	8		T153	10		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T12	1		T146	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T222	16		T70	7		T149	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T57	17		T53	14		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	1		T57	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T156	14		T147	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T57	1		T58	17		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	15		T152	1		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T69	10		T224	8		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T3	1		T5	21		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T2	8		T59	6		T46	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T96	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T230	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T56	1		T266	7		T177	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T284	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T148	1		T231	2		T242	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T50	13		T199	9		T203	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T44	4		T172	16		T165	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T145	11		T69	8		T70	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T154	10		T158	4		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T145	4		T253	10		T161	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	9		T228	2		T233	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	20		T94	13		T18	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T41	1		T30	2		T246	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T222	2		T149	26		T245	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T57	16		T53	4		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T273	12		T232	15		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T156	23		T286	2		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T58	12		T43	2		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	13		T199	11		T229	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T69	5		T161	8		T247	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T11	9		T49	22		T145	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T2	13		T46	7		T53	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T59	1		T148	2		T231	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T50	14		T199	10		T148	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T7	1		T221	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T145	12		T69	9		T70	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T52	1		T154	11		T158	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T145	5		T44	1		T253	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	15		T157	2		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	26		T153	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T146	2		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T222	3		T70	1		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T57	17		T53	5		T172	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	1		T57	1		T58	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T3	1		T5	3		T11	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T57	1		T43	4		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T152	1		T199	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	6		T147	1		T69	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T145	8		T196	5		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T2	9		T46	8		T53	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T152	1		T146	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T59	1		T160	1		T104	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15988	1			T1	181		T8	146		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T59	17		T148	8		T242	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T199	10		T148	4		T223	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T165	5		T228	2		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T145	10		T69	2		T70	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T52	12		T154	7		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T145	2		T161	8		T20	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T39	4		T229	5		T233	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T40	2		T153	9		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T41	1		T171	8		T227	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T222	15		T70	6		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T57	16		T53	13		T32	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T58	16		T224	12		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T5	18		T13	14		T45	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T224	7		T234	11		T189	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T199	11		T159	2		T229	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T69	9		T151	14		T209	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T145	9		T196	6		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	6		T46	8		T53	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T224	15		T235	15		T178	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T59	5		T104	3		T239	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T35	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T96	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T41	1		T230	13		T206	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T56	3		T266	8		T177	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	1		T284	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T6	1		T59	1		T148	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	14		T199	10		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T221	1		T44	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T145	12		T69	9		T70	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T221	1		T154	11		T158	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	5		T159	1		T253	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T39	15		T52	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	26		T153	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	1		T146	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T222	3		T70	1		T149	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T57	17		T53	5		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	1		T57	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T156	25		T147	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T57	1		T58	13		T43	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	14		T152	1		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T69	6		T224	1		T161	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T3	1		T5	3		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	438	1			T2	15		T59	1		T46	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T230	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T56	2		T266	13		T177	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T283	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T59	17		T148	8		T242	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T199	10		T223	11		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T44	3		T165	5		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T145	10		T69	2		T70	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T154	7		T159	13		T229	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T145	2		T159	4		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T39	4		T52	12		T171	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T40	2		T153	9		T18	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T41	1		T246	16		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T222	15		T70	6		T149	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T57	16		T53	13		T234	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T224	12		T273	8		T174	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T156	12		T170	2		T280	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T58	16		T234	17		T189	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	14		T199	11		T159	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T69	9		T224	7		T247	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T5	18		T45	14		T47	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T2	6		T59	5		T46	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14