Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21494

1

T1

181

T3

1

T5

21

auto[ADC_CTRL_FILTER_COND_OUT]

3473

1

T2

21

T7

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18877

1

T1

181

T2

21

T6

1

auto[1]

6090

1

T3

1

T5

21

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	278	1			T2	15		T53	16		T145	17
values[0]	58	1			T269	24		T266	21		T258	10
values[1]	863	1			T6	1		T59	18		T50	14
values[2]	737	1			T7	1		T145	22		T221	1
values[3]	642	1			T145	7		T221	1		T154	18
values[4]	609	1			T39	19		T52	13		T40	28
values[5]	601	1			T12	1		T222	18		T146	1
values[6]	806	1			T7	1		T57	34		T53	18
values[7]	633	1			T57	1		T58	29		T156	37
values[8]	549	1			T13	28		T152	1		T147	1
values[9]	3213	1			T2	6		T3	1		T5	21
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	906	1			T6	1		T59	18		T199	20
values[1]	687	1			T7	1		T145	22		T221	2
values[2]	591	1			T52	13		T145	7		T154	18
values[3]	630	1			T39	19		T40	28		T153	10
values[4]	765	1			T12	1		T222	18		T146	2
values[5]	649	1			T7	1		T57	34		T58	29
values[6]	2905	1			T3	1		T5	21		T11	10
values[7]	524	1			T2	6		T152	1		T147	1
values[8]	939	1			T2	15		T59	6		T46	16
values[9]	184	1			T152	1		T146	1		T224	16
minimum	16187	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	1		T59	18		T148	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T199	11		T148	5		T223	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T221	2		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T145	11		T69	3		T70	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T52	13		T154	8		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T145	3		T44	1		T253	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	10		T157	2		T229	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	8		T153	10		T159	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T146	2		T147	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	1		T222	16		T70	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T57	17		T53	14		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T57	1		T58	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T3	1		T5	21		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T57	1		T43	2		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	1		T159	3		T229	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	1		T147	1		T69	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	9		T145	10		T196	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T2	7		T59	6		T53	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T152	1		T146	1		T224	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T118	5		T206	1		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15901	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T50	1		T288	1		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T148	1		T231	2		T253	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T199	9		T148	15		T203	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T172	16		T165	3		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	11		T69	8		T70	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T154	10		T158	4		T203	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T145	4		T253	10		T161	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	9		T229	2		T233	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	20		T149	15		T245	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T41	1		T30	2		T227	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T222	2		T149	11		T16	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T57	16		T53	4		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T58	12		T234	7		T273	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T11	9		T13	13		T49	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T43	2		T233	12		T247	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T229	18		T30	11		T244	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	5		T69	5		T199	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	7		T145	7		T196	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	8		T53	8		T69	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T235	2		T178	9		T226	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T118	12		T282	14		T290	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T57	1		T40	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T50	13		T106	5		T259	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T145	10		T224	16		T236	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	7		T53	8		T199	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T269	24		T266	14		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	1		T59	18		T148	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	1		T199	11		T223	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T221	1		T165	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T145	11		T69	3		T70	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T221	1		T154	8		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	3		T161	9		T246	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	10		T52	13		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	8		T153	10		T159	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T146	1		T147	1		T157	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T222	16		T70	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T57	17		T53	14		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T57	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T156	14		T147	1		T224	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T57	1		T58	17		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	15		T152	1		T159	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T147	1		T199	12		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T3	1		T5	21		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T2	1		T59	6		T69	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T145	7		T96	2		T291	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	8		T53	8		T199	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T266	7		T258	9		T23	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T148	1		T231	2		T242	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T50	13		T199	9		T203	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T165	3		T228	10		T272	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	11		T69	8		T70	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T154	10		T158	4		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	4		T161	7		T246	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	9		T229	2		T233	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	20		T149	15		T253	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T41	1		T30	2		T246	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T222	2		T149	11		T245	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T57	16		T53	4		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T273	12		T232	15		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T156	23		T32	6		T286	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T58	12		T43	2		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	13		T229	18		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T199	11		T161	8		T247	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T11	9		T46	7		T49	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	5		T69	11		T151	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	1		T59	1		T148	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T199	10		T148	16		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	1		T221	2		T172	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T145	12		T69	9		T70	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	1		T154	11		T158	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T145	5		T44	1		T253	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T39	15		T157	2		T229	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T40	26		T153	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T146	2		T147	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T222	3		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T57	17		T53	5		T172	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T57	1		T58	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T3	1		T5	3		T11	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T57	1		T43	4		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T152	1		T159	1		T229	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	6		T147	1		T69	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T46	8		T145	8		T196	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T2	9		T59	1		T53	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T152	1		T146	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T118	13		T206	1		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16055	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T50	14		T288	1		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T59	17		T148	8		T253	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T199	10		T148	4		T223	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T165	5		T228	2		T247	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T145	10		T69	2		T70	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T52	12		T154	7		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T145	2		T161	8		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	4		T229	5		T233	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T40	2		T153	9		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T41	1		T171	8		T227	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T222	15		T70	6		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T57	16		T53	13		T32	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T58	16		T224	12		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T5	18		T13	14		T45	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T234	11		T233	13		T247	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T159	2		T229	11		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T69	9		T199	11		T189	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	8		T145	9		T196	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	6		T59	5		T53	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T224	15		T235	15		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T118	4		T292	8		T293	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T242	9		T253	5		T269	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T169	6		T106	2		T294	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T145	8		T224	1		T236	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	9		T53	9		T199	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T269	1		T266	8		T258	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T6	1		T59	1		T148	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	14		T199	10		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T221	1		T165	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T145	12		T69	9		T70	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T221	1		T154	11		T158	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	5		T161	8		T246	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T39	15		T52	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	26		T153	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T146	1		T147	1		T157	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T222	3		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T57	17		T53	5		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T57	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T156	25		T147	1		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T57	1		T58	13		T43	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	14		T152	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	1		T199	12		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T3	1		T5	3		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T2	6		T59	1		T69	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T145	9		T224	15		T236	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T2	6		T53	7		T199	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T269	23		T266	13		T23	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T59	17		T148	8		T242	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T199	10		T223	11		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T165	5		T228	2		T247	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T145	10		T69	2		T70	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T154	7		T159	13		T44	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T145	2		T161	8		T246	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	4		T52	12		T229	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	2		T153	9		T159	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	1		T171	8		T246	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T222	15		T70	6		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T57	16		T53	13		T234	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T224	12		T273	8		T174	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T156	12		T224	7		T32	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T58	16		T234	17		T233	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	14		T159	2		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T199	11		T189	10		T247	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T5	18		T45	14		T46	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T59	5		T69	12		T151	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14