Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21464

1

T1

181

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3503

1

T2

6

T6

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19260

1

T1

181

T2

6

T7

2

auto[1]

5707

1

T2

15

T3

1

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T203	5		T295	2		T296	12
values[0]	63	1			T59	18		T261	1		T289	1
values[1]	603	1			T148	20		T229	8		T273	21
values[2]	598	1			T13	28		T222	18		T153	10
values[3]	634	1			T6	1		T147	2		T41	1
values[4]	1010	1			T57	33		T39	19		T145	17
values[5]	2878	1			T2	15		T3	1		T5	21
values[6]	684	1			T2	6		T57	1		T58	29
values[7]	726	1			T7	1		T12	1		T57	1
values[8]	541	1			T59	6		T196	1		T234	14
values[9]	1232	1			T7	1		T46	16		T50	14
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	823	1			T59	18		T157	1		T148	20
values[1]	561	1			T13	28		T222	18		T153	10
values[2]	776	1			T6	1		T39	19		T147	1
values[3]	3248	1			T3	1		T5	21		T11	10
values[4]	513	1			T57	1		T58	29		T156	26
values[5]	740	1			T2	21		T145	7		T146	1
values[6]	706	1			T7	1		T12	1		T57	1
values[7]	503	1			T7	1		T59	6		T52	13
values[8]	975	1			T46	16		T50	14		T152	1
values[9]	139	1			T152	1		T199	21		T148	3
minimum	15983	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T59	18		T157	1		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T148	5		T224	13		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	15		T222	16		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T153	10		T70	10		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T231	1		T159	5		T229	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	1		T39	10		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T3	1		T5	21		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T57	17		T146	1		T69	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T57	1		T147	1		T70	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T58	17		T156	11		T203	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	7		T199	11		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T145	3		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T57	1		T196	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	1		T69	10		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	1		T59	6		T227	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T52	13		T53	14		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T46	9		T172	1		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T50	1		T152	1		T145	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T152	1		T203	1		T177	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T199	10		T148	3		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T297	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T149	11		T242	17		T229	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T148	15		T273	12		T161	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	13		T222	2		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T70	6		T44	4		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T231	2		T229	18		T245	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	9		T172	16		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T11	9		T49	22		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T57	16		T69	6		T234	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T70	4		T165	3		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T58	12		T156	15		T203	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	8		T199	9		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	5		T145	4		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T196	4		T148	1		T235	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T69	5		T230	12		T244	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T227	12		T235	13		T273	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T53	4		T234	7		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T46	7		T172	8		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T50	13		T145	11		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T203	4		T177	1		T192	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T199	11		T246	12		T170	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T297	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T203	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T295	1		T296	12		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T59	18		T299	1		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T261	1		T289	1		T94	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T229	6		T253	9		T247	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T148	5		T273	9		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	15		T222	16		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T153	10		T70	10		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T147	1		T159	5		T149	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T147	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T145	10		T147	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T57	17		T39	10		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T2	7		T3	1		T5	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T146	1		T69	4		T159	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T57	1		T70	2		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T58	17		T145	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T57	1		T196	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T52	13		T69	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T59	6		T235	16		T273	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T196	1		T234	7		T171	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T7	1		T46	9		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T50	1		T53	14		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T203	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T299	10		T300	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T94	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T229	2		T253	11		T247	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T148	15		T273	12		T161	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	13		T222	2		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T70	6		T44	4		T230	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T149	15		T172	8		T245	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T234	6		T253	10		T236	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T145	7		T231	2		T229	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T57	16		T39	9		T172	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T2	8		T11	9		T49	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T69	6		T203	14		T301	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	4		T158	4		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	5		T58	12		T145	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T196	4		T199	9		T148	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T69	5		T230	12		T244	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T235	13		T273	7		T232	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T234	7		T30	2		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T46	7		T172	8		T16	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T50	13		T53	4		T145	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T59	1		T157	1		T149	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T148	16		T224	1		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	14		T222	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T153	1		T70	8		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T231	3		T159	1		T229	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	1		T39	15		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T3	1		T5	3		T11	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T57	17		T146	1		T69	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T57	1		T147	1		T70	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T58	13		T156	16		T203	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	9		T199	10		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	6		T145	5		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T57	1		T196	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T69	6		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	1		T59	1		T227	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T52	1		T53	5		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T46	8		T172	9		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T50	14		T152	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T152	1		T203	5		T177	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T199	12		T148	1		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T297	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T59	17		T242	9		T229	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T148	4		T224	12		T273	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	14		T222	15		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T153	9		T70	8		T44	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T159	4		T229	11		T245	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	4		T255	21		T302	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T5	18		T45	14		T47	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T57	16		T69	3		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T70	1		T165	5		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T58	16		T156	10		T203	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	6		T199	10		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T145	2		T154	7		T69	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T196	6		T148	8		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T69	9		T230	11		T227	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T59	5		T227	11		T235	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T52	12		T53	13		T224	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T46	8		T16	5		T266	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T145	10		T156	2		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T192	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T199	9		T148	2		T246	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T297	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T203	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T295	2		T296	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T59	1		T299	11		T300	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T261	1		T289	1		T94	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T229	3		T253	12		T247	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T148	16		T273	13		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	14		T222	3		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T153	1		T70	8		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T147	1		T159	1		T149	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T147	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T145	8		T147	1		T231	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T57	17		T39	15		T172	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T2	9		T3	1		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	1		T69	7		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T57	1		T70	5		T158	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	6		T58	13		T145	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T57	1		T196	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T52	1		T69	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T59	1		T235	14		T273	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T196	1		T234	8		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T7	1		T46	8		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T50	14		T53	5		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T296	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T59	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T229	5		T253	8		T247	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T148	4		T273	8		T161	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	14		T222	15		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T153	9		T70	8		T224	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T159	4		T149	17		T245	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T234	7		T208	10		T236	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T145	9		T159	2		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T57	16		T39	4		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	6		T5	18		T45	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T69	3		T159	13		T203	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T70	1		T151	14		T165	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T58	16		T145	2		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T196	6		T199	10		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T52	12		T69	9		T234	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T59	5		T235	15		T273	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T234	6		T171	8		T227	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T46	8		T16	5		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T53	13		T145	10		T156	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14