Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21533

1

T1

181

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3434

1

T2

6

T7

2

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18958

1

T1

180

T2

15

T6

1

auto[1]

6009

1

T1

1

T2

6

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	636	1			T1	1		T7	1		T8	7
values[0]	10	1			T205	8		T119	1		T303	1
values[1]	663	1			T2	6		T153	10		T234	14
values[2]	2969	1			T3	1		T5	21		T11	10
values[3]	650	1			T6	1		T145	7		T146	1
values[4]	608	1			T13	28		T57	34		T59	6
values[5]	686	1			T2	15		T7	1		T222	18
values[6]	685	1			T12	1		T52	13		T152	1
values[7]	799	1			T46	16		T221	1		T157	1
values[8]	646	1			T58	29		T40	28		T152	1
values[9]	982	1			T59	18		T50	14		T146	1
minimum	15633	1			T1	180		T8	139		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T2	6		T39	19		T53	16
values[1]	3052	1			T3	1		T5	21		T11	10
values[2]	512	1			T6	1		T145	7		T146	1
values[3]	616	1			T13	28		T57	34		T59	6
values[4]	798	1			T2	15		T7	1		T12	1
values[5]	612	1			T52	13		T152	1		T221	1
values[6]	813	1			T46	16		T158	5		T159	14
values[7]	803	1			T58	29		T59	18		T40	28
values[8]	837	1			T50	14		T156	26		T147	1
values[9]	141	1			T7	1		T53	18		T162	15
minimum	16139	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	10		T153	10		T148	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	1		T53	8		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T3	1		T5	21		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T57	1		T145	11		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T146	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	3		T224	8		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T57	17		T59	6		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T13	15		T57	1		T159	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	7		T222	16		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	1		T12	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T152	1		T157	1		T70	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T52	13		T221	1		T159	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T150	1		T234	12		T229	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T46	9		T158	1		T159	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T59	18		T152	1		T69	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T58	17		T40	8		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T50	1		T69	13		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T156	11		T147	1		T70	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T96	1		T206	1		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T7	1		T53	14		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15853	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T28	1		T168	1		T92	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	9		T235	15		T305	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	5		T53	8		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T11	9		T49	22		T195	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T145	11		T148	16		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T203	14		T16	6		T246	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T145	4		T30	2		T161	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T57	16		T172	16		T151	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	13		T151	13		T273	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	8		T222	2		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T230	12		T279	8		T204	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T70	4		T41	1		T245	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T97	8		T104	4		T21	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T229	18		T253	10		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T46	7		T158	4		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T69	6		T70	6		T242	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T58	12		T40	20		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	13		T69	13		T203	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T156	15		T231	2		T44	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T96	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T53	4		T162	14		T267	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T57	1		T40	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T168	2		T306	16		T307	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T1	1		T8	7		T15	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	1		T53	14		T156	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T119	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T205	3		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T153	10		T235	43		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T234	7		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T3	1		T5	21		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T57	1		T53	8		T145	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T146	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T145	3		T148	5		T224	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T57	17		T59	6		T223	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	15		T57	1		T159	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	7		T222	16		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	1		T230	13		T189	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T152	1		T157	1		T70	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	1		T52	13		T159	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T157	1		T150	1		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	9		T221	1		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T152	1		T157	1		T253	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T58	17		T40	8		T156	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T59	18		T50	1		T69	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T146	1		T41	1		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15480	1			T1	180		T8	139		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T203	4		T253	11		T243	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T53	4		T156	15		T267	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T205	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T235	22		T266	7		T305	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	5		T234	7		T172	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T11	9		T39	9		T49	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T53	8		T145	18		T199	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T43	2		T16	6		T246	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T145	4		T148	15		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T57	16		T203	14		T172	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	13		T151	13		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	8		T222	2		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T230	12		T279	8		T204	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T70	4		T41	1		T245	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T97	8		T191	11		T104	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T229	18		T161	8		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	7		T230	12		T246	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T253	10		T286	2		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T58	12		T40	20		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T50	13		T69	19		T70	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T231	2		T149	15		T44	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	15		T153	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	6		T53	9		T145	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T3	1		T5	3		T11	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T57	1		T145	12		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T146	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T145	5		T224	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T57	17		T59	1		T172	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	14		T57	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	9		T222	3		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T12	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T152	1		T157	1		T70	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T52	1		T221	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T150	1		T234	1		T229	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	8		T158	5		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T59	1		T152	1		T69	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T58	13		T40	26		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T50	14		T69	15		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T156	16		T147	1		T70	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T96	3		T206	1		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T7	1		T53	5		T162	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16006	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T28	1		T168	3		T92	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	4		T153	9		T148	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T53	7		T145	9		T199	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T5	18		T45	14		T47	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T145	10		T148	12		T234	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T223	11		T203	2		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T145	2		T224	7		T161	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T57	16		T59	5		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T13	14		T159	2		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	6		T222	15		T154	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T230	12		T189	3		T252	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T70	1		T41	1		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T52	12		T159	4		T208	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T234	11		T229	11		T233	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T46	8		T159	13		T224	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T59	17		T69	3		T70	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T58	16		T40	2		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T69	11		T253	8		T233	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T156	10		T70	6		T171	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T193	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T53	13		T308	11		T309	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T266	13		T104	3		T310	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T92	11		T306	18		T311	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	413	1			T1	1		T8	7		T15	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	1		T53	5		T156	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T119	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T205	6		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T153	1		T235	25		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	6		T234	8		T172	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T3	1		T5	3		T11	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T57	1		T53	9		T145	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T146	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T145	5		T148	16		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T57	17		T59	1		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	14		T57	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	9		T222	3		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	1		T230	13		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T152	1		T157	1		T70	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T52	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T157	1		T150	1		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T46	8		T221	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	1		T157	1		T253	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T58	13		T40	26		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T59	1		T50	14		T69	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T146	1		T41	1		T231	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15633	1			T1	180		T8	139		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T253	8		T312	10		T277	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T53	13		T156	10		T70	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	9		T235	40		T266	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T234	6		T174	13		T204	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T5	18		T39	4		T45	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T53	7		T145	19		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	5		T246	27		T249	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	2		T148	4		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T57	16		T59	5		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T13	14		T159	2		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	6		T222	15		T154	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T230	12		T189	3		T252	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T70	1		T41	1		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T52	12		T159	4		T208	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T234	11		T229	11		T233	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	8		T159	13		T230	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T247	9		T265	1		T98	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	16		T40	2		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T59	17		T69	14		T70	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T149	17		T250	10		T171	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14