Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24967

1

T1

181

T2

21

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21421

1

T1

181

T3

1

T5

21

auto[ADC_CTRL_FILTER_COND_OUT]

3546

1

T2

21

T6

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19028

1

T1

181

T2

21

T6

1

auto[1]

5939

1

T3

1

T5

21

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20985

1

T1

181

T2

8

T3

1

auto[1]

3982

1

T2

13

T11

9

T13

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	279	1			T2	15		T53	16		T147	1
values[0]	24	1			T221	1		T161	9		T272	3
values[1]	716	1			T53	18		T70	9		T149	12
values[2]	692	1			T70	6		T196	11		T148	30
values[3]	734	1			T7	1		T145	22		T147	1
values[4]	601	1			T2	6		T12	1		T152	1
values[5]	2892	1			T3	1		T5	21		T6	1
values[6]	721	1			T7	1		T59	6		T52	13
values[7]	616	1			T39	19		T46	16		T156	11
values[8]	612	1			T57	1		T50	14		T40	28
values[9]	1102	1			T13	28		T58	29		T59	18
minimum	15978	1			T1	181		T8	146		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	599	1			T70	9		T149	12		T223	12
values[1]	740	1			T70	6		T196	11		T148	30
values[2]	594	1			T2	6		T7	1		T145	22
values[3]	2931	1			T3	1		T5	21		T11	10
values[4]	777	1			T6	1		T57	33		T52	13
values[5]	638	1			T7	1		T59	6		T46	16
values[6]	545	1			T39	19		T156	11		T147	1
values[7]	685	1			T57	1		T59	18		T50	14
values[8]	1088	1			T2	15		T13	28		T58	29
values[9]	105	1			T43	4		T111	26		T225	1
minimum	16265	1			T1	181		T8	146		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

4102

1

T2

6

T5

18

T13

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T223	12		T171	11		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T70	3		T149	1		T273	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T196	7		T148	5		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T70	2		T148	9		T242	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	1		T145	11		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	1		T147	1		T69	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T3	1		T5	21		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T57	1		T69	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T222	16		T199	22		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T57	17		T52	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	1		T59	6		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	9		T146	2		T154	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T39	10		T156	3		T69	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T147	1		T159	5		T224	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	1		T151	15		T227	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T57	1		T59	18		T40	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T58	17		T147	1		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T2	7		T13	15		T53	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T43	2		T225	1		T238	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T111	14		T226	11		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15875	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T53	14		T253	6		T161	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T172	16		T228	10		T174	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T70	6		T149	11		T273	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T196	4		T148	15		T149	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T70	4		T148	1		T242	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	11		T158	4		T44	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	5		T69	8		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T11	9		T49	22		T195	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T69	6		T16	6		T247	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T222	2		T199	22		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T57	16		T145	4		T231	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T233	11		T280	10		T291	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	7		T154	10		T162	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	9		T156	8		T69	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T234	7		T235	2		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	13		T151	13		T227	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	20		T145	7		T165	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T58	12		T172	8		T235	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T2	8		T13	13		T53	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T43	2		T238	5		T239	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T111	12		T226	10		T240	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T57	1		T40	1		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T53	4		T253	14		T161	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T147	1		T148	3		T172	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T2	7		T53	8		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T221	1		T272	1		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T161	1		T166	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T62	1		T172	1		T227	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	14		T70	3		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T196	7		T148	5		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T70	2		T148	9		T242	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T145	11		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T147	1		T69	3		T199	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T152	1		T157	1		T203	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T12	1		T69	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T3	1		T5	21		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T57	18		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	1		T59	6		T222	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T52	13		T146	1		T154	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	10		T156	3		T69	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T46	9		T146	1		T159	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T50	1		T151	18		T227	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T57	1		T40	8		T153	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T58	17		T196	1		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T13	15		T59	18		T145	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15825	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T172	8		T111	2		T313	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T2	8		T53	8		T108	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T272	2		T177	1		T241	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T161	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T172	16		T227	2		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T53	4		T70	6		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T196	4		T148	15		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T70	4		T148	1		T242	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	11		T158	4		T44	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T69	8		T199	9		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T203	4		T229	18		T244	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T2	5		T69	6		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T11	9		T49	22		T195	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T57	16		T145	4		T16	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T222	2		T199	22		T245	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T154	10		T231	2		T162	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T39	9		T156	8		T69	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	7		T234	7		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T50	13		T151	17		T227	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T40	20		T165	3		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T58	12		T43	2		T235	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T13	13		T145	7		T156	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	1		T40	1		T41	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T223	1		T171	1		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T70	7		T149	12		T273	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T196	5		T148	16		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T70	5		T148	2		T242	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T145	12		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	6		T147	1		T69	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T3	1		T5	3		T11	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T57	1		T69	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T222	3		T199	24		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	1		T57	17		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	1		T59	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T46	8		T146	2		T154	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	15		T156	9		T69	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T147	1		T159	1		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	14		T151	14		T227	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T57	1		T59	1		T40	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T58	13		T147	1		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T2	9		T13	14		T53	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T43	4		T225	1		T238	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T111	13		T226	11		T240	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16046	1			T1	181		T8	146		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T53	5		T253	15		T161	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T223	11		T171	10		T228	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T70	2		T273	8		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T196	6		T148	4		T149	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T70	1		T148	8		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T145	10		T70	6		T224	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T69	2		T199	10		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T5	18		T45	14		T47	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T69	3		T171	8		T16	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T222	15		T199	20		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T57	16		T52	12		T145	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T59	5		T233	14		T269	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T46	8		T154	7		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T39	4		T156	2		T69	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T159	4		T224	12		T234	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	14		T227	15		T255	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T59	17		T40	2		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T58	16		T148	2		T250	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T2	6		T13	14		T53	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T238	5		T239	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T111	13		T226	10		T314	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T227	13		T252	4		T263	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T53	13		T253	5		T161	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T147	1		T148	1		T172	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T2	9		T53	9		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T221	1		T272	3		T177	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T161	9		T166	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T62	1		T172	17		T227	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T53	5		T70	7		T149	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T196	5		T148	16		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T70	5		T148	2		T242	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	1		T145	12		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T147	1		T69	9		T199	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T152	1		T157	1		T203	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	6		T12	1		T69	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T3	1		T5	3		T11	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T57	18		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T59	1		T222	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T52	1		T146	1		T154	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	15		T156	9		T69	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	8		T146	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	14		T151	19		T227	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T57	1		T40	26		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T58	13		T196	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T13	14		T59	1		T145	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15978	1			T1	181		T8	146		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T148	2		T111	4		T315	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T2	6		T53	7		T224	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T227	13		T228	2		T174	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	13		T70	2		T273	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T196	6		T148	4		T149	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T70	1		T148	8		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T145	10		T70	6		T224	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T69	2		T199	10		T159	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T229	11		T266	13		T254	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T69	3		T171	8		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T5	18		T45	14		T47	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T57	16		T145	2		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T59	5		T222	15		T199	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T52	12		T154	7		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	4		T156	2		T69	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T46	8		T159	4		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T151	16		T227	15		T169	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	2		T153	9		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T58	16		T250	10		T235	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T13	14		T59	17		T145	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20865

1

T1

181

T2

15

T3

1

auto[1]

auto[0]

4102

1

T2

6

T5

18

T13

14