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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.46


Total test records in report: 916
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T790 /workspace/coverage/default/45.adc_ctrl_clock_gating.1905709302 Jul 31 06:51:39 PM PDT 24 Jul 31 06:54:58 PM PDT 24 351713168069 ps
T791 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2350112580 Jul 31 05:19:09 PM PDT 24 Jul 31 05:19:10 PM PDT 24 380540240 ps
T792 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.371357773 Jul 31 05:18:40 PM PDT 24 Jul 31 05:18:42 PM PDT 24 346335346 ps
T75 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3337775335 Jul 31 05:18:46 PM PDT 24 Jul 31 05:18:49 PM PDT 24 521300405 ps
T793 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3525837689 Jul 31 05:18:56 PM PDT 24 Jul 31 05:18:57 PM PDT 24 322185026 ps
T76 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1519505980 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:49 PM PDT 24 591864742 ps
T794 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1750659045 Jul 31 05:18:58 PM PDT 24 Jul 31 05:18:59 PM PDT 24 444128118 ps
T795 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1159973344 Jul 31 05:18:39 PM PDT 24 Jul 31 05:18:40 PM PDT 24 512395759 ps
T84 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.815383651 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:17 PM PDT 24 1228787251 ps
T123 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3458400469 Jul 31 05:18:15 PM PDT 24 Jul 31 05:18:17 PM PDT 24 745741639 ps
T101 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3631863229 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:56 PM PDT 24 354730086 ps
T66 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2720577495 Jul 31 05:18:34 PM PDT 24 Jul 31 05:18:40 PM PDT 24 4360329109 ps
T85 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1888562229 Jul 31 05:19:07 PM PDT 24 Jul 31 05:19:09 PM PDT 24 421687187 ps
T796 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.139573029 Jul 31 05:19:14 PM PDT 24 Jul 31 05:19:15 PM PDT 24 544597584 ps
T124 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2919547258 Jul 31 05:18:30 PM PDT 24 Jul 31 05:18:32 PM PDT 24 507138419 ps
T797 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1622382251 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:55 PM PDT 24 399111704 ps
T798 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3655135281 Jul 31 05:18:48 PM PDT 24 Jul 31 05:18:48 PM PDT 24 410288349 ps
T71 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1562221825 Jul 31 05:18:49 PM PDT 24 Jul 31 05:19:12 PM PDT 24 8471411175 ps
T102 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1417418147 Jul 31 05:18:22 PM PDT 24 Jul 31 05:18:24 PM PDT 24 429058233 ps
T82 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.295056092 Jul 31 05:18:45 PM PDT 24 Jul 31 05:18:48 PM PDT 24 596980013 ps
T125 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2205602215 Jul 31 05:18:25 PM PDT 24 Jul 31 05:18:26 PM PDT 24 393433003 ps
T67 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3048020349 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:54 PM PDT 24 1930737404 ps
T68 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2915940284 Jul 31 05:18:40 PM PDT 24 Jul 31 05:18:44 PM PDT 24 4513075398 ps
T126 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.907896269 Jul 31 05:18:53 PM PDT 24 Jul 31 05:18:55 PM PDT 24 430648590 ps
T799 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3244909150 Jul 31 05:19:08 PM PDT 24 Jul 31 05:19:09 PM PDT 24 474945692 ps
T138 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3427058860 Jul 31 05:18:33 PM PDT 24 Jul 31 05:18:35 PM PDT 24 4019518887 ps
T139 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3217527711 Jul 31 05:18:38 PM PDT 24 Jul 31 05:18:44 PM PDT 24 4464064076 ps
T800 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.653135312 Jul 31 05:18:59 PM PDT 24 Jul 31 05:19:06 PM PDT 24 348708736 ps
T127 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1166099271 Jul 31 05:18:14 PM PDT 24 Jul 31 05:18:18 PM PDT 24 2653287204 ps
T801 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.518772419 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:55 PM PDT 24 497207418 ps
T72 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1541070684 Jul 31 05:18:48 PM PDT 24 Jul 31 05:18:59 PM PDT 24 8122846356 ps
T140 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.272021805 Jul 31 05:18:46 PM PDT 24 Jul 31 05:18:56 PM PDT 24 4520757897 ps
T802 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3578126074 Jul 31 05:18:50 PM PDT 24 Jul 31 05:18:52 PM PDT 24 445023683 ps
T87 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1786533390 Jul 31 05:18:10 PM PDT 24 Jul 31 05:18:12 PM PDT 24 741591729 ps
T83 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3793837067 Jul 31 05:18:38 PM PDT 24 Jul 31 05:18:41 PM PDT 24 422600809 ps
T141 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.887480422 Jul 31 05:18:56 PM PDT 24 Jul 31 05:19:00 PM PDT 24 2276406105 ps
T803 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1644902176 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:39 PM PDT 24 628058581 ps
T804 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2867669687 Jul 31 05:18:19 PM PDT 24 Jul 31 05:18:20 PM PDT 24 606346501 ps
T805 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.809400210 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:37 PM PDT 24 443021170 ps
T806 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3570326594 Jul 31 05:18:51 PM PDT 24 Jul 31 05:18:52 PM PDT 24 565148395 ps
T73 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3212768380 Jul 31 05:18:17 PM PDT 24 Jul 31 05:18:23 PM PDT 24 7803497937 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.342047856 Jul 31 05:18:26 PM PDT 24 Jul 31 05:18:29 PM PDT 24 1204814774 ps
T807 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2356904620 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:39 PM PDT 24 441775287 ps
T129 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.504257456 Jul 31 05:18:48 PM PDT 24 Jul 31 05:18:49 PM PDT 24 315611880 ps
T130 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3593565114 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:39 PM PDT 24 515351069 ps
T808 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.516541676 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:48 PM PDT 24 531982374 ps
T131 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3125062230 Jul 31 05:19:00 PM PDT 24 Jul 31 05:19:02 PM PDT 24 428562773 ps
T809 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1161819525 Jul 31 05:18:54 PM PDT 24 Jul 31 05:19:03 PM PDT 24 2541365973 ps
T810 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.386483043 Jul 31 05:18:50 PM PDT 24 Jul 31 05:18:52 PM PDT 24 386909504 ps
T811 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.456217003 Jul 31 05:18:29 PM PDT 24 Jul 31 05:18:45 PM PDT 24 4211979306 ps
T812 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3884333908 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:56 PM PDT 24 378945102 ps
T813 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1333353511 Jul 31 05:18:46 PM PDT 24 Jul 31 05:18:48 PM PDT 24 538224809 ps
T341 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3908433061 Jul 31 05:18:48 PM PDT 24 Jul 31 05:18:54 PM PDT 24 9205151745 ps
T342 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3341713452 Jul 31 05:18:38 PM PDT 24 Jul 31 05:18:43 PM PDT 24 4796776410 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2152864602 Jul 31 05:19:01 PM PDT 24 Jul 31 05:19:06 PM PDT 24 8953503026 ps
T815 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1972175011 Jul 31 05:18:55 PM PDT 24 Jul 31 05:18:56 PM PDT 24 481552559 ps
T132 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2548816860 Jul 31 05:18:13 PM PDT 24 Jul 31 05:18:16 PM PDT 24 711026132 ps
T816 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3076798227 Jul 31 05:18:57 PM PDT 24 Jul 31 05:19:04 PM PDT 24 4459557579 ps
T817 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2156739043 Jul 31 05:18:30 PM PDT 24 Jul 31 05:18:31 PM PDT 24 398244171 ps
T818 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.965672138 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:48 PM PDT 24 373697826 ps
T819 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3849710681 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:37 PM PDT 24 1333514158 ps
T133 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2491083564 Jul 31 05:18:22 PM PDT 24 Jul 31 05:18:42 PM PDT 24 26820558617 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4217523025 Jul 31 05:18:46 PM PDT 24 Jul 31 05:18:47 PM PDT 24 520389664 ps
T821 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.357261317 Jul 31 05:18:51 PM PDT 24 Jul 31 05:18:55 PM PDT 24 4141893904 ps
T822 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2704004265 Jul 31 05:18:51 PM PDT 24 Jul 31 05:18:52 PM PDT 24 817575283 ps
T823 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.293890175 Jul 31 05:18:35 PM PDT 24 Jul 31 05:18:39 PM PDT 24 2318443575 ps
T824 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3714250583 Jul 31 05:18:40 PM PDT 24 Jul 31 05:18:43 PM PDT 24 522538481 ps
T825 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1193642129 Jul 31 05:18:51 PM PDT 24 Jul 31 05:18:51 PM PDT 24 355548966 ps
T88 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.275866101 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:38 PM PDT 24 7858214716 ps
T826 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.9720392 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:47 PM PDT 24 3920165296 ps
T827 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2431336566 Jul 31 05:19:01 PM PDT 24 Jul 31 05:19:04 PM PDT 24 393142122 ps
T828 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1038434173 Jul 31 05:18:24 PM PDT 24 Jul 31 05:18:26 PM PDT 24 2244901298 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3149744880 Jul 31 05:18:45 PM PDT 24 Jul 31 05:18:47 PM PDT 24 358072421 ps
T830 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2784959217 Jul 31 05:18:34 PM PDT 24 Jul 31 05:18:36 PM PDT 24 1146812984 ps
T831 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3988708646 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:33 PM PDT 24 422220648 ps
T832 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.719476606 Jul 31 05:19:02 PM PDT 24 Jul 31 05:19:04 PM PDT 24 3091299614 ps
T833 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.7323200 Jul 31 05:18:49 PM PDT 24 Jul 31 05:18:50 PM PDT 24 528771058 ps
T834 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1742521637 Jul 31 05:18:42 PM PDT 24 Jul 31 05:18:45 PM PDT 24 2031333551 ps
T835 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.751166795 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:55 PM PDT 24 368152229 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1768656022 Jul 31 05:18:46 PM PDT 24 Jul 31 05:18:49 PM PDT 24 819985613 ps
T837 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3997200787 Jul 31 05:18:48 PM PDT 24 Jul 31 05:18:52 PM PDT 24 5207920708 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1319914984 Jul 31 05:18:23 PM PDT 24 Jul 31 05:18:24 PM PDT 24 585595642 ps
T839 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3988596350 Jul 31 05:18:19 PM PDT 24 Jul 31 05:18:23 PM PDT 24 1262159026 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1509734216 Jul 31 05:18:50 PM PDT 24 Jul 31 05:18:51 PM PDT 24 582589455 ps
T134 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1643828296 Jul 31 05:18:11 PM PDT 24 Jul 31 05:18:12 PM PDT 24 407005863 ps
T841 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3885418282 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:32 PM PDT 24 483403475 ps
T842 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2541492075 Jul 31 05:18:19 PM PDT 24 Jul 31 05:18:22 PM PDT 24 555811941 ps
T89 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.776184782 Jul 31 05:18:05 PM PDT 24 Jul 31 05:18:13 PM PDT 24 8760657087 ps
T843 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2823653673 Jul 31 05:18:46 PM PDT 24 Jul 31 05:19:18 PM PDT 24 27612684747 ps
T844 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1437279681 Jul 31 05:19:04 PM PDT 24 Jul 31 05:19:07 PM PDT 24 765377649 ps
T845 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3276335541 Jul 31 05:18:53 PM PDT 24 Jul 31 05:18:54 PM PDT 24 398381426 ps
T846 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2417159580 Jul 31 05:18:55 PM PDT 24 Jul 31 05:18:57 PM PDT 24 489951515 ps
T847 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1155313871 Jul 31 05:18:49 PM PDT 24 Jul 31 05:18:50 PM PDT 24 492659096 ps
T848 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3148820916 Jul 31 05:18:49 PM PDT 24 Jul 31 05:18:50 PM PDT 24 343809330 ps
T849 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2279639473 Jul 31 05:18:52 PM PDT 24 Jul 31 05:18:53 PM PDT 24 286429673 ps
T850 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1630243362 Jul 31 05:18:14 PM PDT 24 Jul 31 05:18:19 PM PDT 24 4431452201 ps
T851 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1529284066 Jul 31 05:18:26 PM PDT 24 Jul 31 05:18:29 PM PDT 24 861847254 ps
T852 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2344646548 Jul 31 05:18:52 PM PDT 24 Jul 31 05:18:53 PM PDT 24 391209561 ps
T853 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3419921773 Jul 31 05:18:27 PM PDT 24 Jul 31 05:18:28 PM PDT 24 368652639 ps
T854 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1369074805 Jul 31 05:18:32 PM PDT 24 Jul 31 05:18:35 PM PDT 24 1234531987 ps
T855 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2325639792 Jul 31 05:18:43 PM PDT 24 Jul 31 05:18:50 PM PDT 24 8082523529 ps
T856 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.277050762 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:49 PM PDT 24 440747919 ps
T857 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1579675990 Jul 31 05:18:55 PM PDT 24 Jul 31 05:18:56 PM PDT 24 393248101 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2020664685 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:39 PM PDT 24 844923049 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.150319053 Jul 31 05:18:53 PM PDT 24 Jul 31 05:18:54 PM PDT 24 383941860 ps
T860 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2322231040 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:51 PM PDT 24 4571214442 ps
T135 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2258352440 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:47 PM PDT 24 16265458458 ps
T861 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3108590996 Jul 31 05:19:01 PM PDT 24 Jul 31 05:19:02 PM PDT 24 463810517 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.214072040 Jul 31 05:18:25 PM PDT 24 Jul 31 05:18:26 PM PDT 24 513779105 ps
T863 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.292054111 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:51 PM PDT 24 1830970665 ps
T864 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2197024303 Jul 31 05:18:41 PM PDT 24 Jul 31 05:18:44 PM PDT 24 517091328 ps
T865 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4032672485 Jul 31 05:18:52 PM PDT 24 Jul 31 05:18:53 PM PDT 24 421004688 ps
T866 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3734823301 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:55 PM PDT 24 538255668 ps
T867 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3517884367 Jul 31 05:18:48 PM PDT 24 Jul 31 05:18:55 PM PDT 24 2614220492 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4242969879 Jul 31 05:18:45 PM PDT 24 Jul 31 05:18:47 PM PDT 24 457311685 ps
T869 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2016117231 Jul 31 05:19:04 PM PDT 24 Jul 31 05:19:05 PM PDT 24 563608025 ps
T870 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2221936212 Jul 31 05:18:44 PM PDT 24 Jul 31 05:18:48 PM PDT 24 2918603411 ps
T871 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4177917399 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:49 PM PDT 24 582394959 ps
T872 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2377355620 Jul 31 05:19:00 PM PDT 24 Jul 31 05:19:02 PM PDT 24 423895270 ps
T136 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1124047985 Jul 31 05:18:08 PM PDT 24 Jul 31 05:18:55 PM PDT 24 51532310029 ps
T873 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.360396577 Jul 31 05:18:59 PM PDT 24 Jul 31 05:19:00 PM PDT 24 351836637 ps
T874 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2628067166 Jul 31 05:18:43 PM PDT 24 Jul 31 05:18:45 PM PDT 24 402121663 ps
T875 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3787930081 Jul 31 05:18:44 PM PDT 24 Jul 31 05:18:46 PM PDT 24 5127477718 ps
T876 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2569255126 Jul 31 05:19:00 PM PDT 24 Jul 31 05:19:00 PM PDT 24 370114009 ps
T877 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3898191771 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:38 PM PDT 24 343202513 ps
T878 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2891343007 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:55 PM PDT 24 411400284 ps
T879 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3523634982 Jul 31 05:18:52 PM PDT 24 Jul 31 05:18:53 PM PDT 24 549491851 ps
T880 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1006560433 Jul 31 05:18:38 PM PDT 24 Jul 31 05:18:40 PM PDT 24 456365281 ps
T881 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3041268564 Jul 31 05:18:53 PM PDT 24 Jul 31 05:18:56 PM PDT 24 494733059 ps
T882 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.694850802 Jul 31 05:18:32 PM PDT 24 Jul 31 05:18:33 PM PDT 24 329529077 ps
T883 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.121094951 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:38 PM PDT 24 463459232 ps
T884 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.539057944 Jul 31 05:18:34 PM PDT 24 Jul 31 05:18:38 PM PDT 24 4457038370 ps
T885 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2775872061 Jul 31 05:18:27 PM PDT 24 Jul 31 05:18:31 PM PDT 24 4315155049 ps
T886 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.137129485 Jul 31 05:19:01 PM PDT 24 Jul 31 05:19:02 PM PDT 24 503856077 ps
T887 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4192383627 Jul 31 05:18:41 PM PDT 24 Jul 31 05:18:42 PM PDT 24 391449940 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1681912627 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:33 PM PDT 24 320984196 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4277526376 Jul 31 05:18:32 PM PDT 24 Jul 31 05:18:36 PM PDT 24 4772149957 ps
T890 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1615297160 Jul 31 05:18:41 PM PDT 24 Jul 31 05:18:42 PM PDT 24 529897588 ps
T891 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3209312323 Jul 31 05:18:44 PM PDT 24 Jul 31 05:18:45 PM PDT 24 456417129 ps
T892 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3745749730 Jul 31 05:18:45 PM PDT 24 Jul 31 05:18:57 PM PDT 24 8597057875 ps
T893 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2849474754 Jul 31 05:18:32 PM PDT 24 Jul 31 05:18:35 PM PDT 24 1219736560 ps
T894 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.910876632 Jul 31 05:18:39 PM PDT 24 Jul 31 05:18:40 PM PDT 24 549380320 ps
T895 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.769610625 Jul 31 05:18:44 PM PDT 24 Jul 31 05:18:47 PM PDT 24 591913231 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.378426024 Jul 31 05:19:02 PM PDT 24 Jul 31 05:19:05 PM PDT 24 1712542014 ps
T343 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3105832600 Jul 31 05:18:48 PM PDT 24 Jul 31 05:19:11 PM PDT 24 8729062181 ps
T897 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1836358829 Jul 31 05:18:48 PM PDT 24 Jul 31 05:18:50 PM PDT 24 540230558 ps
T898 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.445938241 Jul 31 05:18:52 PM PDT 24 Jul 31 05:18:53 PM PDT 24 464489675 ps
T899 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1558653752 Jul 31 05:19:00 PM PDT 24 Jul 31 05:19:01 PM PDT 24 368906514 ps
T900 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.982266431 Jul 31 05:18:46 PM PDT 24 Jul 31 05:19:06 PM PDT 24 8505961776 ps
T137 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4260898618 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:48 PM PDT 24 562715281 ps
T901 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2799154456 Jul 31 05:18:35 PM PDT 24 Jul 31 05:18:39 PM PDT 24 770686379 ps
T902 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.185251793 Jul 31 05:18:31 PM PDT 24 Jul 31 05:18:32 PM PDT 24 338018528 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1807623880 Jul 31 05:18:14 PM PDT 24 Jul 31 05:18:16 PM PDT 24 368004178 ps
T904 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4121251393 Jul 31 05:18:44 PM PDT 24 Jul 31 05:18:56 PM PDT 24 8603321433 ps
T905 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3573787758 Jul 31 05:18:36 PM PDT 24 Jul 31 05:18:38 PM PDT 24 469150621 ps
T906 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3121412046 Jul 31 05:18:23 PM PDT 24 Jul 31 05:18:26 PM PDT 24 1935795478 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2503540274 Jul 31 05:18:19 PM PDT 24 Jul 31 05:18:21 PM PDT 24 1244785634 ps
T908 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2509714423 Jul 31 05:18:40 PM PDT 24 Jul 31 05:18:42 PM PDT 24 422351723 ps
T909 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4240814641 Jul 31 05:18:41 PM PDT 24 Jul 31 05:18:42 PM PDT 24 399328837 ps
T910 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3327701043 Jul 31 05:18:54 PM PDT 24 Jul 31 05:18:55 PM PDT 24 356547211 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.358482513 Jul 31 05:18:37 PM PDT 24 Jul 31 05:18:39 PM PDT 24 447062357 ps
T912 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3704460373 Jul 31 05:18:50 PM PDT 24 Jul 31 05:18:51 PM PDT 24 500550726 ps
T913 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1503353714 Jul 31 05:18:53 PM PDT 24 Jul 31 05:19:00 PM PDT 24 384792657 ps
T914 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.4150126689 Jul 31 05:18:21 PM PDT 24 Jul 31 05:18:22 PM PDT 24 556200618 ps
T915 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3546854571 Jul 31 05:18:47 PM PDT 24 Jul 31 05:18:48 PM PDT 24 505658597 ps
T916 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3304095411 Jul 31 05:18:52 PM PDT 24 Jul 31 05:18:53 PM PDT 24 333117242 ps

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.346469525
Short name T2
Test name
Test status
Simulation time 349606599708 ps
CPU time 401.7 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:44:42 PM PDT 24
Peak memory 201480 kb
Host smart-98c05f16-3470-4cb6-bae3-1efc3e7defaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346469525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.346469525
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3602638141
Short name T1
Test name
Test status
Simulation time 115723805812 ps
CPU time 593 seconds
Started Jul 31 06:44:45 PM PDT 24
Finished Jul 31 06:54:38 PM PDT 24
Peak memory 201824 kb
Host smart-ff826be3-ba9a-4d7a-8770-c6e0e99d56f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602638141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3602638141
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.117021913
Short name T57
Test name
Test status
Simulation time 525634163804 ps
CPU time 264.45 seconds
Started Jul 31 06:47:32 PM PDT 24
Finished Jul 31 06:51:57 PM PDT 24
Peak memory 201444 kb
Host smart-9257b01e-80c9-4063-ab14-c71c639da2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117021913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
117021913
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3683114320
Short name T16
Test name
Test status
Simulation time 79872406942 ps
CPU time 51.29 seconds
Started Jul 31 06:41:33 PM PDT 24
Finished Jul 31 06:42:24 PM PDT 24
Peak memory 210156 kb
Host smart-f0750847-327e-4a2f-a7c1-12ace6911a54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683114320 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3683114320
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1791360499
Short name T69
Test name
Test status
Simulation time 524799207049 ps
CPU time 72.3 seconds
Started Jul 31 06:52:33 PM PDT 24
Finished Jul 31 06:53:46 PM PDT 24
Peak memory 201412 kb
Host smart-3560271d-7c2a-40da-ba32-219d70d767a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791360499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1791360499
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.623029692
Short name T172
Test name
Test status
Simulation time 675019416042 ps
CPU time 916.68 seconds
Started Jul 31 06:49:18 PM PDT 24
Finished Jul 31 07:04:35 PM PDT 24
Peak memory 218244 kb
Host smart-6bdb7a9d-a2d5-44c0-b5ea-4bf1760601ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623029692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
623029692
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3711085951
Short name T148
Test name
Test status
Simulation time 500697999078 ps
CPU time 1118.56 seconds
Started Jul 31 06:52:25 PM PDT 24
Finished Jul 31 07:11:04 PM PDT 24
Peak memory 201516 kb
Host smart-742b093c-a59b-4f6e-80ab-f9d920abee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711085951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3711085951
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1599560492
Short name T159
Test name
Test status
Simulation time 727730208844 ps
CPU time 1662.37 seconds
Started Jul 31 06:38:04 PM PDT 24
Finished Jul 31 07:05:47 PM PDT 24
Peak memory 201452 kb
Host smart-59f9812f-6830-4f27-95d8-ca7b773507ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599560492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1599560492
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3698654065
Short name T74
Test name
Test status
Simulation time 126886794942 ps
CPU time 172.13 seconds
Started Jul 31 06:51:13 PM PDT 24
Finished Jul 31 06:54:06 PM PDT 24
Peak memory 217916 kb
Host smart-79a08ca3-ea23-48a0-83db-f1dfef2ec0ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698654065 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3698654065
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1130762406
Short name T246
Test name
Test status
Simulation time 536924906037 ps
CPU time 605.3 seconds
Started Jul 31 06:42:16 PM PDT 24
Finished Jul 31 06:52:21 PM PDT 24
Peak memory 201464 kb
Host smart-117e334a-055a-49b5-8f05-e7b38f3be313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130762406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1130762406
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.4030369829
Short name T174
Test name
Test status
Simulation time 555322228915 ps
CPU time 278.08 seconds
Started Jul 31 06:44:40 PM PDT 24
Finished Jul 31 06:49:18 PM PDT 24
Peak memory 201488 kb
Host smart-cc7c3fc4-eccc-45d0-9bf7-478b15e2d599
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030369829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.4030369829
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2940788058
Short name T53
Test name
Test status
Simulation time 355227731350 ps
CPU time 799.58 seconds
Started Jul 31 06:45:02 PM PDT 24
Finished Jul 31 06:58:22 PM PDT 24
Peak memory 201456 kb
Host smart-6f3fac64-aabe-4445-b384-c09fa8bbff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940788058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2940788058
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.24564427
Short name T236
Test name
Test status
Simulation time 498771776965 ps
CPU time 1141.88 seconds
Started Jul 31 06:38:18 PM PDT 24
Finished Jul 31 06:57:20 PM PDT 24
Peak memory 201472 kb
Host smart-f8b3cef5-47a2-4463-9abf-127dcac1cab9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24564427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating
.24564427
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.971595108
Short name T145
Test name
Test status
Simulation time 526847346111 ps
CPU time 355.93 seconds
Started Jul 31 06:40:08 PM PDT 24
Finished Jul 31 06:46:04 PM PDT 24
Peak memory 201464 kb
Host smart-37749f8c-0084-4b5e-bef1-45f0f8e8fdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971595108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.971595108
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3337775335
Short name T75
Test name
Test status
Simulation time 521300405 ps
CPU time 3.71 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:18:49 PM PDT 24
Peak memory 201536 kb
Host smart-c7f302ca-ee7a-4cd2-bdd7-adf4e09f22b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337775335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3337775335
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2428630819
Short name T230
Test name
Test status
Simulation time 351772266798 ps
CPU time 202.87 seconds
Started Jul 31 06:45:12 PM PDT 24
Finished Jul 31 06:48:35 PM PDT 24
Peak memory 201384 kb
Host smart-3ce5ef6a-72ad-4225-a8f2-1d95d2f6dd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428630819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2428630819
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.214356640
Short name T373
Test name
Test status
Simulation time 310352294 ps
CPU time 0.77 seconds
Started Jul 31 06:44:34 PM PDT 24
Finished Jul 31 06:44:35 PM PDT 24
Peak memory 201248 kb
Host smart-8c1331ca-f472-4fa1-b5bc-652b6927a1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214356640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.214356640
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2427666178
Short name T5
Test name
Test status
Simulation time 596056933034 ps
CPU time 152.32 seconds
Started Jul 31 06:38:06 PM PDT 24
Finished Jul 31 06:40:39 PM PDT 24
Peak memory 201448 kb
Host smart-d7d36f0d-8afd-4104-a91f-75e166045265
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427666178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2427666178
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4183792126
Short name T247
Test name
Test status
Simulation time 503006780050 ps
CPU time 92.47 seconds
Started Jul 31 06:49:57 PM PDT 24
Finished Jul 31 06:51:29 PM PDT 24
Peak memory 201504 kb
Host smart-5e78873f-9d60-4ff2-8977-2cce1ea3a93e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183792126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4183792126
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1166099271
Short name T127
Test name
Test status
Simulation time 2653287204 ps
CPU time 3.89 seconds
Started Jul 31 05:18:14 PM PDT 24
Finished Jul 31 05:18:18 PM PDT 24
Peak memory 201588 kb
Host smart-61b8cd45-8a24-4d07-8b4f-a1265b1adc63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166099271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1166099271
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1500223059
Short name T80
Test name
Test status
Simulation time 8415183004 ps
CPU time 2.91 seconds
Started Jul 31 06:37:50 PM PDT 24
Finished Jul 31 06:37:53 PM PDT 24
Peak memory 218196 kb
Host smart-b33a69e8-1ef2-45ba-bec4-225739991cbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500223059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1500223059
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1968046700
Short name T40
Test name
Test status
Simulation time 312826833775 ps
CPU time 205.47 seconds
Started Jul 31 06:38:21 PM PDT 24
Finished Jul 31 06:41:47 PM PDT 24
Peak memory 209884 kb
Host smart-13213fa1-b64d-405b-a8e2-08ccab7a2249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968046700 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1968046700
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2993041269
Short name T177
Test name
Test status
Simulation time 139479937592 ps
CPU time 322.78 seconds
Started Jul 31 06:46:33 PM PDT 24
Finished Jul 31 06:51:56 PM PDT 24
Peak memory 218340 kb
Host smart-547aca56-414a-4fd1-bc12-6c6739f53276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993041269 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2993041269
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3905000186
Short name T149
Test name
Test status
Simulation time 548742122974 ps
CPU time 1307.57 seconds
Started Jul 31 06:48:49 PM PDT 24
Finished Jul 31 07:10:36 PM PDT 24
Peak memory 201464 kb
Host smart-a83a8531-9f7d-44e9-99cd-6c6dc014a1ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905000186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3905000186
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2646976249
Short name T235
Test name
Test status
Simulation time 567403205217 ps
CPU time 912.2 seconds
Started Jul 31 06:51:17 PM PDT 24
Finished Jul 31 07:06:29 PM PDT 24
Peak memory 201460 kb
Host smart-97543eb2-3cdb-4cff-a4cb-4b39bdb83dd0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646976249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2646976249
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3138258857
Short name T226
Test name
Test status
Simulation time 688997717484 ps
CPU time 410.42 seconds
Started Jul 31 06:48:12 PM PDT 24
Finished Jul 31 06:55:03 PM PDT 24
Peak memory 201468 kb
Host smart-900d74f8-221d-41fe-9119-9fcd8a1a3148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138258857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3138258857
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1046017183
Short name T179
Test name
Test status
Simulation time 488433172765 ps
CPU time 287.62 seconds
Started Jul 31 06:49:28 PM PDT 24
Finished Jul 31 06:54:16 PM PDT 24
Peak memory 201460 kb
Host smart-b3947637-ee11-42ab-9eef-8ac2865c5984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046017183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1046017183
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.602725852
Short name T252
Test name
Test status
Simulation time 450216963406 ps
CPU time 979.72 seconds
Started Jul 31 06:48:57 PM PDT 24
Finished Jul 31 07:05:17 PM PDT 24
Peak memory 201432 kb
Host smart-1a11079d-3627-4b2a-a90f-d9ba32ab2f7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602725852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.602725852
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3789459947
Short name T168
Test name
Test status
Simulation time 492919581571 ps
CPU time 291.15 seconds
Started Jul 31 06:50:44 PM PDT 24
Finished Jul 31 06:55:35 PM PDT 24
Peak memory 201448 kb
Host smart-b687df5e-389f-4dd3-abb1-dc996e695c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789459947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3789459947
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1667289374
Short name T109
Test name
Test status
Simulation time 355576842962 ps
CPU time 609.85 seconds
Started Jul 31 06:40:59 PM PDT 24
Finished Jul 31 06:51:09 PM PDT 24
Peak memory 201460 kb
Host smart-a0d2e102-bf1d-4dc6-9861-73f99709b9f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667289374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1667289374
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1504197526
Short name T205
Test name
Test status
Simulation time 339366997547 ps
CPU time 45.43 seconds
Started Jul 31 06:46:53 PM PDT 24
Finished Jul 31 06:47:39 PM PDT 24
Peak memory 201452 kb
Host smart-f425a3a1-6fa9-412d-9abc-b5e37d621389
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504197526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1504197526
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.622647502
Short name T44
Test name
Test status
Simulation time 150550488653 ps
CPU time 91.56 seconds
Started Jul 31 06:49:34 PM PDT 24
Finished Jul 31 06:51:05 PM PDT 24
Peak memory 209796 kb
Host smart-609fbcdc-1b63-4d10-a6f1-4ab8f8c8622d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622647502 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.622647502
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.275866101
Short name T88
Test name
Test status
Simulation time 7858214716 ps
CPU time 6.8 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 201684 kb
Host smart-73a2c4b5-94d9-41b0-beb9-e25055fd40a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275866101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.275866101
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2053721745
Short name T228
Test name
Test status
Simulation time 336565979220 ps
CPU time 215.77 seconds
Started Jul 31 06:39:56 PM PDT 24
Finished Jul 31 06:43:32 PM PDT 24
Peak memory 201464 kb
Host smart-3872f1c7-44e2-426a-aa3e-fd50e9cd777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053721745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2053721745
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2231062353
Short name T326
Test name
Test status
Simulation time 346093214087 ps
CPU time 429.63 seconds
Started Jul 31 06:42:44 PM PDT 24
Finished Jul 31 06:49:53 PM PDT 24
Peak memory 201464 kb
Host smart-61822cb3-9a1c-4a6a-9928-7770054bf1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231062353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2231062353
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2910164187
Short name T203
Test name
Test status
Simulation time 697171541004 ps
CPU time 1757.35 seconds
Started Jul 31 06:43:36 PM PDT 24
Finished Jul 31 07:12:54 PM PDT 24
Peak memory 210028 kb
Host smart-236f7605-4aa4-49bc-b131-cf2b990ccd17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910164187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2910164187
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.46137272
Short name T259
Test name
Test status
Simulation time 351059759528 ps
CPU time 389.25 seconds
Started Jul 31 06:46:28 PM PDT 24
Finished Jul 31 06:52:57 PM PDT 24
Peak memory 201472 kb
Host smart-3874d8ee-e101-44e4-acd1-1625042354c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46137272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.46137272
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1615705940
Short name T242
Test name
Test status
Simulation time 174197447705 ps
CPU time 396.29 seconds
Started Jul 31 06:38:32 PM PDT 24
Finished Jul 31 06:45:09 PM PDT 24
Peak memory 201476 kb
Host smart-a3b08101-cc24-43f7-9820-e54158ec14ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615705940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1615705940
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3217527711
Short name T139
Test name
Test status
Simulation time 4464064076 ps
CPU time 6.44 seconds
Started Jul 31 05:18:38 PM PDT 24
Finished Jul 31 05:18:44 PM PDT 24
Peak memory 201624 kb
Host smart-6976d216-067c-45f9-bc8a-f9582fe8ab20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217527711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3217527711
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2554008774
Short name T154
Test name
Test status
Simulation time 351832548846 ps
CPU time 1322.87 seconds
Started Jul 31 06:42:54 PM PDT 24
Finished Jul 31 07:04:57 PM PDT 24
Peak memory 201840 kb
Host smart-2fec1f67-1d7e-4a46-8341-e44bd54b3df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554008774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2554008774
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2215071343
Short name T293
Test name
Test status
Simulation time 371065242230 ps
CPU time 852.79 seconds
Started Jul 31 06:45:02 PM PDT 24
Finished Jul 31 06:59:15 PM PDT 24
Peak memory 201428 kb
Host smart-fc363590-719c-48da-8e77-fa3a29aca46a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215071343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2215071343
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3482352703
Short name T94
Test name
Test status
Simulation time 490972831663 ps
CPU time 280.57 seconds
Started Jul 31 06:47:40 PM PDT 24
Finished Jul 31 06:52:21 PM PDT 24
Peak memory 201432 kb
Host smart-ae40fbde-8745-4517-bc0c-511b7544c2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482352703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3482352703
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.680601309
Short name T162
Test name
Test status
Simulation time 501504825015 ps
CPU time 292.77 seconds
Started Jul 31 06:38:45 PM PDT 24
Finished Jul 31 06:43:38 PM PDT 24
Peak memory 201476 kb
Host smart-26ac8989-0e10-4e15-9181-20de602e0677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680601309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.680601309
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.236732416
Short name T239
Test name
Test status
Simulation time 511831065418 ps
CPU time 327.72 seconds
Started Jul 31 06:51:58 PM PDT 24
Finished Jul 31 06:57:26 PM PDT 24
Peak memory 201472 kb
Host smart-1fba85fd-f78c-403d-80a5-e3aedc84e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236732416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.236732416
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3525732345
Short name T11
Test name
Test status
Simulation time 164810248032 ps
CPU time 47.03 seconds
Started Jul 31 06:41:42 PM PDT 24
Finished Jul 31 06:42:29 PM PDT 24
Peak memory 201444 kb
Host smart-1338d9ba-8466-46b7-9b21-c6b6818d6849
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525732345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3525732345
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.500793215
Short name T245
Test name
Test status
Simulation time 216479704030 ps
CPU time 250.69 seconds
Started Jul 31 06:46:53 PM PDT 24
Finished Jul 31 06:51:04 PM PDT 24
Peak memory 201400 kb
Host smart-0050b2dc-72fe-48d1-becd-9902c22ac324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500793215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.500793215
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.255033188
Short name T270
Test name
Test status
Simulation time 162441397489 ps
CPU time 165.17 seconds
Started Jul 31 06:39:14 PM PDT 24
Finished Jul 31 06:41:59 PM PDT 24
Peak memory 201536 kb
Host smart-6d4204ff-1038-41ba-9242-45dfa6aac561
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255033188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.255033188
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1844853180
Short name T297
Test name
Test status
Simulation time 77206853744 ps
CPU time 159.08 seconds
Started Jul 31 06:38:02 PM PDT 24
Finished Jul 31 06:40:41 PM PDT 24
Peak memory 209804 kb
Host smart-fa82e10b-4e26-4b47-ac11-29103bf6029c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844853180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1844853180
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3623712671
Short name T92
Test name
Test status
Simulation time 537929849475 ps
CPU time 162.34 seconds
Started Jul 31 06:46:21 PM PDT 24
Finished Jul 31 06:49:03 PM PDT 24
Peak memory 201472 kb
Host smart-b36df572-d2b4-4b89-b263-104e11447743
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623712671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3623712671
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2166835757
Short name T104
Test name
Test status
Simulation time 146340565893 ps
CPU time 163.07 seconds
Started Jul 31 06:51:03 PM PDT 24
Finished Jul 31 06:53:46 PM PDT 24
Peak memory 209764 kb
Host smart-2aa86319-6e15-4fed-9712-99ffe06f911a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166835757 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2166835757
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3463523940
Short name T257
Test name
Test status
Simulation time 198932309388 ps
CPU time 318.24 seconds
Started Jul 31 06:37:43 PM PDT 24
Finished Jul 31 06:43:01 PM PDT 24
Peak memory 201460 kb
Host smart-95ee1518-08ae-475c-a4ce-ff67e76f1384
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463523940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3463523940
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1696491056
Short name T96
Test name
Test status
Simulation time 165792876609 ps
CPU time 102.71 seconds
Started Jul 31 06:43:26 PM PDT 24
Finished Jul 31 06:45:09 PM PDT 24
Peak memory 201448 kb
Host smart-6f59eda4-4b71-4b9b-bd47-5b2dc5e1b3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696491056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1696491056
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.411332685
Short name T269
Test name
Test status
Simulation time 167544000301 ps
CPU time 186.7 seconds
Started Jul 31 06:43:25 PM PDT 24
Finished Jul 31 06:46:31 PM PDT 24
Peak memory 201460 kb
Host smart-8630c392-0b9b-49f1-88f1-496e6c99e0b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411332685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.411332685
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3658398993
Short name T161
Test name
Test status
Simulation time 342950242686 ps
CPU time 794.87 seconds
Started Jul 31 06:44:21 PM PDT 24
Finished Jul 31 06:57:36 PM PDT 24
Peak memory 201512 kb
Host smart-72512647-61ff-4242-a77a-3b8fd16d604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658398993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3658398993
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4180136516
Short name T147
Test name
Test status
Simulation time 485581367473 ps
CPU time 587.71 seconds
Started Jul 31 06:50:44 PM PDT 24
Finished Jul 31 07:00:32 PM PDT 24
Peak memory 201420 kb
Host smart-23f79497-60fc-48e7-80cb-d7d4cf7753d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180136516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4180136516
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4275542030
Short name T54
Test name
Test status
Simulation time 9456353470 ps
CPU time 38.82 seconds
Started Jul 31 06:44:27 PM PDT 24
Finished Jul 31 06:45:06 PM PDT 24
Peak memory 210216 kb
Host smart-3cf138d2-7b03-4eb0-9a43-d114a6f60b26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275542030 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4275542030
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2732220328
Short name T216
Test name
Test status
Simulation time 163275376445 ps
CPU time 324.19 seconds
Started Jul 31 06:48:11 PM PDT 24
Finished Jul 31 06:53:36 PM PDT 24
Peak memory 210160 kb
Host smart-1d2666f9-afe5-436e-b361-e60cb45ae7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732220328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2732220328
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1285521047
Short name T319
Test name
Test status
Simulation time 180470553167 ps
CPU time 207.24 seconds
Started Jul 31 06:50:32 PM PDT 24
Finished Jul 31 06:53:59 PM PDT 24
Peak memory 201404 kb
Host smart-6ee4e767-f5c7-409e-9539-768f8e9d90d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285521047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1285521047
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2076112899
Short name T334
Test name
Test status
Simulation time 545467759165 ps
CPU time 473.06 seconds
Started Jul 31 06:40:36 PM PDT 24
Finished Jul 31 06:48:29 PM PDT 24
Peak memory 201440 kb
Host smart-a5c8a2bc-9bb3-488c-9c08-a56984db4e77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076112899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2076112899
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3256105395
Short name T309
Test name
Test status
Simulation time 403949795412 ps
CPU time 779.11 seconds
Started Jul 31 06:40:56 PM PDT 24
Finished Jul 31 06:53:55 PM PDT 24
Peak memory 201460 kb
Host smart-fb59b866-49b4-4317-bac4-24cd7c8bdb30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256105395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3256105395
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2487331626
Short name T298
Test name
Test status
Simulation time 360168150014 ps
CPU time 408.13 seconds
Started Jul 31 06:42:06 PM PDT 24
Finished Jul 31 06:48:54 PM PDT 24
Peak memory 201528 kb
Host smart-27be305c-2467-4647-9131-fce0a60982d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487331626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2487331626
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4120045775
Short name T56
Test name
Test status
Simulation time 19045423851 ps
CPU time 35.05 seconds
Started Jul 31 06:42:22 PM PDT 24
Finished Jul 31 06:42:57 PM PDT 24
Peak memory 210812 kb
Host smart-f56d4e8a-a342-43f9-ba16-acd0170a551b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120045775 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4120045775
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.178665153
Short name T299
Test name
Test status
Simulation time 326262181974 ps
CPU time 348.72 seconds
Started Jul 31 06:42:38 PM PDT 24
Finished Jul 31 06:48:27 PM PDT 24
Peak memory 201484 kb
Host smart-138df1c7-90c0-460a-ac56-b17ce5b1bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178665153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.178665153
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2252783218
Short name T217
Test name
Test status
Simulation time 112523412881 ps
CPU time 558.7 seconds
Started Jul 31 06:45:47 PM PDT 24
Finished Jul 31 06:55:06 PM PDT 24
Peak memory 210036 kb
Host smart-8faaa949-535c-4dc8-b38a-0e976f219bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252783218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2252783218
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.443533829
Short name T320
Test name
Test status
Simulation time 102222703080 ps
CPU time 67.51 seconds
Started Jul 31 06:49:46 PM PDT 24
Finished Jul 31 06:50:54 PM PDT 24
Peak memory 201532 kb
Host smart-5d7aeace-b355-42c2-a1a1-1e8562082467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443533829 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.443533829
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.58467387
Short name T284
Test name
Test status
Simulation time 483878852088 ps
CPU time 1154.73 seconds
Started Jul 31 06:51:36 PM PDT 24
Finished Jul 31 07:10:51 PM PDT 24
Peak memory 201516 kb
Host smart-c95df22a-1d02-43d7-9040-3a8abe74e41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58467387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.58467387
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3197281465
Short name T180
Test name
Test status
Simulation time 497591464121 ps
CPU time 289.57 seconds
Started Jul 31 06:38:52 PM PDT 24
Finished Jul 31 06:43:42 PM PDT 24
Peak memory 201448 kb
Host smart-9828edb9-fd3f-4b91-8916-779c9fd6a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197281465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3197281465
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1352695349
Short name T114
Test name
Test status
Simulation time 1733276657195 ps
CPU time 397.79 seconds
Started Jul 31 06:40:21 PM PDT 24
Finished Jul 31 06:46:59 PM PDT 24
Peak memory 210196 kb
Host smart-0d707fd4-99af-4106-81a5-71f25e10e20c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352695349 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1352695349
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1141388013
Short name T192
Test name
Test status
Simulation time 397090589973 ps
CPU time 138.41 seconds
Started Jul 31 06:43:52 PM PDT 24
Finished Jul 31 06:46:11 PM PDT 24
Peak memory 201516 kb
Host smart-959a3e27-e927-43f7-b64f-3259f3f2b467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141388013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1141388013
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1526664220
Short name T277
Test name
Test status
Simulation time 734451751965 ps
CPU time 1061.53 seconds
Started Jul 31 06:46:32 PM PDT 24
Finished Jul 31 07:04:13 PM PDT 24
Peak memory 201476 kb
Host smart-cda4770b-cc28-4dc3-8fe4-689109b75f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526664220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1526664220
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1826824437
Short name T119
Test name
Test status
Simulation time 332466483185 ps
CPU time 185.85 seconds
Started Jul 31 06:46:39 PM PDT 24
Finished Jul 31 06:49:45 PM PDT 24
Peak memory 201484 kb
Host smart-4b4a33c4-653c-49fa-aa0c-fd205c636fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826824437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1826824437
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2991815012
Short name T345
Test name
Test status
Simulation time 88297202667 ps
CPU time 425.36 seconds
Started Jul 31 06:47:11 PM PDT 24
Finished Jul 31 06:54:17 PM PDT 24
Peak memory 201836 kb
Host smart-c4e45c21-27b8-4afb-b5b6-7c1c4f0ec51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991815012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2991815012
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1271891039
Short name T318
Test name
Test status
Simulation time 167097224358 ps
CPU time 41.73 seconds
Started Jul 31 06:47:29 PM PDT 24
Finished Jul 31 06:48:11 PM PDT 24
Peak memory 201452 kb
Host smart-1a4ad1bc-e0fc-46fa-91af-092507a48f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271891039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1271891039
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4239735485
Short name T777
Test name
Test status
Simulation time 407751525979 ps
CPU time 295.43 seconds
Started Jul 31 06:49:34 PM PDT 24
Finished Jul 31 06:54:29 PM PDT 24
Peak memory 201904 kb
Host smart-be5eeff1-9c88-4238-8dd8-d1c026f155de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239735485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4239735485
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1971280673
Short name T317
Test name
Test status
Simulation time 324881703607 ps
CPU time 698.05 seconds
Started Jul 31 06:50:26 PM PDT 24
Finished Jul 31 07:02:04 PM PDT 24
Peak memory 201432 kb
Host smart-72fba3e6-8295-4e6a-bf28-4be7b1744889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971280673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1971280673
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2272326135
Short name T304
Test name
Test status
Simulation time 200188521596 ps
CPU time 121.99 seconds
Started Jul 31 06:52:28 PM PDT 24
Finished Jul 31 06:54:30 PM PDT 24
Peak memory 201452 kb
Host smart-c500bc23-7421-4027-8a67-a9a056d56cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272326135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2272326135
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1562221825
Short name T71
Test name
Test status
Simulation time 8471411175 ps
CPU time 22.58 seconds
Started Jul 31 05:18:49 PM PDT 24
Finished Jul 31 05:19:12 PM PDT 24
Peak memory 201652 kb
Host smart-7e59eaaf-c121-42c4-8c93-f8bad8e2cd82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562221825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1562221825
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1053609053
Short name T329
Test name
Test status
Simulation time 326746820514 ps
CPU time 201.65 seconds
Started Jul 31 06:41:16 PM PDT 24
Finished Jul 31 06:44:37 PM PDT 24
Peak memory 201456 kb
Host smart-e461bd0b-b7c5-4204-ae35-1c19bb637196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053609053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1053609053
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3097821904
Short name T352
Test name
Test status
Simulation time 402276248549 ps
CPU time 1492.76 seconds
Started Jul 31 06:41:34 PM PDT 24
Finished Jul 31 07:06:27 PM PDT 24
Peak memory 218292 kb
Host smart-34aadfea-aeb9-4624-8d2b-a2c94c3d5bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097821904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3097821904
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1296581402
Short name T656
Test name
Test status
Simulation time 399107594926 ps
CPU time 442.66 seconds
Started Jul 31 06:42:12 PM PDT 24
Finished Jul 31 06:49:34 PM PDT 24
Peak memory 201460 kb
Host smart-31e05c3c-b2fc-4968-9426-7573e4501ab1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296581402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1296581402
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3193372701
Short name T322
Test name
Test status
Simulation time 352183716556 ps
CPU time 217.81 seconds
Started Jul 31 06:43:05 PM PDT 24
Finished Jul 31 06:46:43 PM PDT 24
Peak memory 201456 kb
Host smart-cf7d0822-437d-4c88-b9eb-32f0ea259b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193372701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3193372701
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3344033760
Short name T258
Test name
Test status
Simulation time 486203408869 ps
CPU time 1167.83 seconds
Started Jul 31 06:43:46 PM PDT 24
Finished Jul 31 07:03:14 PM PDT 24
Peak memory 201452 kb
Host smart-cb401ce8-c232-4a2b-8b3a-21d13985247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344033760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3344033760
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.871650775
Short name T256
Test name
Test status
Simulation time 204083398556 ps
CPU time 430.46 seconds
Started Jul 31 06:43:58 PM PDT 24
Finished Jul 31 06:51:08 PM PDT 24
Peak memory 201488 kb
Host smart-78ffa4ce-e1c6-4b16-9b80-bfcaef17e91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871650775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
871650775
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1223042278
Short name T282
Test name
Test status
Simulation time 327080536505 ps
CPU time 220.95 seconds
Started Jul 31 06:44:18 PM PDT 24
Finished Jul 31 06:47:59 PM PDT 24
Peak memory 201548 kb
Host smart-1603ed9c-6619-4e26-a54b-548434cbc225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223042278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1223042278
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4107886159
Short name T274
Test name
Test status
Simulation time 495994491090 ps
CPU time 275.17 seconds
Started Jul 31 06:44:38 PM PDT 24
Finished Jul 31 06:49:13 PM PDT 24
Peak memory 201404 kb
Host smart-75d30120-8e37-4cf1-bb11-5f82a8ab5ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107886159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4107886159
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.4152874801
Short name T295
Test name
Test status
Simulation time 345563796542 ps
CPU time 217.05 seconds
Started Jul 31 06:47:48 PM PDT 24
Finished Jul 31 06:51:25 PM PDT 24
Peak memory 201488 kb
Host smart-373a311b-2757-46b5-99ad-20a29bd85078
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152874801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.4152874801
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4019181965
Short name T330
Test name
Test status
Simulation time 417753359699 ps
CPU time 146.75 seconds
Started Jul 31 06:48:27 PM PDT 24
Finished Jul 31 06:50:54 PM PDT 24
Peak memory 210296 kb
Host smart-c4073d9a-5611-4a9c-80e5-19c239506d44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019181965 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4019181965
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.647031851
Short name T193
Test name
Test status
Simulation time 580170198742 ps
CPU time 107.44 seconds
Started Jul 31 06:48:38 PM PDT 24
Finished Jul 31 06:50:26 PM PDT 24
Peak memory 201416 kb
Host smart-80d64cff-75a1-4535-8fe8-d27737ddbeb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647031851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.647031851
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2683094877
Short name T296
Test name
Test status
Simulation time 524126271522 ps
CPU time 640.48 seconds
Started Jul 31 06:49:29 PM PDT 24
Finished Jul 31 07:00:11 PM PDT 24
Peak memory 201428 kb
Host smart-34c67e17-0c1a-4982-aa7a-bdd1d77d4964
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683094877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2683094877
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2581812889
Short name T59
Test name
Test status
Simulation time 393824009945 ps
CPU time 833.98 seconds
Started Jul 31 06:49:40 PM PDT 24
Finished Jul 31 07:03:35 PM PDT 24
Peak memory 201568 kb
Host smart-51bcbc6a-eef0-4874-9d75-21ce94953134
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581812889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2581812889
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.162053009
Short name T35
Test name
Test status
Simulation time 38924543414 ps
CPU time 57.36 seconds
Started Jul 31 06:51:22 PM PDT 24
Finished Jul 31 06:52:20 PM PDT 24
Peak memory 211532 kb
Host smart-0ac53990-ec53-4e1a-a3d8-0b3441a19507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162053009 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.162053009
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2143501432
Short name T283
Test name
Test status
Simulation time 613220061290 ps
CPU time 631.42 seconds
Started Jul 31 06:52:37 PM PDT 24
Finished Jul 31 07:03:08 PM PDT 24
Peak memory 201464 kb
Host smart-cd2775d8-344e-47c1-be8f-e484ebb2baa7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143501432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2143501432
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3458400469
Short name T123
Test name
Test status
Simulation time 745741639 ps
CPU time 2.13 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:17 PM PDT 24
Peak memory 201552 kb
Host smart-3e54b988-81d0-4ca7-adad-da247b7f6fb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458400469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3458400469
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1369074805
Short name T854
Test name
Test status
Simulation time 1234531987 ps
CPU time 3.35 seconds
Started Jul 31 05:18:32 PM PDT 24
Finished Jul 31 05:18:35 PM PDT 24
Peak memory 201336 kb
Host smart-52d02648-022c-4236-a296-57ab2f36f3d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369074805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1369074805
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1417418147
Short name T102
Test name
Test status
Simulation time 429058233 ps
CPU time 1.76 seconds
Started Jul 31 05:18:22 PM PDT 24
Finished Jul 31 05:18:24 PM PDT 24
Peak memory 201356 kb
Host smart-7ec2b16e-cbb7-4347-99a4-7b3369a48931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417418147 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1417418147
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3593565114
Short name T130
Test name
Test status
Simulation time 515351069 ps
CPU time 1.53 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 201308 kb
Host smart-90d2ce33-3668-48ee-baea-6373896f835c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593565114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3593565114
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.214072040
Short name T862
Test name
Test status
Simulation time 513779105 ps
CPU time 0.74 seconds
Started Jul 31 05:18:25 PM PDT 24
Finished Jul 31 05:18:26 PM PDT 24
Peak memory 201312 kb
Host smart-b42579d1-8408-4b14-b578-88bddeadc37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214072040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.214072040
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1038434173
Short name T828
Test name
Test status
Simulation time 2244901298 ps
CPU time 2 seconds
Started Jul 31 05:18:24 PM PDT 24
Finished Jul 31 05:18:26 PM PDT 24
Peak memory 201408 kb
Host smart-0f96780c-e599-4fa9-9a4c-7b593656bbe8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038434173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1038434173
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2541492075
Short name T842
Test name
Test status
Simulation time 555811941 ps
CPU time 2.5 seconds
Started Jul 31 05:18:19 PM PDT 24
Finished Jul 31 05:18:22 PM PDT 24
Peak memory 201596 kb
Host smart-fce753a0-b1d4-44d5-bb41-25ae0a03521f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541492075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2541492075
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.776184782
Short name T89
Test name
Test status
Simulation time 8760657087 ps
CPU time 7.3 seconds
Started Jul 31 05:18:05 PM PDT 24
Finished Jul 31 05:18:13 PM PDT 24
Peak memory 201624 kb
Host smart-f693e446-06a3-47e4-8e31-9c2318cef617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776184782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.776184782
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2548816860
Short name T132
Test name
Test status
Simulation time 711026132 ps
CPU time 3.09 seconds
Started Jul 31 05:18:13 PM PDT 24
Finished Jul 31 05:18:16 PM PDT 24
Peak memory 201544 kb
Host smart-532c98a2-32c1-44fe-8d04-669c6816b6cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548816860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2548816860
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1124047985
Short name T136
Test name
Test status
Simulation time 51532310029 ps
CPU time 47.34 seconds
Started Jul 31 05:18:08 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201608 kb
Host smart-12edab9f-c666-4103-911d-d2fa23239f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124047985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1124047985
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2503540274
Short name T907
Test name
Test status
Simulation time 1244785634 ps
CPU time 1.61 seconds
Started Jul 31 05:18:19 PM PDT 24
Finished Jul 31 05:18:21 PM PDT 24
Peak memory 201368 kb
Host smart-859ea9a1-61e7-4cd7-86e4-3330de2d4444
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503540274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2503540274
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1681912627
Short name T888
Test name
Test status
Simulation time 320984196 ps
CPU time 1.55 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:33 PM PDT 24
Peak memory 201512 kb
Host smart-75e98b89-9025-4a35-91e2-90f8b591ab10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681912627 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1681912627
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1643828296
Short name T134
Test name
Test status
Simulation time 407005863 ps
CPU time 1.6 seconds
Started Jul 31 05:18:11 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 201304 kb
Host smart-8d07324b-4000-4f16-9d54-dac5316ed4de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643828296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1643828296
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3898191771
Short name T877
Test name
Test status
Simulation time 343202513 ps
CPU time 1.36 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 201376 kb
Host smart-3edea1e3-5478-4c01-a3cc-5149254b1d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898191771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3898191771
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.456217003
Short name T811
Test name
Test status
Simulation time 4211979306 ps
CPU time 16.29 seconds
Started Jul 31 05:18:29 PM PDT 24
Finished Jul 31 05:18:45 PM PDT 24
Peak memory 201628 kb
Host smart-f8c0f4fc-949f-4e15-a598-03d69aa3a5f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456217003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.456217003
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1786533390
Short name T87
Test name
Test status
Simulation time 741591729 ps
CPU time 2.32 seconds
Started Jul 31 05:18:10 PM PDT 24
Finished Jul 31 05:18:12 PM PDT 24
Peak memory 201556 kb
Host smart-8b575875-dc7e-41a5-9780-933d9222e689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786533390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1786533390
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.539057944
Short name T884
Test name
Test status
Simulation time 4457038370 ps
CPU time 4.25 seconds
Started Jul 31 05:18:34 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 201636 kb
Host smart-b1d3f486-edba-44be-82e1-040857632160
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539057944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.539057944
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2628067166
Short name T874
Test name
Test status
Simulation time 402121663 ps
CPU time 1.69 seconds
Started Jul 31 05:18:43 PM PDT 24
Finished Jul 31 05:18:45 PM PDT 24
Peak memory 201448 kb
Host smart-93eee94d-f95b-4280-9683-b4a1ae60e664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628067166 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2628067166
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3327701043
Short name T910
Test name
Test status
Simulation time 356547211 ps
CPU time 0.89 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201304 kb
Host smart-ac35967f-1d43-42c4-8d81-996955a3a891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327701043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3327701043
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1006560433
Short name T880
Test name
Test status
Simulation time 456365281 ps
CPU time 1.68 seconds
Started Jul 31 05:18:38 PM PDT 24
Finished Jul 31 05:18:40 PM PDT 24
Peak memory 201356 kb
Host smart-9059a347-6fba-4411-8a32-52c95c4775b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006560433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1006560433
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1644902176
Short name T803
Test name
Test status
Simulation time 628058581 ps
CPU time 2.47 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 201680 kb
Host smart-2e370817-2e78-4302-9982-d057a872fa8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644902176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1644902176
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3341713452
Short name T342
Test name
Test status
Simulation time 4796776410 ps
CPU time 4.18 seconds
Started Jul 31 05:18:38 PM PDT 24
Finished Jul 31 05:18:43 PM PDT 24
Peak memory 201620 kb
Host smart-65ab1f0c-aec8-49b4-b4cb-704dbc6338f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341713452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3341713452
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1333353511
Short name T813
Test name
Test status
Simulation time 538224809 ps
CPU time 1.12 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201536 kb
Host smart-0fc49fb8-dfa2-4b2a-8568-1417b09292c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333353511 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1333353511
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3125062230
Short name T131
Test name
Test status
Simulation time 428562773 ps
CPU time 1.62 seconds
Started Jul 31 05:19:00 PM PDT 24
Finished Jul 31 05:19:02 PM PDT 24
Peak memory 201284 kb
Host smart-1a44d616-2660-4577-9d55-1e8c8b1a13fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125062230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3125062230
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.751166795
Short name T835
Test name
Test status
Simulation time 368152229 ps
CPU time 1.41 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201272 kb
Host smart-1974dcea-f75e-4fe7-ac38-f4c59dc6050d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751166795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.751166795
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.272021805
Short name T140
Test name
Test status
Simulation time 4520757897 ps
CPU time 10.27 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:18:56 PM PDT 24
Peak memory 201612 kb
Host smart-0a744669-05fa-4bd9-892f-f07489c31323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272021805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.272021805
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2704004265
Short name T822
Test name
Test status
Simulation time 817575283 ps
CPU time 1.51 seconds
Started Jul 31 05:18:51 PM PDT 24
Finished Jul 31 05:18:52 PM PDT 24
Peak memory 201588 kb
Host smart-ecf27029-38b7-4b1b-a1cd-28e73d25814e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704004265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2704004265
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.910876632
Short name T894
Test name
Test status
Simulation time 549380320 ps
CPU time 1.46 seconds
Started Jul 31 05:18:39 PM PDT 24
Finished Jul 31 05:18:40 PM PDT 24
Peak memory 201496 kb
Host smart-ccd90039-a151-4081-9b81-3c1b53f4d954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910876632 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.910876632
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3704460373
Short name T912
Test name
Test status
Simulation time 500550726 ps
CPU time 1.05 seconds
Started Jul 31 05:18:50 PM PDT 24
Finished Jul 31 05:18:51 PM PDT 24
Peak memory 201340 kb
Host smart-a8b2d9ad-c673-4a29-adc4-3c8bd2b09e1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704460373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3704460373
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3209312323
Short name T891
Test name
Test status
Simulation time 456417129 ps
CPU time 1.53 seconds
Started Jul 31 05:18:44 PM PDT 24
Finished Jul 31 05:18:45 PM PDT 24
Peak memory 201372 kb
Host smart-66ce4414-167d-421d-af7d-653b7c2ba02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209312323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3209312323
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3048020349
Short name T67
Test name
Test status
Simulation time 1930737404 ps
CPU time 6.61 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:54 PM PDT 24
Peak memory 201340 kb
Host smart-513f9beb-2c55-43d5-8bab-0a5af0be4fe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048020349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3048020349
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1437279681
Short name T844
Test name
Test status
Simulation time 765377649 ps
CPU time 2.89 seconds
Started Jul 31 05:19:04 PM PDT 24
Finished Jul 31 05:19:07 PM PDT 24
Peak memory 209828 kb
Host smart-df7d7b94-4cf1-4498-a224-d785204bc1c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437279681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1437279681
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3908433061
Short name T341
Test name
Test status
Simulation time 9205151745 ps
CPU time 5.34 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:18:54 PM PDT 24
Peak memory 201636 kb
Host smart-1b0873d8-4646-4618-a9c8-92200ebac26e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908433061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3908433061
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3523634982
Short name T879
Test name
Test status
Simulation time 549491851 ps
CPU time 1.3 seconds
Started Jul 31 05:18:52 PM PDT 24
Finished Jul 31 05:18:53 PM PDT 24
Peak memory 201456 kb
Host smart-acdb65b5-ecd2-4a25-bf72-622be70cdf38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523634982 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3523634982
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4260898618
Short name T137
Test name
Test status
Simulation time 562715281 ps
CPU time 1.13 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201284 kb
Host smart-98ece02f-3e29-47a9-9a08-eb8c38ed8c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260898618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4260898618
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1193642129
Short name T825
Test name
Test status
Simulation time 355548966 ps
CPU time 0.75 seconds
Started Jul 31 05:18:51 PM PDT 24
Finished Jul 31 05:18:51 PM PDT 24
Peak memory 201312 kb
Host smart-32ed1f0d-cf15-4889-90de-adfb17f6fd25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193642129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1193642129
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2915940284
Short name T68
Test name
Test status
Simulation time 4513075398 ps
CPU time 4.33 seconds
Started Jul 31 05:18:40 PM PDT 24
Finished Jul 31 05:18:44 PM PDT 24
Peak memory 201472 kb
Host smart-a28cf98a-4f8f-4ed5-817a-e914fab1df78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915940284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2915940284
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.292054111
Short name T863
Test name
Test status
Simulation time 1830970665 ps
CPU time 3.13 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:51 PM PDT 24
Peak memory 210912 kb
Host smart-930940f7-853d-4a58-802e-b0879aaf4e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292054111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.292054111
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3076798227
Short name T816
Test name
Test status
Simulation time 4459557579 ps
CPU time 6.66 seconds
Started Jul 31 05:18:57 PM PDT 24
Finished Jul 31 05:19:04 PM PDT 24
Peak memory 201684 kb
Host smart-cc211baf-dcac-46ae-8008-cc944e3a9ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076798227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3076798227
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.121094951
Short name T883
Test name
Test status
Simulation time 463459232 ps
CPU time 1.02 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 201500 kb
Host smart-eed04215-3447-4e21-93d8-2dcccfba9e92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121094951 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.121094951
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.907896269
Short name T126
Test name
Test status
Simulation time 430648590 ps
CPU time 1.82 seconds
Started Jul 31 05:18:53 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201340 kb
Host smart-ba1b7155-4839-46d2-be3b-9682569fe98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907896269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.907896269
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4217523025
Short name T820
Test name
Test status
Simulation time 520389664 ps
CPU time 0.93 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:18:47 PM PDT 24
Peak memory 201320 kb
Host smart-fc6fbe12-eb06-4005-ba63-70c24eaae4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217523025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.4217523025
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1742521637
Short name T834
Test name
Test status
Simulation time 2031333551 ps
CPU time 2.81 seconds
Started Jul 31 05:18:42 PM PDT 24
Finished Jul 31 05:18:45 PM PDT 24
Peak memory 201308 kb
Host smart-4ed99746-68a1-4adf-9e0c-c66044cad7b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742521637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1742521637
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4121251393
Short name T904
Test name
Test status
Simulation time 8603321433 ps
CPU time 11.54 seconds
Started Jul 31 05:18:44 PM PDT 24
Finished Jul 31 05:18:56 PM PDT 24
Peak memory 201720 kb
Host smart-e3acece4-1e17-472d-a3ad-b72fde8f62bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121251393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4121251393
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.694850802
Short name T882
Test name
Test status
Simulation time 329529077 ps
CPU time 1.53 seconds
Started Jul 31 05:18:32 PM PDT 24
Finished Jul 31 05:18:33 PM PDT 24
Peak memory 201640 kb
Host smart-ab26e9e6-30f2-49b9-aa05-0582ada132da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694850802 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.694850802
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.504257456
Short name T129
Test name
Test status
Simulation time 315611880 ps
CPU time 1.41 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:18:49 PM PDT 24
Peak memory 201224 kb
Host smart-d8196002-4c8a-4931-8000-8a82ba53f657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504257456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.504257456
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.516541676
Short name T808
Test name
Test status
Simulation time 531982374 ps
CPU time 0.91 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201404 kb
Host smart-9dc15e90-2a41-4ba5-999f-4b7cbb0b17a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516541676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.516541676
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3997200787
Short name T837
Test name
Test status
Simulation time 5207920708 ps
CPU time 4.03 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:18:52 PM PDT 24
Peak memory 201608 kb
Host smart-54854f49-da9c-46d3-85ee-b428aebabd3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997200787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3997200787
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1768656022
Short name T836
Test name
Test status
Simulation time 819985613 ps
CPU time 2.75 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:18:49 PM PDT 24
Peak memory 217512 kb
Host smart-b29c51f1-a0f2-4e7a-bf28-62222b24d500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768656022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1768656022
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.357261317
Short name T821
Test name
Test status
Simulation time 4141893904 ps
CPU time 4.48 seconds
Started Jul 31 05:18:51 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201628 kb
Host smart-23ea50ba-f22b-4a41-a7a0-54fc530c0257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357261317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.357261317
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3631863229
Short name T101
Test name
Test status
Simulation time 354730086 ps
CPU time 1.03 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:56 PM PDT 24
Peak memory 201504 kb
Host smart-b07dc3df-7edb-4d43-9091-bc38e2bf9c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631863229 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3631863229
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.150319053
Short name T859
Test name
Test status
Simulation time 383941860 ps
CPU time 1.19 seconds
Started Jul 31 05:18:53 PM PDT 24
Finished Jul 31 05:18:54 PM PDT 24
Peak memory 201316 kb
Host smart-96e170c9-3cbe-424a-8668-1f5fb6ef6295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150319053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.150319053
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1579675990
Short name T857
Test name
Test status
Simulation time 393248101 ps
CPU time 1.47 seconds
Started Jul 31 05:18:55 PM PDT 24
Finished Jul 31 05:18:56 PM PDT 24
Peak memory 201504 kb
Host smart-faf76c0a-1bcd-4892-b9bc-344d0cbe54cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579675990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1579675990
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.378426024
Short name T896
Test name
Test status
Simulation time 1712542014 ps
CPU time 2.05 seconds
Started Jul 31 05:19:02 PM PDT 24
Finished Jul 31 05:19:05 PM PDT 24
Peak memory 201304 kb
Host smart-2eb87158-176a-438b-af89-671a9e440c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378426024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.378426024
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2197024303
Short name T864
Test name
Test status
Simulation time 517091328 ps
CPU time 2.55 seconds
Started Jul 31 05:18:41 PM PDT 24
Finished Jul 31 05:18:44 PM PDT 24
Peak memory 201672 kb
Host smart-659ec3d5-70aa-48aa-b305-365882c6a195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197024303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2197024303
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3745749730
Short name T892
Test name
Test status
Simulation time 8597057875 ps
CPU time 11.83 seconds
Started Jul 31 05:18:45 PM PDT 24
Finished Jul 31 05:18:57 PM PDT 24
Peak memory 201640 kb
Host smart-dddd94d1-8c76-40b8-a2ee-2493174315b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745749730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3745749730
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1519505980
Short name T76
Test name
Test status
Simulation time 591864742 ps
CPU time 1.1 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:49 PM PDT 24
Peak memory 201456 kb
Host smart-c854ffbc-1464-4af0-96f1-915bec0eb384
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519505980 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1519505980
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1155313871
Short name T847
Test name
Test status
Simulation time 492659096 ps
CPU time 1.03 seconds
Started Jul 31 05:18:49 PM PDT 24
Finished Jul 31 05:18:50 PM PDT 24
Peak memory 201340 kb
Host smart-de416624-abce-433c-b15e-e84c6c17920c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155313871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1155313871
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3546854571
Short name T915
Test name
Test status
Simulation time 505658597 ps
CPU time 0.89 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201356 kb
Host smart-a3b0d52a-53d6-4d11-b8d4-46e60ec1a4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546854571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3546854571
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1161819525
Short name T809
Test name
Test status
Simulation time 2541365973 ps
CPU time 9.58 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:19:03 PM PDT 24
Peak memory 201620 kb
Host smart-7a23bd09-d056-48a8-8aaf-a6d19d66fd4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161819525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1161819525
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4177917399
Short name T871
Test name
Test status
Simulation time 582394959 ps
CPU time 1.76 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:49 PM PDT 24
Peak memory 201624 kb
Host smart-dacccd86-1fe8-45dc-8247-861cb027c46e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177917399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.4177917399
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2152864602
Short name T814
Test name
Test status
Simulation time 8953503026 ps
CPU time 4.35 seconds
Started Jul 31 05:19:01 PM PDT 24
Finished Jul 31 05:19:06 PM PDT 24
Peak memory 201688 kb
Host smart-e7ed944b-e030-4a09-b63f-4e5fcc1655e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152864602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2152864602
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.7323200
Short name T833
Test name
Test status
Simulation time 528771058 ps
CPU time 1.27 seconds
Started Jul 31 05:18:49 PM PDT 24
Finished Jul 31 05:18:50 PM PDT 24
Peak memory 201484 kb
Host smart-d5f9ccbc-e6ef-4b80-a638-b88d1955a963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7323200 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.7323200
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4240814641
Short name T909
Test name
Test status
Simulation time 399328837 ps
CPU time 1.29 seconds
Started Jul 31 05:18:41 PM PDT 24
Finished Jul 31 05:18:42 PM PDT 24
Peak memory 201364 kb
Host smart-5a803b42-c541-4ca9-a8c5-dbd52a7baee2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240814641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4240814641
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3734823301
Short name T866
Test name
Test status
Simulation time 538255668 ps
CPU time 0.94 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201324 kb
Host smart-3b1771c7-26e6-445d-8452-cc9bf537b2df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734823301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3734823301
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.887480422
Short name T141
Test name
Test status
Simulation time 2276406105 ps
CPU time 4.36 seconds
Started Jul 31 05:18:56 PM PDT 24
Finished Jul 31 05:19:00 PM PDT 24
Peak memory 201344 kb
Host smart-5fe149f4-1246-4a5d-9547-71a24dd8c738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887480422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.887480422
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1888562229
Short name T85
Test name
Test status
Simulation time 421687187 ps
CPU time 1.96 seconds
Started Jul 31 05:19:07 PM PDT 24
Finished Jul 31 05:19:09 PM PDT 24
Peak memory 201696 kb
Host smart-1b4be924-a38a-4fc2-94ba-8ee007e4b478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888562229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1888562229
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1541070684
Short name T72
Test name
Test status
Simulation time 8122846356 ps
CPU time 11.17 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:18:59 PM PDT 24
Peak memory 201680 kb
Host smart-aea27585-fb0c-44f2-9f00-3c3ad4d74aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541070684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1541070684
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3149744880
Short name T829
Test name
Test status
Simulation time 358072421 ps
CPU time 1.7 seconds
Started Jul 31 05:18:45 PM PDT 24
Finished Jul 31 05:18:47 PM PDT 24
Peak memory 201436 kb
Host smart-8c643f83-ab9e-4fb4-a4e2-aeeb8a84daac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149744880 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3149744880
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4032672485
Short name T865
Test name
Test status
Simulation time 421004688 ps
CPU time 0.9 seconds
Started Jul 31 05:18:52 PM PDT 24
Finished Jul 31 05:18:53 PM PDT 24
Peak memory 201376 kb
Host smart-0935112e-9d3f-43d8-8965-4f0269950f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032672485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4032672485
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1509734216
Short name T840
Test name
Test status
Simulation time 582589455 ps
CPU time 0.76 seconds
Started Jul 31 05:18:50 PM PDT 24
Finished Jul 31 05:18:51 PM PDT 24
Peak memory 201248 kb
Host smart-90ec829a-795d-4e16-8aad-b5816690f83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509734216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1509734216
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.719476606
Short name T832
Test name
Test status
Simulation time 3091299614 ps
CPU time 1.38 seconds
Started Jul 31 05:19:02 PM PDT 24
Finished Jul 31 05:19:04 PM PDT 24
Peak memory 201480 kb
Host smart-84005391-9a85-40fc-a537-d868857415ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719476606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.719476606
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2417159580
Short name T846
Test name
Test status
Simulation time 489951515 ps
CPU time 2.41 seconds
Started Jul 31 05:18:55 PM PDT 24
Finished Jul 31 05:18:57 PM PDT 24
Peak memory 201668 kb
Host smart-849cf5d9-e96d-44dd-8207-4c943f278556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417159580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2417159580
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3105832600
Short name T343
Test name
Test status
Simulation time 8729062181 ps
CPU time 22.62 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:19:11 PM PDT 24
Peak memory 201628 kb
Host smart-2d14a104-55e9-4134-bf79-dcc11eae2823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105832600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3105832600
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.342047856
Short name T128
Test name
Test status
Simulation time 1204814774 ps
CPU time 2.48 seconds
Started Jul 31 05:18:26 PM PDT 24
Finished Jul 31 05:18:29 PM PDT 24
Peak memory 201592 kb
Host smart-8c379263-22ef-41b0-9ab7-5e511163763e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342047856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.342047856
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2491083564
Short name T133
Test name
Test status
Simulation time 26820558617 ps
CPU time 19.91 seconds
Started Jul 31 05:18:22 PM PDT 24
Finished Jul 31 05:18:42 PM PDT 24
Peak memory 201636 kb
Host smart-9c670b31-226d-494d-a5f6-b5e2b85a94dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491083564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2491083564
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1529284066
Short name T851
Test name
Test status
Simulation time 861847254 ps
CPU time 2.65 seconds
Started Jul 31 05:18:26 PM PDT 24
Finished Jul 31 05:18:29 PM PDT 24
Peak memory 201364 kb
Host smart-fef53541-1676-4ee5-8d51-b9540aed54ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529284066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1529284066
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1319914984
Short name T838
Test name
Test status
Simulation time 585595642 ps
CPU time 0.87 seconds
Started Jul 31 05:18:23 PM PDT 24
Finished Jul 31 05:18:24 PM PDT 24
Peak memory 201484 kb
Host smart-734e41a6-f853-42f6-8f30-92e9e65747c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319914984 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1319914984
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3573787758
Short name T905
Test name
Test status
Simulation time 469150621 ps
CPU time 1.78 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:38 PM PDT 24
Peak memory 201368 kb
Host smart-642e730a-4777-4426-a781-6860b14883da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573787758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3573787758
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2509714423
Short name T908
Test name
Test status
Simulation time 422351723 ps
CPU time 1.65 seconds
Started Jul 31 05:18:40 PM PDT 24
Finished Jul 31 05:18:42 PM PDT 24
Peak memory 201348 kb
Host smart-b6e47aea-31bc-45f0-b788-389159f3f5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509714423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2509714423
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3121412046
Short name T906
Test name
Test status
Simulation time 1935795478 ps
CPU time 2.92 seconds
Started Jul 31 05:18:23 PM PDT 24
Finished Jul 31 05:18:26 PM PDT 24
Peak memory 201372 kb
Host smart-78bd6ade-7082-4dec-b123-c6f34a11dea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121412046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3121412046
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.295056092
Short name T82
Test name
Test status
Simulation time 596980013 ps
CPU time 3.78 seconds
Started Jul 31 05:18:45 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201688 kb
Host smart-2118b3b4-932a-428b-8edb-4242b894e6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295056092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.295056092
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2325639792
Short name T855
Test name
Test status
Simulation time 8082523529 ps
CPU time 6.33 seconds
Started Jul 31 05:18:43 PM PDT 24
Finished Jul 31 05:18:50 PM PDT 24
Peak memory 201704 kb
Host smart-fe5b5cfb-311a-40e1-9833-1a9c536e9fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325639792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2325639792
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2279639473
Short name T849
Test name
Test status
Simulation time 286429673 ps
CPU time 0.92 seconds
Started Jul 31 05:18:52 PM PDT 24
Finished Jul 31 05:18:53 PM PDT 24
Peak memory 201336 kb
Host smart-96d468a1-b9da-4dbd-9146-89ab743fc067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279639473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2279639473
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3655135281
Short name T798
Test name
Test status
Simulation time 410288349 ps
CPU time 0.73 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201356 kb
Host smart-922060f6-0b7e-4311-b917-919a5afb7738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655135281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3655135281
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1750659045
Short name T794
Test name
Test status
Simulation time 444128118 ps
CPU time 0.9 seconds
Started Jul 31 05:18:58 PM PDT 24
Finished Jul 31 05:18:59 PM PDT 24
Peak memory 201384 kb
Host smart-872a8337-3e31-433c-8fdc-5962bb842f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750659045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1750659045
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2016117231
Short name T869
Test name
Test status
Simulation time 563608025 ps
CPU time 0.99 seconds
Started Jul 31 05:19:04 PM PDT 24
Finished Jul 31 05:19:05 PM PDT 24
Peak memory 201352 kb
Host smart-21372cd3-f4d7-4491-a691-6614122da3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016117231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2016117231
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.137129485
Short name T886
Test name
Test status
Simulation time 503856077 ps
CPU time 0.91 seconds
Started Jul 31 05:19:01 PM PDT 24
Finished Jul 31 05:19:02 PM PDT 24
Peak memory 201312 kb
Host smart-8bf01295-c840-4543-a7c7-d2fc50e85c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137129485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.137129485
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2377355620
Short name T872
Test name
Test status
Simulation time 423895270 ps
CPU time 1.07 seconds
Started Jul 31 05:19:00 PM PDT 24
Finished Jul 31 05:19:02 PM PDT 24
Peak memory 201368 kb
Host smart-e4f94f50-a40d-4841-b995-10040747fa01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377355620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2377355620
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3570326594
Short name T806
Test name
Test status
Simulation time 565148395 ps
CPU time 0.81 seconds
Started Jul 31 05:18:51 PM PDT 24
Finished Jul 31 05:18:52 PM PDT 24
Peak memory 201356 kb
Host smart-73e7f41f-b7e4-40ea-8c5d-c1c39c74ac52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570326594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3570326594
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3276335541
Short name T845
Test name
Test status
Simulation time 398381426 ps
CPU time 0.96 seconds
Started Jul 31 05:18:53 PM PDT 24
Finished Jul 31 05:18:54 PM PDT 24
Peak memory 201372 kb
Host smart-ffca976f-d8da-46a6-bca9-fc81f12e1a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276335541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3276335541
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.809400210
Short name T805
Test name
Test status
Simulation time 443021170 ps
CPU time 0.82 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:37 PM PDT 24
Peak memory 201336 kb
Host smart-13c54078-3fae-46da-9257-49168894e7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809400210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.809400210
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.518772419
Short name T801
Test name
Test status
Simulation time 497207418 ps
CPU time 0.88 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201344 kb
Host smart-de08de7f-1a3b-4f05-af3d-336127d5bfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518772419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.518772419
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2020664685
Short name T858
Test name
Test status
Simulation time 844923049 ps
CPU time 1.83 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 201468 kb
Host smart-99d57e63-b1c3-40a5-b6df-ca009bcd694b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020664685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2020664685
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2258352440
Short name T135
Test name
Test status
Simulation time 16265458458 ps
CPU time 11.2 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:47 PM PDT 24
Peak memory 201464 kb
Host smart-a184fedd-8cef-45e1-a553-9a079480f65d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258352440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2258352440
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2784959217
Short name T830
Test name
Test status
Simulation time 1146812984 ps
CPU time 1.53 seconds
Started Jul 31 05:18:34 PM PDT 24
Finished Jul 31 05:18:36 PM PDT 24
Peak memory 201404 kb
Host smart-e3b46a73-13f3-4b0a-a815-f81d5e2045a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784959217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2784959217
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.358482513
Short name T911
Test name
Test status
Simulation time 447062357 ps
CPU time 1.86 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 201500 kb
Host smart-6a6dae05-70e3-4ffc-8217-aa655d7604b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358482513 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.358482513
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2205602215
Short name T125
Test name
Test status
Simulation time 393433003 ps
CPU time 1.03 seconds
Started Jul 31 05:18:25 PM PDT 24
Finished Jul 31 05:18:26 PM PDT 24
Peak memory 201368 kb
Host smart-1a87b10f-36b1-47ec-92a6-ed63e2aaa49c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205602215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2205602215
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2356904620
Short name T807
Test name
Test status
Simulation time 441775287 ps
CPU time 1.63 seconds
Started Jul 31 05:18:37 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 201272 kb
Host smart-b6a528ef-7c8e-4efb-96e4-2b4bbe46d3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356904620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2356904620
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4277526376
Short name T889
Test name
Test status
Simulation time 4772149957 ps
CPU time 3.6 seconds
Started Jul 31 05:18:32 PM PDT 24
Finished Jul 31 05:18:36 PM PDT 24
Peak memory 201588 kb
Host smart-e87baa6f-e82b-48d1-af4d-85a678d62f0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277526376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4277526376
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.815383651
Short name T84
Test name
Test status
Simulation time 1228787251 ps
CPU time 1.62 seconds
Started Jul 31 05:18:15 PM PDT 24
Finished Jul 31 05:18:17 PM PDT 24
Peak memory 201616 kb
Host smart-3ec15fd8-8963-4aa9-9de1-dae685682912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815383651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.815383651
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.9720392
Short name T826
Test name
Test status
Simulation time 3920165296 ps
CPU time 11.05 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:47 PM PDT 24
Peak memory 201560 kb
Host smart-5334c347-a8cc-4318-b4d8-db026278a81f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9720392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_
err.9720392
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2891343007
Short name T878
Test name
Test status
Simulation time 411400284 ps
CPU time 1.09 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201328 kb
Host smart-b5389577-a2c6-4254-9534-b14408df87a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891343007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2891343007
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3108590996
Short name T861
Test name
Test status
Simulation time 463810517 ps
CPU time 0.83 seconds
Started Jul 31 05:19:01 PM PDT 24
Finished Jul 31 05:19:02 PM PDT 24
Peak memory 201372 kb
Host smart-c4364265-02d2-4866-90a8-64b353058e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108590996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3108590996
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2344646548
Short name T852
Test name
Test status
Simulation time 391209561 ps
CPU time 1.4 seconds
Started Jul 31 05:18:52 PM PDT 24
Finished Jul 31 05:18:53 PM PDT 24
Peak memory 201364 kb
Host smart-378784d4-b195-4096-944b-b9c060ff4704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344646548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2344646548
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2431336566
Short name T827
Test name
Test status
Simulation time 393142122 ps
CPU time 1.49 seconds
Started Jul 31 05:19:01 PM PDT 24
Finished Jul 31 05:19:04 PM PDT 24
Peak memory 201384 kb
Host smart-dd52235c-e025-480d-8c3f-01fcd75f51d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431336566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2431336566
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3304095411
Short name T916
Test name
Test status
Simulation time 333117242 ps
CPU time 0.95 seconds
Started Jul 31 05:18:52 PM PDT 24
Finished Jul 31 05:18:53 PM PDT 24
Peak memory 201280 kb
Host smart-25fb5dce-8e13-44c4-9cdd-93e28adfab1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304095411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3304095411
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1972175011
Short name T815
Test name
Test status
Simulation time 481552559 ps
CPU time 1.34 seconds
Started Jul 31 05:18:55 PM PDT 24
Finished Jul 31 05:18:56 PM PDT 24
Peak memory 201264 kb
Host smart-8086d77c-909e-462d-87e8-3ea54958f26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972175011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1972175011
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3884333908
Short name T812
Test name
Test status
Simulation time 378945102 ps
CPU time 0.88 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:56 PM PDT 24
Peak memory 201340 kb
Host smart-216c3118-b985-4be4-a0b1-3de97a9bf86f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884333908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3884333908
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1558653752
Short name T899
Test name
Test status
Simulation time 368906514 ps
CPU time 0.83 seconds
Started Jul 31 05:19:00 PM PDT 24
Finished Jul 31 05:19:01 PM PDT 24
Peak memory 201300 kb
Host smart-070713df-4d92-4257-96c3-26b170a17829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558653752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1558653752
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3525837689
Short name T793
Test name
Test status
Simulation time 322185026 ps
CPU time 0.8 seconds
Started Jul 31 05:18:56 PM PDT 24
Finished Jul 31 05:18:57 PM PDT 24
Peak memory 201376 kb
Host smart-b6e3c409-66d2-4eb9-a2f4-0061f4f120fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525837689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3525837689
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.653135312
Short name T800
Test name
Test status
Simulation time 348708736 ps
CPU time 1.35 seconds
Started Jul 31 05:18:59 PM PDT 24
Finished Jul 31 05:19:06 PM PDT 24
Peak memory 201380 kb
Host smart-3077c601-f0df-478e-9bb9-cbf1935c054c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653135312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.653135312
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3988596350
Short name T839
Test name
Test status
Simulation time 1262159026 ps
CPU time 4.7 seconds
Started Jul 31 05:18:19 PM PDT 24
Finished Jul 31 05:18:23 PM PDT 24
Peak memory 201584 kb
Host smart-3c106d77-8f98-4e15-a09e-8e589c15b159
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988596350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3988596350
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2823653673
Short name T843
Test name
Test status
Simulation time 27612684747 ps
CPU time 32.58 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:19:18 PM PDT 24
Peak memory 201568 kb
Host smart-f924c019-9937-4e20-91b5-8121d6f4e883
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823653673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2823653673
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3849710681
Short name T819
Test name
Test status
Simulation time 1333514158 ps
CPU time 0.98 seconds
Started Jul 31 05:18:36 PM PDT 24
Finished Jul 31 05:18:37 PM PDT 24
Peak memory 201320 kb
Host smart-afb0e333-844e-480f-a0c1-3924921bab7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849710681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3849710681
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2867669687
Short name T804
Test name
Test status
Simulation time 606346501 ps
CPU time 1.28 seconds
Started Jul 31 05:18:19 PM PDT 24
Finished Jul 31 05:18:20 PM PDT 24
Peak memory 201472 kb
Host smart-9e1c5046-2595-4e4e-bdd4-e8c06efa00e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867669687 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2867669687
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.4150126689
Short name T914
Test name
Test status
Simulation time 556200618 ps
CPU time 1.01 seconds
Started Jul 31 05:18:21 PM PDT 24
Finished Jul 31 05:18:22 PM PDT 24
Peak memory 201396 kb
Host smart-064d9883-8aef-45b1-b8c9-125376116589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150126689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.4150126689
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4192383627
Short name T887
Test name
Test status
Simulation time 391449940 ps
CPU time 0.83 seconds
Started Jul 31 05:18:41 PM PDT 24
Finished Jul 31 05:18:42 PM PDT 24
Peak memory 201300 kb
Host smart-6df3e039-a984-44b9-b696-391399c24ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192383627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4192383627
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.293890175
Short name T823
Test name
Test status
Simulation time 2318443575 ps
CPU time 3.88 seconds
Started Jul 31 05:18:35 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 201404 kb
Host smart-542ef3af-5d85-48e4-bf78-a12637f65f3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293890175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.293890175
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3793837067
Short name T83
Test name
Test status
Simulation time 422600809 ps
CPU time 3.1 seconds
Started Jul 31 05:18:38 PM PDT 24
Finished Jul 31 05:18:41 PM PDT 24
Peak memory 217864 kb
Host smart-7fc6930f-e48e-46c1-bb6a-67d8e515d45d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793837067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3793837067
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3212768380
Short name T73
Test name
Test status
Simulation time 7803497937 ps
CPU time 6.63 seconds
Started Jul 31 05:18:17 PM PDT 24
Finished Jul 31 05:18:23 PM PDT 24
Peak memory 201648 kb
Host smart-ea1ef870-d612-4ace-a266-c55f0f26e1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212768380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3212768380
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.139573029
Short name T796
Test name
Test status
Simulation time 544597584 ps
CPU time 0.94 seconds
Started Jul 31 05:19:14 PM PDT 24
Finished Jul 31 05:19:15 PM PDT 24
Peak memory 201332 kb
Host smart-b7a53eac-1202-4dec-94a8-36851daea0fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139573029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.139573029
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.360396577
Short name T873
Test name
Test status
Simulation time 351836637 ps
CPU time 1.37 seconds
Started Jul 31 05:18:59 PM PDT 24
Finished Jul 31 05:19:00 PM PDT 24
Peak memory 201356 kb
Host smart-ada7410e-d36a-4738-8deb-53f1275d18bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360396577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.360396577
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.445938241
Short name T898
Test name
Test status
Simulation time 464489675 ps
CPU time 0.9 seconds
Started Jul 31 05:18:52 PM PDT 24
Finished Jul 31 05:18:53 PM PDT 24
Peak memory 201392 kb
Host smart-876f781c-dc72-4397-9587-ada58ee9fd2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445938241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.445938241
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3244909150
Short name T799
Test name
Test status
Simulation time 474945692 ps
CPU time 0.91 seconds
Started Jul 31 05:19:08 PM PDT 24
Finished Jul 31 05:19:09 PM PDT 24
Peak memory 201264 kb
Host smart-f397fbfc-73c4-43e7-9417-01ca2e71d7a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244909150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3244909150
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1622382251
Short name T797
Test name
Test status
Simulation time 399111704 ps
CPU time 0.84 seconds
Started Jul 31 05:18:54 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201304 kb
Host smart-4e3a248a-7d44-457c-b1a3-c2cff44784df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622382251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1622382251
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.386483043
Short name T810
Test name
Test status
Simulation time 386909504 ps
CPU time 1.47 seconds
Started Jul 31 05:18:50 PM PDT 24
Finished Jul 31 05:18:52 PM PDT 24
Peak memory 201496 kb
Host smart-bb3fecd8-32f8-40a0-91be-6e2cf1f929a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386483043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.386483043
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2569255126
Short name T876
Test name
Test status
Simulation time 370114009 ps
CPU time 0.81 seconds
Started Jul 31 05:19:00 PM PDT 24
Finished Jul 31 05:19:00 PM PDT 24
Peak memory 201384 kb
Host smart-76ca9b20-7eec-40dc-80f9-5a7972502d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569255126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2569255126
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1503353714
Short name T913
Test name
Test status
Simulation time 384792657 ps
CPU time 1.1 seconds
Started Jul 31 05:18:53 PM PDT 24
Finished Jul 31 05:19:00 PM PDT 24
Peak memory 201304 kb
Host smart-99e8305b-52b3-40fa-9647-6d0e9f23bfed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503353714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1503353714
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2350112580
Short name T791
Test name
Test status
Simulation time 380540240 ps
CPU time 1.43 seconds
Started Jul 31 05:19:09 PM PDT 24
Finished Jul 31 05:19:10 PM PDT 24
Peak memory 201344 kb
Host smart-6594caf8-691f-493c-973d-d3c72062d0ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350112580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2350112580
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3578126074
Short name T802
Test name
Test status
Simulation time 445023683 ps
CPU time 1.15 seconds
Started Jul 31 05:18:50 PM PDT 24
Finished Jul 31 05:18:52 PM PDT 24
Peak memory 201284 kb
Host smart-7b222565-d84f-4817-a6a4-de19645258e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578126074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3578126074
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1615297160
Short name T890
Test name
Test status
Simulation time 529897588 ps
CPU time 1.09 seconds
Started Jul 31 05:18:41 PM PDT 24
Finished Jul 31 05:18:42 PM PDT 24
Peak memory 201412 kb
Host smart-a1132194-2136-4f0b-9239-d3603005447d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615297160 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1615297160
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.277050762
Short name T856
Test name
Test status
Simulation time 440747919 ps
CPU time 1.75 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:49 PM PDT 24
Peak memory 201340 kb
Host smart-2aac226d-dcba-4a41-b746-4e648cb1c570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277050762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.277050762
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1807623880
Short name T903
Test name
Test status
Simulation time 368004178 ps
CPU time 1.47 seconds
Started Jul 31 05:18:14 PM PDT 24
Finished Jul 31 05:18:16 PM PDT 24
Peak memory 201292 kb
Host smart-9fce55d2-0778-42fb-9fd2-91a255b1078b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807623880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1807623880
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2322231040
Short name T860
Test name
Test status
Simulation time 4571214442 ps
CPU time 3.63 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:51 PM PDT 24
Peak memory 201568 kb
Host smart-7618c968-f99e-40ad-b035-d0c2e0ffe2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322231040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2322231040
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3041268564
Short name T881
Test name
Test status
Simulation time 494733059 ps
CPU time 3.28 seconds
Started Jul 31 05:18:53 PM PDT 24
Finished Jul 31 05:18:56 PM PDT 24
Peak memory 218028 kb
Host smart-30bd98e7-a021-4b79-bf9b-3706aeb567e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041268564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3041268564
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2156739043
Short name T817
Test name
Test status
Simulation time 398244171 ps
CPU time 1.24 seconds
Started Jul 31 05:18:30 PM PDT 24
Finished Jul 31 05:18:31 PM PDT 24
Peak memory 201452 kb
Host smart-7656e85e-ab39-4f4a-99b4-128d06d9bdd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156739043 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2156739043
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.185251793
Short name T902
Test name
Test status
Simulation time 338018528 ps
CPU time 1.5 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:32 PM PDT 24
Peak memory 201376 kb
Host smart-4e5776da-8c70-4461-9408-36f95f422a94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185251793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.185251793
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3419921773
Short name T853
Test name
Test status
Simulation time 368652639 ps
CPU time 0.83 seconds
Started Jul 31 05:18:27 PM PDT 24
Finished Jul 31 05:18:28 PM PDT 24
Peak memory 201228 kb
Host smart-062176c9-7b1d-4bb7-9bb6-8f6bb2a9591f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419921773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3419921773
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2720577495
Short name T66
Test name
Test status
Simulation time 4360329109 ps
CPU time 6.33 seconds
Started Jul 31 05:18:34 PM PDT 24
Finished Jul 31 05:18:40 PM PDT 24
Peak memory 201576 kb
Host smart-fd3ad45c-bec8-40a5-9b15-ae8ab55616d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720577495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2720577495
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3714250583
Short name T824
Test name
Test status
Simulation time 522538481 ps
CPU time 3.21 seconds
Started Jul 31 05:18:40 PM PDT 24
Finished Jul 31 05:18:43 PM PDT 24
Peak memory 217924 kb
Host smart-1418037c-42ba-4a69-986e-7b0ce9092d31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714250583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3714250583
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1630243362
Short name T850
Test name
Test status
Simulation time 4431452201 ps
CPU time 4.11 seconds
Started Jul 31 05:18:14 PM PDT 24
Finished Jul 31 05:18:19 PM PDT 24
Peak memory 201620 kb
Host smart-91f9f910-c0d1-4fa8-b4fe-5405447ad3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630243362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1630243362
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3988708646
Short name T831
Test name
Test status
Simulation time 422220648 ps
CPU time 1.97 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:33 PM PDT 24
Peak memory 201412 kb
Host smart-861f515f-5442-46eb-a361-3fc7a730e1e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988708646 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3988708646
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2919547258
Short name T124
Test name
Test status
Simulation time 507138419 ps
CPU time 1.87 seconds
Started Jul 31 05:18:30 PM PDT 24
Finished Jul 31 05:18:32 PM PDT 24
Peak memory 201284 kb
Host smart-cbb9876d-577d-4aec-94ae-ce4d0a0720fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919547258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2919547258
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3885418282
Short name T841
Test name
Test status
Simulation time 483403475 ps
CPU time 1.23 seconds
Started Jul 31 05:18:31 PM PDT 24
Finished Jul 31 05:18:32 PM PDT 24
Peak memory 201308 kb
Host smart-11de0478-3c31-4f1d-83be-d9badb9e0d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885418282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3885418282
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2221936212
Short name T870
Test name
Test status
Simulation time 2918603411 ps
CPU time 3.97 seconds
Started Jul 31 05:18:44 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201340 kb
Host smart-44c30b34-0612-4b59-8c50-0335c229d879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221936212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2221936212
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2849474754
Short name T893
Test name
Test status
Simulation time 1219736560 ps
CPU time 2.39 seconds
Started Jul 31 05:18:32 PM PDT 24
Finished Jul 31 05:18:35 PM PDT 24
Peak memory 201552 kb
Host smart-75ef00f2-9a49-4b52-9678-4a5eeb47b900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849474754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2849474754
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2775872061
Short name T885
Test name
Test status
Simulation time 4315155049 ps
CPU time 4.16 seconds
Started Jul 31 05:18:27 PM PDT 24
Finished Jul 31 05:18:31 PM PDT 24
Peak memory 201636 kb
Host smart-02167a93-af7c-4712-994c-ade93898281e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775872061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2775872061
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.965672138
Short name T818
Test name
Test status
Simulation time 373697826 ps
CPU time 1.3 seconds
Started Jul 31 05:18:47 PM PDT 24
Finished Jul 31 05:18:48 PM PDT 24
Peak memory 201520 kb
Host smart-f6d4829a-fe5c-4528-a73f-b9377dea8837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965672138 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.965672138
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4242969879
Short name T868
Test name
Test status
Simulation time 457311685 ps
CPU time 1.64 seconds
Started Jul 31 05:18:45 PM PDT 24
Finished Jul 31 05:18:47 PM PDT 24
Peak memory 201364 kb
Host smart-d9eeb8f5-445e-488e-8e11-d6e38588da41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242969879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4242969879
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.371357773
Short name T792
Test name
Test status
Simulation time 346335346 ps
CPU time 1.43 seconds
Started Jul 31 05:18:40 PM PDT 24
Finished Jul 31 05:18:42 PM PDT 24
Peak memory 201320 kb
Host smart-1ebbb268-1115-43f9-91ee-aa3698c55388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371357773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.371357773
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3517884367
Short name T867
Test name
Test status
Simulation time 2614220492 ps
CPU time 2.29 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:18:55 PM PDT 24
Peak memory 201356 kb
Host smart-113afae5-9e2f-40ca-95d1-ee1be3dc5686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517884367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3517884367
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.769610625
Short name T895
Test name
Test status
Simulation time 591913231 ps
CPU time 2.8 seconds
Started Jul 31 05:18:44 PM PDT 24
Finished Jul 31 05:18:47 PM PDT 24
Peak memory 210832 kb
Host smart-f3fedcda-8f89-430f-8bb9-333b689e846d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769610625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.769610625
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.982266431
Short name T900
Test name
Test status
Simulation time 8505961776 ps
CPU time 19.53 seconds
Started Jul 31 05:18:46 PM PDT 24
Finished Jul 31 05:19:06 PM PDT 24
Peak memory 201648 kb
Host smart-fc9e4a02-0cdb-46d9-abdb-629e2dde872d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982266431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.982266431
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1836358829
Short name T897
Test name
Test status
Simulation time 540230558 ps
CPU time 2.15 seconds
Started Jul 31 05:18:48 PM PDT 24
Finished Jul 31 05:18:50 PM PDT 24
Peak memory 201492 kb
Host smart-8709234b-1c70-48fe-aa5e-c3bd00ad92f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836358829 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1836358829
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3148820916
Short name T848
Test name
Test status
Simulation time 343809330 ps
CPU time 1.35 seconds
Started Jul 31 05:18:49 PM PDT 24
Finished Jul 31 05:18:50 PM PDT 24
Peak memory 201404 kb
Host smart-f2579687-5b07-4026-b722-4539b334cb0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148820916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3148820916
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1159973344
Short name T795
Test name
Test status
Simulation time 512395759 ps
CPU time 1.37 seconds
Started Jul 31 05:18:39 PM PDT 24
Finished Jul 31 05:18:40 PM PDT 24
Peak memory 201232 kb
Host smart-a094dc34-af4d-448f-ab83-0ad2433300c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159973344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1159973344
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3427058860
Short name T138
Test name
Test status
Simulation time 4019518887 ps
CPU time 2.6 seconds
Started Jul 31 05:18:33 PM PDT 24
Finished Jul 31 05:18:35 PM PDT 24
Peak memory 201596 kb
Host smart-8414f18b-26ef-465f-affd-e634fddd1b37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427058860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3427058860
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2799154456
Short name T901
Test name
Test status
Simulation time 770686379 ps
CPU time 3.47 seconds
Started Jul 31 05:18:35 PM PDT 24
Finished Jul 31 05:18:39 PM PDT 24
Peak memory 201632 kb
Host smart-e5766039-52e3-4387-8f51-36e23e675282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799154456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2799154456
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3787930081
Short name T875
Test name
Test status
Simulation time 5127477718 ps
CPU time 2.35 seconds
Started Jul 31 05:18:44 PM PDT 24
Finished Jul 31 05:18:46 PM PDT 24
Peak memory 201668 kb
Host smart-10db9aae-29bc-4bb1-be8f-030278ce2ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787930081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3787930081
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.139842798
Short name T626
Test name
Test status
Simulation time 515933671 ps
CPU time 1.18 seconds
Started Jul 31 06:37:49 PM PDT 24
Finished Jul 31 06:37:50 PM PDT 24
Peak memory 201252 kb
Host smart-19baf395-af99-4cd9-8c94-161e93c96863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139842798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.139842798
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.817665998
Short name T306
Test name
Test status
Simulation time 165369415964 ps
CPU time 39.77 seconds
Started Jul 31 06:37:43 PM PDT 24
Finished Jul 31 06:38:23 PM PDT 24
Peak memory 201436 kb
Host smart-390c28db-bc07-43ee-bc55-56025eed0ed7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817665998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.817665998
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1676734914
Short name T170
Test name
Test status
Simulation time 568405994560 ps
CPU time 692.13 seconds
Started Jul 31 06:37:42 PM PDT 24
Finished Jul 31 06:49:14 PM PDT 24
Peak memory 201448 kb
Host smart-516b7a24-8147-4a87-9112-9970cc7261ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676734914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1676734914
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3932409975
Short name T567
Test name
Test status
Simulation time 496376715341 ps
CPU time 1068.6 seconds
Started Jul 31 06:37:44 PM PDT 24
Finished Jul 31 06:55:33 PM PDT 24
Peak memory 201472 kb
Host smart-ad43a2a4-7144-4c44-98a4-185490614e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932409975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3932409975
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1104919315
Short name T447
Test name
Test status
Simulation time 171048325945 ps
CPU time 367.16 seconds
Started Jul 31 06:37:42 PM PDT 24
Finished Jul 31 06:43:49 PM PDT 24
Peak memory 201484 kb
Host smart-64ee37cc-a5a8-46cb-9b80-83b36cd60612
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104919315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1104919315
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.335350058
Short name T571
Test name
Test status
Simulation time 169357697359 ps
CPU time 184.34 seconds
Started Jul 31 06:37:44 PM PDT 24
Finished Jul 31 06:40:48 PM PDT 24
Peak memory 201380 kb
Host smart-61cb4140-2581-45f2-b83a-55ac813e468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335350058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.335350058
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1088452840
Short name T120
Test name
Test status
Simulation time 169039802918 ps
CPU time 378.22 seconds
Started Jul 31 06:37:41 PM PDT 24
Finished Jul 31 06:44:00 PM PDT 24
Peak memory 201396 kb
Host smart-746c263f-4a96-42bf-9c1e-cf581fc06949
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088452840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1088452840
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1865611643
Short name T446
Test name
Test status
Simulation time 385910274663 ps
CPU time 851.26 seconds
Started Jul 31 06:37:41 PM PDT 24
Finished Jul 31 06:51:53 PM PDT 24
Peak memory 201376 kb
Host smart-6c1dce31-1137-4786-9390-cb9aad90b1de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865611643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1865611643
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3207821531
Short name T509
Test name
Test status
Simulation time 111760142583 ps
CPU time 388.05 seconds
Started Jul 31 06:37:42 PM PDT 24
Finished Jul 31 06:44:10 PM PDT 24
Peak memory 201828 kb
Host smart-6bc6317e-9990-42da-84d0-d7ff95808677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207821531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3207821531
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3862304338
Short name T582
Test name
Test status
Simulation time 36959920137 ps
CPU time 42.97 seconds
Started Jul 31 06:37:43 PM PDT 24
Finished Jul 31 06:38:26 PM PDT 24
Peak memory 201324 kb
Host smart-5c3f499a-0132-444b-b3d4-fc5593051804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862304338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3862304338
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.581822191
Short name T676
Test name
Test status
Simulation time 3222293318 ps
CPU time 2.67 seconds
Started Jul 31 06:37:45 PM PDT 24
Finished Jul 31 06:37:48 PM PDT 24
Peak memory 201340 kb
Host smart-9c8aaecc-29c0-4378-aa58-42a2ae108538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581822191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.581822191
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2983504408
Short name T668
Test name
Test status
Simulation time 5735475069 ps
CPU time 7.42 seconds
Started Jul 31 06:37:44 PM PDT 24
Finished Jul 31 06:37:52 PM PDT 24
Peak memory 201352 kb
Host smart-ed158ea9-0720-4663-b604-21444526272a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983504408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2983504408
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4162802308
Short name T36
Test name
Test status
Simulation time 202014698350 ps
CPU time 105.27 seconds
Started Jul 31 06:37:50 PM PDT 24
Finished Jul 31 06:39:35 PM PDT 24
Peak memory 201440 kb
Host smart-a5cb0c33-90cb-4c85-913d-434b82113ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162802308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4162802308
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.627038889
Short name T595
Test name
Test status
Simulation time 170804077944 ps
CPU time 259.79 seconds
Started Jul 31 06:37:42 PM PDT 24
Finished Jul 31 06:42:02 PM PDT 24
Peak memory 209772 kb
Host smart-01f78ee9-a479-4d25-bbd3-f6d42bd0756b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627038889 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.627038889
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.384693734
Short name T407
Test name
Test status
Simulation time 464551061 ps
CPU time 1.09 seconds
Started Jul 31 06:37:57 PM PDT 24
Finished Jul 31 06:37:59 PM PDT 24
Peak memory 201252 kb
Host smart-d8d1df60-f1cf-4438-b019-c771648c1656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384693734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.384693734
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3960746477
Short name T222
Test name
Test status
Simulation time 158251005054 ps
CPU time 91.02 seconds
Started Jul 31 06:37:55 PM PDT 24
Finished Jul 31 06:39:26 PM PDT 24
Peak memory 201424 kb
Host smart-71703223-caf6-4b57-ade1-1fea555db717
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960746477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3960746477
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3747767199
Short name T604
Test name
Test status
Simulation time 165514659293 ps
CPU time 378.57 seconds
Started Jul 31 06:37:57 PM PDT 24
Finished Jul 31 06:44:16 PM PDT 24
Peak memory 201464 kb
Host smart-5541238d-37d5-478f-9dcd-e9d88b4e1ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747767199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3747767199
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4048777833
Short name T323
Test name
Test status
Simulation time 326623193459 ps
CPU time 627.11 seconds
Started Jul 31 06:37:49 PM PDT 24
Finished Jul 31 06:48:16 PM PDT 24
Peak memory 201456 kb
Host smart-7da1c983-fa69-4f84-ab76-74b71920e93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048777833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4048777833
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.139367375
Short name T640
Test name
Test status
Simulation time 172069343385 ps
CPU time 380.41 seconds
Started Jul 31 06:37:48 PM PDT 24
Finished Jul 31 06:44:08 PM PDT 24
Peak memory 201464 kb
Host smart-c8efb4b0-6ceb-4795-aebd-c41cd8a6d227
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=139367375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.139367375
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4285254191
Short name T303
Test name
Test status
Simulation time 495060418384 ps
CPU time 1178.19 seconds
Started Jul 31 06:37:49 PM PDT 24
Finished Jul 31 06:57:27 PM PDT 24
Peak memory 201452 kb
Host smart-2e22a137-663a-45e3-92b5-157994e37147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285254191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4285254191
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2026465534
Short name T663
Test name
Test status
Simulation time 162318136817 ps
CPU time 360.29 seconds
Started Jul 31 06:37:51 PM PDT 24
Finished Jul 31 06:43:51 PM PDT 24
Peak memory 201436 kb
Host smart-85409f9f-137e-4bf2-a351-6404adaf1836
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026465534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2026465534
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.723676231
Short name T33
Test name
Test status
Simulation time 169882281885 ps
CPU time 94.54 seconds
Started Jul 31 06:37:48 PM PDT 24
Finished Jul 31 06:39:23 PM PDT 24
Peak memory 201460 kb
Host smart-43bec34b-ac43-4726-ad22-68fa51e2d1a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723676231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.723676231
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4290527231
Short name T588
Test name
Test status
Simulation time 611838118648 ps
CPU time 332.05 seconds
Started Jul 31 06:37:53 PM PDT 24
Finished Jul 31 06:43:25 PM PDT 24
Peak memory 201436 kb
Host smart-b67a30f0-af05-4dfe-a6b9-8afb36ff58d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290527231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4290527231
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.431655302
Short name T453
Test name
Test status
Simulation time 137787178310 ps
CPU time 491.38 seconds
Started Jul 31 06:37:56 PM PDT 24
Finished Jul 31 06:46:08 PM PDT 24
Peak memory 201844 kb
Host smart-7c742ee8-4c02-4c2c-a253-088be0f05a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431655302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.431655302
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3846125757
Short name T783
Test name
Test status
Simulation time 21905329093 ps
CPU time 6.73 seconds
Started Jul 31 06:37:55 PM PDT 24
Finished Jul 31 06:38:02 PM PDT 24
Peak memory 201360 kb
Host smart-547962c5-bb13-493e-8581-8a0899c3a5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846125757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3846125757
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3791946732
Short name T702
Test name
Test status
Simulation time 2638519345 ps
CPU time 6.82 seconds
Started Jul 31 06:37:55 PM PDT 24
Finished Jul 31 06:38:02 PM PDT 24
Peak memory 201368 kb
Host smart-ae3cb6e9-500c-4d4d-b337-da7a9d9d75b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791946732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3791946732
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.894573573
Short name T79
Test name
Test status
Simulation time 4328465899 ps
CPU time 2.52 seconds
Started Jul 31 06:37:56 PM PDT 24
Finished Jul 31 06:37:59 PM PDT 24
Peak memory 217296 kb
Host smart-6a4ee059-4887-4437-8cdc-162e3bb83b5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894573573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.894573573
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1257241864
Short name T719
Test name
Test status
Simulation time 5744147358 ps
CPU time 14.01 seconds
Started Jul 31 06:37:49 PM PDT 24
Finished Jul 31 06:38:03 PM PDT 24
Peak memory 201388 kb
Host smart-a3408080-048f-4b8b-af52-19b00ccf8d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257241864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1257241864
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3838647377
Short name T219
Test name
Test status
Simulation time 203984452435 ps
CPU time 696.79 seconds
Started Jul 31 06:37:54 PM PDT 24
Finished Jul 31 06:49:31 PM PDT 24
Peak memory 201808 kb
Host smart-2aac2e49-dace-49a8-9c69-4e443f799bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838647377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3838647377
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1552898481
Short name T464
Test name
Test status
Simulation time 137804978500 ps
CPU time 273.99 seconds
Started Jul 31 06:37:57 PM PDT 24
Finished Jul 31 06:42:31 PM PDT 24
Peak memory 218260 kb
Host smart-4b27c3ea-2829-4a6e-81ca-c05abce0a285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552898481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1552898481
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.540770632
Short name T391
Test name
Test status
Simulation time 440214563 ps
CPU time 1.12 seconds
Started Jul 31 06:40:25 PM PDT 24
Finished Jul 31 06:40:27 PM PDT 24
Peak memory 201160 kb
Host smart-42a4e708-241f-4a31-8fb2-341ac7f2e3d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540770632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.540770632
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1013558672
Short name T58
Test name
Test status
Simulation time 163581393599 ps
CPU time 345.95 seconds
Started Jul 31 06:40:09 PM PDT 24
Finished Jul 31 06:45:55 PM PDT 24
Peak memory 201436 kb
Host smart-95edf12d-bbb2-41ac-a0cb-8f1dbbfe3bc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013558672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1013558672
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3575263986
Short name T751
Test name
Test status
Simulation time 492268069837 ps
CPU time 275.62 seconds
Started Jul 31 06:40:04 PM PDT 24
Finished Jul 31 06:44:39 PM PDT 24
Peak memory 201444 kb
Host smart-9c42c693-7d99-4044-9edd-44b48916a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575263986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3575263986
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4194564532
Short name T752
Test name
Test status
Simulation time 488814314200 ps
CPU time 267.6 seconds
Started Jul 31 06:40:05 PM PDT 24
Finished Jul 31 06:44:33 PM PDT 24
Peak memory 201492 kb
Host smart-74f2207c-fbd8-4dbf-8ed8-4ee88ce49f05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194564532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4194564532
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3092147588
Short name T164
Test name
Test status
Simulation time 496007463048 ps
CPU time 1096.06 seconds
Started Jul 31 06:40:04 PM PDT 24
Finished Jul 31 06:58:20 PM PDT 24
Peak memory 201452 kb
Host smart-bd6d7a89-aa60-4112-8153-4edebe41289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092147588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3092147588
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2855144911
Short name T712
Test name
Test status
Simulation time 490748355161 ps
CPU time 225.46 seconds
Started Jul 31 06:40:04 PM PDT 24
Finished Jul 31 06:43:50 PM PDT 24
Peak memory 201416 kb
Host smart-c010dcf2-97e4-4e1e-bcd4-d3998e6f2872
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855144911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2855144911
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1261834365
Short name T52
Test name
Test status
Simulation time 166158896609 ps
CPU time 372.2 seconds
Started Jul 31 06:40:08 PM PDT 24
Finished Jul 31 06:46:21 PM PDT 24
Peak memory 201488 kb
Host smart-084e2ce4-5ae8-45da-9fbd-ab328db8769c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261834365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1261834365
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.4026759715
Short name T382
Test name
Test status
Simulation time 572265573623 ps
CPU time 240.51 seconds
Started Jul 31 06:40:12 PM PDT 24
Finished Jul 31 06:44:12 PM PDT 24
Peak memory 201464 kb
Host smart-0df2cc8a-2627-4a41-be10-29f2a3a63dc5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026759715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.4026759715
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2726116860
Short name T15
Test name
Test status
Simulation time 64784651774 ps
CPU time 371.16 seconds
Started Jul 31 06:40:20 PM PDT 24
Finished Jul 31 06:46:31 PM PDT 24
Peak memory 201848 kb
Host smart-396d0d9f-a186-4e21-b589-d7c55600ea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726116860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2726116860
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4257266335
Short name T421
Test name
Test status
Simulation time 31318707356 ps
CPU time 21.6 seconds
Started Jul 31 06:40:15 PM PDT 24
Finished Jul 31 06:40:37 PM PDT 24
Peak memory 201368 kb
Host smart-2bf22795-1c83-4865-8ec4-761e217c00a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257266335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4257266335
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3677068446
Short name T462
Test name
Test status
Simulation time 5231894192 ps
CPU time 4.22 seconds
Started Jul 31 06:40:15 PM PDT 24
Finished Jul 31 06:40:19 PM PDT 24
Peak memory 201344 kb
Host smart-a74c11ff-47d7-4ece-8d51-f6f1dbe57fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677068446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3677068446
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.4209438717
Short name T436
Test name
Test status
Simulation time 6095690436 ps
CPU time 2.88 seconds
Started Jul 31 06:40:04 PM PDT 24
Finished Jul 31 06:40:07 PM PDT 24
Peak memory 201380 kb
Host smart-b0075559-ba02-4f5e-b422-6d1e2a57e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209438717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.4209438717
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2472893619
Short name T281
Test name
Test status
Simulation time 518675257969 ps
CPU time 127.34 seconds
Started Jul 31 06:40:18 PM PDT 24
Finished Jul 31 06:42:26 PM PDT 24
Peak memory 201464 kb
Host smart-7ecf89c7-e166-440a-aaea-6b2890e4001d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472893619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2472893619
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.748177849
Short name T423
Test name
Test status
Simulation time 437552785 ps
CPU time 0.93 seconds
Started Jul 31 06:40:46 PM PDT 24
Finished Jul 31 06:40:47 PM PDT 24
Peak memory 201280 kb
Host smart-c728d39f-07fd-4566-aee8-08d52312cf6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748177849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.748177849
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3685684930
Short name T313
Test name
Test status
Simulation time 168264961653 ps
CPU time 354.29 seconds
Started Jul 31 06:40:34 PM PDT 24
Finished Jul 31 06:46:29 PM PDT 24
Peak memory 201524 kb
Host smart-7cafd48e-b861-4e4c-958c-efdc3f8bfa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685684930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3685684930
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1286730490
Short name T231
Test name
Test status
Simulation time 161202120742 ps
CPU time 363.17 seconds
Started Jul 31 06:40:32 PM PDT 24
Finished Jul 31 06:46:35 PM PDT 24
Peak memory 201432 kb
Host smart-8229f3ff-c4ed-4a0f-9dfc-1524b395ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286730490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1286730490
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.606471004
Short name T704
Test name
Test status
Simulation time 162294722055 ps
CPU time 101.59 seconds
Started Jul 31 06:40:31 PM PDT 24
Finished Jul 31 06:42:13 PM PDT 24
Peak memory 201388 kb
Host smart-afa28a67-ece6-4e22-b2e4-3c1b8f12d788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=606471004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.606471004
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3285617144
Short name T207
Test name
Test status
Simulation time 492849413786 ps
CPU time 844.04 seconds
Started Jul 31 06:40:26 PM PDT 24
Finished Jul 31 06:54:30 PM PDT 24
Peak memory 201468 kb
Host smart-28e1e31f-08f3-4013-a21f-bc46c1068ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285617144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3285617144
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3573778309
Short name T475
Test name
Test status
Simulation time 322566691488 ps
CPU time 738.54 seconds
Started Jul 31 06:40:32 PM PDT 24
Finished Jul 31 06:52:51 PM PDT 24
Peak memory 201452 kb
Host smart-4727c6cf-940f-4f59-8acb-4870715f85dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573778309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3573778309
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.612672
Short name T294
Test name
Test status
Simulation time 372820130465 ps
CPU time 776.6 seconds
Started Jul 31 06:40:36 PM PDT 24
Finished Jul 31 06:53:32 PM PDT 24
Peak memory 201468 kb
Host smart-1a48b800-9eb9-4e67-b6dc-a3d58c9ba795
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wa
keup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wak
eup.612672
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3035502148
Short name T187
Test name
Test status
Simulation time 581982125373 ps
CPU time 1394.73 seconds
Started Jul 31 06:40:36 PM PDT 24
Finished Jul 31 07:03:51 PM PDT 24
Peak memory 201428 kb
Host smart-0a606a27-090a-4fb4-8747-665c5dff02ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035502148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3035502148
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3716807938
Short name T459
Test name
Test status
Simulation time 82051954967 ps
CPU time 402.03 seconds
Started Jul 31 06:40:40 PM PDT 24
Finished Jul 31 06:47:22 PM PDT 24
Peak memory 201880 kb
Host smart-268ace0b-7807-4855-96eb-7770b32c7329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716807938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3716807938
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3481573025
Short name T635
Test name
Test status
Simulation time 22036935467 ps
CPU time 23.27 seconds
Started Jul 31 06:40:41 PM PDT 24
Finished Jul 31 06:41:04 PM PDT 24
Peak memory 201392 kb
Host smart-f3e20358-c974-4e21-b4c5-eb71aad8904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481573025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3481573025
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1804778828
Short name T609
Test name
Test status
Simulation time 3925297848 ps
CPU time 1.15 seconds
Started Jul 31 06:40:35 PM PDT 24
Finished Jul 31 06:40:36 PM PDT 24
Peak memory 201356 kb
Host smart-bc39b2c3-c024-4ce2-aa82-1332a8204129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804778828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1804778828
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.669884702
Short name T393
Test name
Test status
Simulation time 5650695149 ps
CPU time 2.76 seconds
Started Jul 31 06:40:27 PM PDT 24
Finished Jul 31 06:40:30 PM PDT 24
Peak memory 201432 kb
Host smart-1c98c6f1-ea18-4a9d-b5d2-9083dcd5a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669884702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.669884702
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3865696691
Short name T150
Test name
Test status
Simulation time 331697535063 ps
CPU time 691.61 seconds
Started Jul 31 06:40:46 PM PDT 24
Finished Jul 31 06:52:17 PM PDT 24
Peak memory 201492 kb
Host smart-ee358af8-06c9-420c-b75c-4beb59887306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865696691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3865696691
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3286240537
Short name T493
Test name
Test status
Simulation time 60212648466 ps
CPU time 101.54 seconds
Started Jul 31 06:40:43 PM PDT 24
Finished Jul 31 06:42:24 PM PDT 24
Peak memory 209892 kb
Host smart-70bafd06-8f9b-4b8b-9143-21f41f7acb1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286240537 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3286240537
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.689703701
Short name T750
Test name
Test status
Simulation time 449607088 ps
CPU time 0.86 seconds
Started Jul 31 06:41:12 PM PDT 24
Finished Jul 31 06:41:13 PM PDT 24
Peak memory 201228 kb
Host smart-df926708-0bd5-4ac2-b09c-545cdf99be84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689703701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.689703701
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2831713722
Short name T229
Test name
Test status
Simulation time 374349854488 ps
CPU time 510.79 seconds
Started Jul 31 06:40:58 PM PDT 24
Finished Jul 31 06:49:29 PM PDT 24
Peak memory 201296 kb
Host smart-8fd35452-79d2-4a04-b49b-9b78c66cea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831713722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2831713722
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.587910177
Short name T620
Test name
Test status
Simulation time 158474940535 ps
CPU time 96.44 seconds
Started Jul 31 06:40:58 PM PDT 24
Finished Jul 31 06:42:34 PM PDT 24
Peak memory 201520 kb
Host smart-ba264d35-d173-4d08-9712-147a2561aa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587910177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.587910177
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.633775273
Short name T400
Test name
Test status
Simulation time 163434906411 ps
CPU time 98.35 seconds
Started Jul 31 06:40:58 PM PDT 24
Finished Jul 31 06:42:36 PM PDT 24
Peak memory 201340 kb
Host smart-f9219b68-d042-422e-a247-7f2661043938
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=633775273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.633775273
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3750721122
Short name T157
Test name
Test status
Simulation time 496050348402 ps
CPU time 1088.18 seconds
Started Jul 31 06:40:50 PM PDT 24
Finished Jul 31 06:58:58 PM PDT 24
Peak memory 201472 kb
Host smart-86fc0893-4f62-435b-9380-290a2c17a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750721122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3750721122
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1958339261
Short name T770
Test name
Test status
Simulation time 491424778514 ps
CPU time 1101.42 seconds
Started Jul 31 06:40:51 PM PDT 24
Finished Jul 31 06:59:13 PM PDT 24
Peak memory 201400 kb
Host smart-57d91cdd-d5cb-4cce-9b2d-480128337571
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958339261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1958339261
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3937311239
Short name T34
Test name
Test status
Simulation time 205177411653 ps
CPU time 217.87 seconds
Started Jul 31 06:40:55 PM PDT 24
Finished Jul 31 06:44:33 PM PDT 24
Peak memory 201344 kb
Host smart-69ec48ef-b34b-43e9-a428-ca1118158eac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937311239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3937311239
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1360003965
Short name T60
Test name
Test status
Simulation time 75411875976 ps
CPU time 304.21 seconds
Started Jul 31 06:41:06 PM PDT 24
Finished Jul 31 06:46:11 PM PDT 24
Peak memory 201896 kb
Host smart-efd57068-2208-4c98-9063-a80f4c3a896a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360003965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1360003965
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2137702926
Short name T488
Test name
Test status
Simulation time 36629384974 ps
CPU time 22.92 seconds
Started Jul 31 06:41:02 PM PDT 24
Finished Jul 31 06:41:25 PM PDT 24
Peak memory 201344 kb
Host smart-3c1d06ae-3397-4372-ad46-d71cdab8f2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137702926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2137702926
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.4103549326
Short name T144
Test name
Test status
Simulation time 3493269341 ps
CPU time 8.61 seconds
Started Jul 31 06:41:06 PM PDT 24
Finished Jul 31 06:41:15 PM PDT 24
Peak memory 201344 kb
Host smart-c635da5d-2234-4344-8f0f-28111548c44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103549326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.4103549326
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4194641552
Short name T672
Test name
Test status
Simulation time 5735730621 ps
CPU time 12.37 seconds
Started Jul 31 06:40:47 PM PDT 24
Finished Jul 31 06:40:59 PM PDT 24
Peak memory 201368 kb
Host smart-e0e2cb81-f955-4a4d-8c8a-71635076c535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194641552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4194641552
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3796473688
Short name T641
Test name
Test status
Simulation time 471886956970 ps
CPU time 608.49 seconds
Started Jul 31 06:41:10 PM PDT 24
Finished Jul 31 06:51:19 PM PDT 24
Peak memory 201812 kb
Host smart-63fbb11c-14f5-46cf-a9a1-a370e5c365ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796473688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3796473688
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2516408336
Short name T499
Test name
Test status
Simulation time 526966090 ps
CPU time 0.98 seconds
Started Jul 31 06:41:34 PM PDT 24
Finished Jul 31 06:41:35 PM PDT 24
Peak memory 201252 kb
Host smart-9fb03ce3-6e4a-4a23-97f9-3a1800f004e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516408336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2516408336
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1285970760
Short name T454
Test name
Test status
Simulation time 168341694747 ps
CPU time 375.14 seconds
Started Jul 31 06:41:21 PM PDT 24
Finished Jul 31 06:47:36 PM PDT 24
Peak memory 201460 kb
Host smart-b167d0c6-1aaa-4330-9231-f260a1994923
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285970760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1285970760
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2058684278
Short name T753
Test name
Test status
Simulation time 326731956619 ps
CPU time 722.94 seconds
Started Jul 31 06:41:22 PM PDT 24
Finished Jul 31 06:53:25 PM PDT 24
Peak memory 201508 kb
Host smart-ce28e304-4333-4d2b-b4bf-f4cf8fbec6b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058684278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2058684278
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.963474288
Short name T460
Test name
Test status
Simulation time 163123464106 ps
CPU time 337.54 seconds
Started Jul 31 06:41:10 PM PDT 24
Finished Jul 31 06:46:47 PM PDT 24
Peak memory 201384 kb
Host smart-f70e784c-0f0a-4c9b-ae1a-651970227849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963474288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.963474288
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2508909046
Short name T354
Test name
Test status
Simulation time 323011722373 ps
CPU time 724.31 seconds
Started Jul 31 06:41:17 PM PDT 24
Finished Jul 31 06:53:22 PM PDT 24
Peak memory 201428 kb
Host smart-3825ff26-e478-48d6-973a-32eea3529713
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508909046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2508909046
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2011564385
Short name T249
Test name
Test status
Simulation time 553846862130 ps
CPU time 335.63 seconds
Started Jul 31 06:41:25 PM PDT 24
Finished Jul 31 06:47:01 PM PDT 24
Peak memory 201548 kb
Host smart-f63c542b-ec34-4fb7-b56c-a64b0d90744a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011564385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2011564385
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3420782155
Short name T539
Test name
Test status
Simulation time 197833690465 ps
CPU time 90.82 seconds
Started Jul 31 06:41:22 PM PDT 24
Finished Jul 31 06:42:53 PM PDT 24
Peak memory 201416 kb
Host smart-f3e194fc-a4ae-4b07-b8b8-4f59e68f23c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420782155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3420782155
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4290285928
Short name T348
Test name
Test status
Simulation time 81265573529 ps
CPU time 394.07 seconds
Started Jul 31 06:41:28 PM PDT 24
Finished Jul 31 06:48:03 PM PDT 24
Peak memory 201848 kb
Host smart-5d324e8f-ab30-47ea-9e82-c98ae40f1d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290285928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4290285928
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2949777256
Short name T723
Test name
Test status
Simulation time 46589569612 ps
CPU time 102.04 seconds
Started Jul 31 06:41:27 PM PDT 24
Finished Jul 31 06:43:09 PM PDT 24
Peak memory 201392 kb
Host smart-8b3ffdef-7899-4256-b6b8-b29306d89e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949777256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2949777256
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3698735466
Short name T536
Test name
Test status
Simulation time 5097995971 ps
CPU time 2.24 seconds
Started Jul 31 06:41:27 PM PDT 24
Finished Jul 31 06:41:30 PM PDT 24
Peak memory 201408 kb
Host smart-b66648e5-ca7f-4fb7-9ad9-fb7d3dc6fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698735466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3698735466
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.978570456
Short name T356
Test name
Test status
Simulation time 5846016333 ps
CPU time 14.09 seconds
Started Jul 31 06:41:10 PM PDT 24
Finished Jul 31 06:41:24 PM PDT 24
Peak memory 201396 kb
Host smart-ab841b30-096a-4e16-a922-614955582cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978570456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.978570456
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.14315346
Short name T487
Test name
Test status
Simulation time 526107688 ps
CPU time 1.86 seconds
Started Jul 31 06:42:06 PM PDT 24
Finished Jul 31 06:42:08 PM PDT 24
Peak memory 201252 kb
Host smart-fc000f18-c627-43ff-aa19-10b9c970ad9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.14315346
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2368371839
Short name T325
Test name
Test status
Simulation time 495579431049 ps
CPU time 179.99 seconds
Started Jul 31 06:41:53 PM PDT 24
Finished Jul 31 06:44:53 PM PDT 24
Peak memory 201452 kb
Host smart-2e2b4efb-6ed6-4fc1-8b89-5801af4ba58d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368371839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2368371839
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.217779006
Short name T735
Test name
Test status
Simulation time 187641160330 ps
CPU time 427.78 seconds
Started Jul 31 06:41:52 PM PDT 24
Finished Jul 31 06:49:00 PM PDT 24
Peak memory 201556 kb
Host smart-359292b8-fefd-466d-9a5f-edd988440d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217779006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.217779006
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3042853309
Short name T267
Test name
Test status
Simulation time 325322459988 ps
CPU time 177.83 seconds
Started Jul 31 06:41:37 PM PDT 24
Finished Jul 31 06:44:35 PM PDT 24
Peak memory 201400 kb
Host smart-2e689d04-f95c-46f4-889f-02998102558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042853309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3042853309
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1717944964
Short name T415
Test name
Test status
Simulation time 168449669181 ps
CPU time 29.03 seconds
Started Jul 31 06:41:38 PM PDT 24
Finished Jul 31 06:42:07 PM PDT 24
Peak memory 201452 kb
Host smart-7d248efa-9be9-4cc9-988c-c10eedb1b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717944964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1717944964
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2144755101
Short name T397
Test name
Test status
Simulation time 320964721838 ps
CPU time 405.5 seconds
Started Jul 31 06:41:37 PM PDT 24
Finished Jul 31 06:48:23 PM PDT 24
Peak memory 201480 kb
Host smart-6be68d3b-b736-423f-9e09-36b33ab0a9cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144755101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2144755101
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2755939203
Short name T189
Test name
Test status
Simulation time 355973562052 ps
CPU time 144.49 seconds
Started Jul 31 06:41:43 PM PDT 24
Finished Jul 31 06:44:08 PM PDT 24
Peak memory 201360 kb
Host smart-86da8f53-bed9-4ff6-899a-8b6bdc13d7f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755939203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2755939203
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1048229524
Short name T654
Test name
Test status
Simulation time 588068109373 ps
CPU time 1376.1 seconds
Started Jul 31 06:41:49 PM PDT 24
Finished Jul 31 07:04:46 PM PDT 24
Peak memory 201424 kb
Host smart-5428b336-3357-4f72-b337-1ca3db82b2b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048229524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1048229524
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.152805282
Short name T470
Test name
Test status
Simulation time 105889483799 ps
CPU time 340.81 seconds
Started Jul 31 06:41:58 PM PDT 24
Finished Jul 31 06:47:39 PM PDT 24
Peak memory 201868 kb
Host smart-85cde2f5-ee8a-44e5-aa70-114be28a9852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152805282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.152805282
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.182848967
Short name T77
Test name
Test status
Simulation time 31068081780 ps
CPU time 7.55 seconds
Started Jul 31 06:41:52 PM PDT 24
Finished Jul 31 06:42:00 PM PDT 24
Peak memory 201348 kb
Host smart-c2557e05-e6e7-4e70-a4f5-f5057d06e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182848967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.182848967
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.974170705
Short name T738
Test name
Test status
Simulation time 5487683610 ps
CPU time 6.44 seconds
Started Jul 31 06:41:54 PM PDT 24
Finished Jul 31 06:42:00 PM PDT 24
Peak memory 201404 kb
Host smart-524b3104-b50e-46d6-9d84-ae6cb38726a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974170705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.974170705
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3220924143
Short name T689
Test name
Test status
Simulation time 5994690284 ps
CPU time 13.39 seconds
Started Jul 31 06:41:32 PM PDT 24
Finished Jul 31 06:41:45 PM PDT 24
Peak memory 201376 kb
Host smart-7b3087c8-eceb-443d-b5e6-5b6e59e7b086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220924143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3220924143
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.14963201
Short name T457
Test name
Test status
Simulation time 138288676125 ps
CPU time 64.17 seconds
Started Jul 31 06:42:07 PM PDT 24
Finished Jul 31 06:43:11 PM PDT 24
Peak memory 210168 kb
Host smart-0ab44662-067e-43eb-a274-0f2f51c29b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963201 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.14963201
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.201407841
Short name T452
Test name
Test status
Simulation time 487952744 ps
CPU time 0.88 seconds
Started Jul 31 06:42:38 PM PDT 24
Finished Jul 31 06:42:39 PM PDT 24
Peak memory 201224 kb
Host smart-83ba3654-315e-4474-822f-1c8a9f084c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201407841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.201407841
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.827137993
Short name T151
Test name
Test status
Simulation time 328359953103 ps
CPU time 188.68 seconds
Started Jul 31 06:42:17 PM PDT 24
Finished Jul 31 06:45:26 PM PDT 24
Peak memory 201484 kb
Host smart-b3079ff3-df4e-474d-8cdb-be347ecf3ce2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827137993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.827137993
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2537439066
Short name T614
Test name
Test status
Simulation time 320998826140 ps
CPU time 310.12 seconds
Started Jul 31 06:42:11 PM PDT 24
Finished Jul 31 06:47:21 PM PDT 24
Peak memory 201476 kb
Host smart-755d95f4-4a58-468b-812a-36906031f628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537439066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2537439066
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.852025251
Short name T468
Test name
Test status
Simulation time 328783112082 ps
CPU time 179.82 seconds
Started Jul 31 06:42:11 PM PDT 24
Finished Jul 31 06:45:10 PM PDT 24
Peak memory 201416 kb
Host smart-db7d2099-1bf2-484a-a067-121264a70d60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=852025251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.852025251
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2079953977
Short name T463
Test name
Test status
Simulation time 326724349467 ps
CPU time 748.82 seconds
Started Jul 31 06:42:11 PM PDT 24
Finished Jul 31 06:54:40 PM PDT 24
Peak memory 201468 kb
Host smart-b31be3cc-c227-4258-9311-413d38138fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079953977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2079953977
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2692913398
Short name T442
Test name
Test status
Simulation time 329180507504 ps
CPU time 86.45 seconds
Started Jul 31 06:42:11 PM PDT 24
Finished Jul 31 06:43:38 PM PDT 24
Peak memory 201424 kb
Host smart-01b84f32-de82-4feb-b648-8904a6ac44fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692913398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2692913398
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1320320128
Short name T598
Test name
Test status
Simulation time 404717891088 ps
CPU time 402.19 seconds
Started Jul 31 06:42:09 PM PDT 24
Finished Jul 31 06:48:51 PM PDT 24
Peak memory 201424 kb
Host smart-55f40514-f08d-4f22-a595-4e0c45ca9e18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320320128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1320320128
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1226563889
Short name T638
Test name
Test status
Simulation time 87768426154 ps
CPU time 376.24 seconds
Started Jul 31 06:42:21 PM PDT 24
Finished Jul 31 06:48:37 PM PDT 24
Peak memory 201844 kb
Host smart-9f4c9e6e-3aeb-4e43-953f-4dd48d4eab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226563889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1226563889
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3106692183
Short name T65
Test name
Test status
Simulation time 46242516026 ps
CPU time 25.64 seconds
Started Jul 31 06:42:22 PM PDT 24
Finished Jul 31 06:42:48 PM PDT 24
Peak memory 201360 kb
Host smart-813c2731-49f8-4eed-9ffa-d50f799d65c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106692183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3106692183
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.382525546
Short name T367
Test name
Test status
Simulation time 4920956753 ps
CPU time 11.87 seconds
Started Jul 31 06:42:15 PM PDT 24
Finished Jul 31 06:42:27 PM PDT 24
Peak memory 201336 kb
Host smart-bc89e53a-86b8-4802-a8e1-ebd855733497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382525546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.382525546
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1611514193
Short name T728
Test name
Test status
Simulation time 5816117532 ps
CPU time 7.38 seconds
Started Jul 31 06:42:15 PM PDT 24
Finished Jul 31 06:42:23 PM PDT 24
Peak memory 201388 kb
Host smart-5cadfe0b-7387-4061-9a55-d431ab89f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611514193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1611514193
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.559426667
Short name T314
Test name
Test status
Simulation time 338388582827 ps
CPU time 195.46 seconds
Started Jul 31 06:42:21 PM PDT 24
Finished Jul 31 06:45:36 PM PDT 24
Peak memory 201560 kb
Host smart-5dae2925-9583-4eff-9af3-ab76bf7bddc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559426667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
559426667
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.346166963
Short name T565
Test name
Test status
Simulation time 304370747 ps
CPU time 1.34 seconds
Started Jul 31 06:42:53 PM PDT 24
Finished Jul 31 06:42:55 PM PDT 24
Peak memory 201260 kb
Host smart-ef349af5-5eb8-4dfd-b6f8-10341d21244c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346166963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.346166963
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.514201547
Short name T237
Test name
Test status
Simulation time 187389586498 ps
CPU time 26.76 seconds
Started Jul 31 06:42:43 PM PDT 24
Finished Jul 31 06:43:10 PM PDT 24
Peak memory 201544 kb
Host smart-52ff2ee2-2f81-4864-ae25-34d3245c30a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514201547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.514201547
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.321559192
Short name T534
Test name
Test status
Simulation time 488880252047 ps
CPU time 1091.18 seconds
Started Jul 31 06:42:37 PM PDT 24
Finished Jul 31 07:00:48 PM PDT 24
Peak memory 201464 kb
Host smart-47cc120a-f3e1-44e9-9e5a-df1ae1dc0e35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=321559192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.321559192
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2040827003
Short name T287
Test name
Test status
Simulation time 487358189107 ps
CPU time 991.9 seconds
Started Jul 31 06:42:38 PM PDT 24
Finished Jul 31 06:59:10 PM PDT 24
Peak memory 201480 kb
Host smart-bd895932-3099-4da0-99dc-c05bc882b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040827003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2040827003
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1494370795
Short name T584
Test name
Test status
Simulation time 493365958263 ps
CPU time 267.15 seconds
Started Jul 31 06:42:38 PM PDT 24
Finished Jul 31 06:47:05 PM PDT 24
Peak memory 201464 kb
Host smart-3087c228-003e-429c-9500-e6df4f4e78c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494370795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1494370795
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2103210218
Short name T742
Test name
Test status
Simulation time 529943508408 ps
CPU time 164 seconds
Started Jul 31 06:42:39 PM PDT 24
Finished Jul 31 06:45:23 PM PDT 24
Peak memory 201444 kb
Host smart-e742b08b-8720-40c1-aaf5-650ef3ea9361
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103210218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2103210218
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.353772975
Short name T748
Test name
Test status
Simulation time 591393181037 ps
CPU time 656.96 seconds
Started Jul 31 06:42:39 PM PDT 24
Finished Jul 31 06:53:36 PM PDT 24
Peak memory 201476 kb
Host smart-7faa76c5-d7cd-491a-a3a0-5b9e19696f5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353772975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.353772975
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4275551447
Short name T48
Test name
Test status
Simulation time 132852608070 ps
CPU time 673.11 seconds
Started Jul 31 06:42:54 PM PDT 24
Finished Jul 31 06:54:07 PM PDT 24
Peak memory 201816 kb
Host smart-dea4f4b6-5b4f-4d27-bac6-28053b1fb16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275551447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4275551447
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.308669256
Short name T378
Test name
Test status
Simulation time 38381354349 ps
CPU time 90.35 seconds
Started Jul 31 06:42:49 PM PDT 24
Finished Jul 31 06:44:19 PM PDT 24
Peak memory 201392 kb
Host smart-83c2da67-abf5-4de7-8c0a-98091b55dc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308669256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.308669256
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.956729523
Short name T734
Test name
Test status
Simulation time 3535754320 ps
CPU time 2.79 seconds
Started Jul 31 06:42:43 PM PDT 24
Finished Jul 31 06:42:46 PM PDT 24
Peak memory 201360 kb
Host smart-65fdda67-c075-40d0-a459-d2f1e0115048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956729523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.956729523
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3977824913
Short name T405
Test name
Test status
Simulation time 5810523318 ps
CPU time 3.91 seconds
Started Jul 31 06:42:33 PM PDT 24
Finished Jul 31 06:42:37 PM PDT 24
Peak memory 201316 kb
Host smart-c78ed75e-86ec-443d-bc97-89ed49f853ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977824913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3977824913
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3128342675
Short name T709
Test name
Test status
Simulation time 328507702082 ps
CPU time 75.53 seconds
Started Jul 31 06:42:54 PM PDT 24
Finished Jul 31 06:44:10 PM PDT 24
Peak memory 210092 kb
Host smart-bdb70a86-227b-491c-ad3a-3b69b30f9703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128342675 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3128342675
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.4041532733
Short name T784
Test name
Test status
Simulation time 312218409 ps
CPU time 0.84 seconds
Started Jul 31 06:43:14 PM PDT 24
Finished Jul 31 06:43:15 PM PDT 24
Peak memory 201248 kb
Host smart-33e856db-d062-4111-8964-1b7921059fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041532733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.4041532733
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2700943030
Short name T674
Test name
Test status
Simulation time 332686566003 ps
CPU time 199.59 seconds
Started Jul 31 06:43:04 PM PDT 24
Finished Jul 31 06:46:23 PM PDT 24
Peak memory 201432 kb
Host smart-2577ca0b-ddcc-4138-afb6-48310b017611
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700943030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2700943030
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.980731877
Short name T671
Test name
Test status
Simulation time 487855046499 ps
CPU time 285.58 seconds
Started Jul 31 06:42:59 PM PDT 24
Finished Jul 31 06:47:45 PM PDT 24
Peak memory 201464 kb
Host smart-37f51060-d62b-4fdf-8220-cce17213d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980731877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.980731877
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4165249581
Short name T503
Test name
Test status
Simulation time 324352531525 ps
CPU time 810.92 seconds
Started Jul 31 06:43:04 PM PDT 24
Finished Jul 31 06:56:35 PM PDT 24
Peak memory 201536 kb
Host smart-65e12431-7b8b-4d93-a3ba-4fe60d707e79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165249581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4165249581
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.259326718
Short name T691
Test name
Test status
Simulation time 327238851482 ps
CPU time 679.62 seconds
Started Jul 31 06:43:00 PM PDT 24
Finished Jul 31 06:54:19 PM PDT 24
Peak memory 201460 kb
Host smart-5d658008-ac7d-4cc6-abec-27bad900f50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259326718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.259326718
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1479925190
Short name T579
Test name
Test status
Simulation time 159372106281 ps
CPU time 297.77 seconds
Started Jul 31 06:43:00 PM PDT 24
Finished Jul 31 06:47:58 PM PDT 24
Peak memory 201428 kb
Host smart-4495b931-119e-44e2-8549-b4f490bf4a25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479925190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1479925190
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2916910457
Short name T171
Test name
Test status
Simulation time 347574184475 ps
CPU time 405.75 seconds
Started Jul 31 06:43:05 PM PDT 24
Finished Jul 31 06:49:51 PM PDT 24
Peak memory 201464 kb
Host smart-9fcfa598-2417-4606-8c31-dc83ff62c0cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916910457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2916910457
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2452053260
Short name T202
Test name
Test status
Simulation time 618304609862 ps
CPU time 1303.22 seconds
Started Jul 31 06:43:03 PM PDT 24
Finished Jul 31 07:04:47 PM PDT 24
Peak memory 201452 kb
Host smart-9510b7d2-b6fc-4621-acd9-3da24a28e1b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452053260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2452053260
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2906112866
Short name T215
Test name
Test status
Simulation time 71151585348 ps
CPU time 287.03 seconds
Started Jul 31 06:43:15 PM PDT 24
Finished Jul 31 06:48:02 PM PDT 24
Peak memory 201824 kb
Host smart-8d58b1be-54fa-4599-800c-573d2ada9cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906112866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2906112866
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3892896474
Short name T758
Test name
Test status
Simulation time 43599583112 ps
CPU time 97.99 seconds
Started Jul 31 06:43:10 PM PDT 24
Finished Jul 31 06:44:48 PM PDT 24
Peak memory 201388 kb
Host smart-2103eadd-a0e6-4995-aa35-3a88681fea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892896474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3892896474
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.411234660
Short name T107
Test name
Test status
Simulation time 3481227282 ps
CPU time 7.67 seconds
Started Jul 31 06:43:10 PM PDT 24
Finished Jul 31 06:43:17 PM PDT 24
Peak memory 201332 kb
Host smart-45dcf340-08b9-4709-a042-ae2ee00d572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411234660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.411234660
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.132932171
Short name T736
Test name
Test status
Simulation time 5770450220 ps
CPU time 4.41 seconds
Started Jul 31 06:42:59 PM PDT 24
Finished Jul 31 06:43:03 PM PDT 24
Peak memory 201388 kb
Host smart-f265abf6-88f8-43ce-a6ef-b3f87a74844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132932171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.132932171
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.376239652
Short name T713
Test name
Test status
Simulation time 239143575890 ps
CPU time 37.13 seconds
Started Jul 31 06:43:14 PM PDT 24
Finished Jul 31 06:43:51 PM PDT 24
Peak memory 201452 kb
Host smart-71b082a2-1db6-45e8-8d8b-683274be44c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376239652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
376239652
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.765652530
Short name T268
Test name
Test status
Simulation time 230806229385 ps
CPU time 247.71 seconds
Started Jul 31 06:43:15 PM PDT 24
Finished Jul 31 06:47:22 PM PDT 24
Peak memory 209772 kb
Host smart-893273d5-69ed-46af-a265-9d8f53335a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765652530 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.765652530
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.704808160
Short name T523
Test name
Test status
Simulation time 306887272 ps
CPU time 1.31 seconds
Started Jul 31 06:43:40 PM PDT 24
Finished Jul 31 06:43:41 PM PDT 24
Peak memory 201252 kb
Host smart-64c12d2c-284d-4aae-af09-01e6a7ab69f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704808160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.704808160
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4156809086
Short name T32
Test name
Test status
Simulation time 249130598535 ps
CPU time 474.81 seconds
Started Jul 31 06:43:32 PM PDT 24
Finished Jul 31 06:51:27 PM PDT 24
Peak memory 201464 kb
Host smart-7e591643-1bd4-4d69-aac2-d361c83f50c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156809086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4156809086
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1997519403
Short name T238
Test name
Test status
Simulation time 467930028027 ps
CPU time 1035.51 seconds
Started Jul 31 06:43:31 PM PDT 24
Finished Jul 31 07:00:47 PM PDT 24
Peak memory 201416 kb
Host smart-aa323d9c-846e-4594-b27f-45fbf7b4b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997519403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1997519403
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1694378191
Short name T706
Test name
Test status
Simulation time 328606482289 ps
CPU time 693.26 seconds
Started Jul 31 06:43:26 PM PDT 24
Finished Jul 31 06:54:59 PM PDT 24
Peak memory 201540 kb
Host smart-bf2a8d6f-9f54-4bf4-ae04-7b737fc3d792
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694378191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1694378191
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2382348556
Short name T12
Test name
Test status
Simulation time 162392717992 ps
CPU time 371.1 seconds
Started Jul 31 06:43:21 PM PDT 24
Finished Jul 31 06:49:32 PM PDT 24
Peak memory 201432 kb
Host smart-771fcd06-c8d1-49d4-b108-926485b805db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382348556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2382348556
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2456534056
Short name T554
Test name
Test status
Simulation time 484553262712 ps
CPU time 1172.3 seconds
Started Jul 31 06:43:27 PM PDT 24
Finished Jul 31 07:02:59 PM PDT 24
Peak memory 201460 kb
Host smart-6114e764-1d1f-445b-8b66-d8781045be74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456534056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2456534056
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3842787422
Short name T381
Test name
Test status
Simulation time 205702141578 ps
CPU time 320 seconds
Started Jul 31 06:43:25 PM PDT 24
Finished Jul 31 06:48:45 PM PDT 24
Peak memory 201452 kb
Host smart-92d5781f-8cf5-4deb-afa9-a05fdccdc606
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842787422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3842787422
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1414369466
Short name T489
Test name
Test status
Simulation time 116011359228 ps
CPU time 518.04 seconds
Started Jul 31 06:43:35 PM PDT 24
Finished Jul 31 06:52:14 PM PDT 24
Peak memory 201808 kb
Host smart-63e194e6-0712-482b-b784-a5b2782b3f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414369466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1414369466
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.351699739
Short name T505
Test name
Test status
Simulation time 41830160263 ps
CPU time 95.77 seconds
Started Jul 31 06:43:32 PM PDT 24
Finished Jul 31 06:45:08 PM PDT 24
Peak memory 201332 kb
Host smart-b0c53cc1-667b-424b-b4d8-55be047d116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351699739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.351699739
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.705651980
Short name T559
Test name
Test status
Simulation time 4984286756 ps
CPU time 1.98 seconds
Started Jul 31 06:43:29 PM PDT 24
Finished Jul 31 06:43:31 PM PDT 24
Peak memory 201396 kb
Host smart-d9ae2287-dbc0-4b23-9619-0cb842c36e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705651980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.705651980
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3312266418
Short name T773
Test name
Test status
Simulation time 6132780085 ps
CPU time 4.05 seconds
Started Jul 31 06:43:19 PM PDT 24
Finished Jul 31 06:43:23 PM PDT 24
Peak memory 201372 kb
Host smart-4831aa61-2e50-415d-af13-51905ae96e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312266418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3312266418
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3559963138
Short name T41
Test name
Test status
Simulation time 82199676555 ps
CPU time 146.63 seconds
Started Jul 31 06:43:36 PM PDT 24
Finished Jul 31 06:46:02 PM PDT 24
Peak memory 213624 kb
Host smart-52586dc2-10a9-46c2-a265-82b2e8203f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559963138 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3559963138
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.635488206
Short name T433
Test name
Test status
Simulation time 383706217 ps
CPU time 1.02 seconds
Started Jul 31 06:44:03 PM PDT 24
Finished Jul 31 06:44:04 PM PDT 24
Peak memory 201232 kb
Host smart-d7116c7f-afe3-4473-87fa-834b816a5c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635488206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.635488206
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2762176287
Short name T764
Test name
Test status
Simulation time 494964259037 ps
CPU time 1198.69 seconds
Started Jul 31 06:43:49 PM PDT 24
Finished Jul 31 07:03:48 PM PDT 24
Peak memory 201472 kb
Host smart-ecc089e6-c230-4b03-92f7-7e644d9a77b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762176287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2762176287
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1290323736
Short name T580
Test name
Test status
Simulation time 323055919766 ps
CPU time 423.02 seconds
Started Jul 31 06:43:47 PM PDT 24
Finished Jul 31 06:50:51 PM PDT 24
Peak memory 201432 kb
Host smart-cf8dd2ba-4e55-4b74-a8e6-3c3b7405bf42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290323736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1290323736
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1803263875
Short name T693
Test name
Test status
Simulation time 480017041825 ps
CPU time 487.14 seconds
Started Jul 31 06:43:40 PM PDT 24
Finished Jul 31 06:51:48 PM PDT 24
Peak memory 201452 kb
Host smart-1c5229e2-e7a2-40df-b16a-162947368e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803263875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1803263875
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3629406995
Short name T622
Test name
Test status
Simulation time 161962752284 ps
CPU time 356.8 seconds
Started Jul 31 06:43:45 PM PDT 24
Finished Jul 31 06:49:42 PM PDT 24
Peak memory 201472 kb
Host smart-9d8ca54b-41ab-412e-80f3-9b58bc419e55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629406995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3629406995
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3517206605
Short name T261
Test name
Test status
Simulation time 183021527787 ps
CPU time 398.18 seconds
Started Jul 31 06:43:46 PM PDT 24
Finished Jul 31 06:50:24 PM PDT 24
Peak memory 201476 kb
Host smart-53ce6d33-47b6-4293-9756-570217f82533
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517206605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3517206605
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4204091703
Short name T385
Test name
Test status
Simulation time 191944077229 ps
CPU time 126.98 seconds
Started Jul 31 06:43:46 PM PDT 24
Finished Jul 31 06:45:53 PM PDT 24
Peak memory 201464 kb
Host smart-72e00e7f-eed2-49b9-be0d-172d77ae46ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204091703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4204091703
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4140099319
Short name T411
Test name
Test status
Simulation time 72274815091 ps
CPU time 368.48 seconds
Started Jul 31 06:43:57 PM PDT 24
Finished Jul 31 06:50:06 PM PDT 24
Peak memory 201832 kb
Host smart-f14158c5-e164-4aa9-9144-ecc16fdc5436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140099319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4140099319
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1992438726
Short name T472
Test name
Test status
Simulation time 33499976643 ps
CPU time 20.64 seconds
Started Jul 31 06:43:51 PM PDT 24
Finished Jul 31 06:44:12 PM PDT 24
Peak memory 201388 kb
Host smart-d5808ac2-54fb-4f27-9464-2dc75155814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992438726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1992438726
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.334737809
Short name T51
Test name
Test status
Simulation time 3707665449 ps
CPU time 2.84 seconds
Started Jul 31 06:43:53 PM PDT 24
Finished Jul 31 06:43:56 PM PDT 24
Peak memory 201284 kb
Host smart-78115c74-6a7c-4bec-a27e-41fb6a869cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334737809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.334737809
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3510581911
Short name T779
Test name
Test status
Simulation time 5789325483 ps
CPU time 2.31 seconds
Started Jul 31 06:43:40 PM PDT 24
Finished Jul 31 06:43:43 PM PDT 24
Peak memory 201364 kb
Host smart-9fb3e89f-6d22-4dad-bcbe-afccdebea7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510581911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3510581911
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.717583677
Short name T560
Test name
Test status
Simulation time 95944134615 ps
CPU time 270.92 seconds
Started Jul 31 06:43:58 PM PDT 24
Finished Jul 31 06:48:29 PM PDT 24
Peak memory 210180 kb
Host smart-7e86ac8f-77b5-445b-b828-7bcee5571a7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717583677 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.717583677
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3600066820
Short name T623
Test name
Test status
Simulation time 483941702 ps
CPU time 0.72 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:38:01 PM PDT 24
Peak memory 201256 kb
Host smart-14f5e953-02d8-4fa8-80f9-b8383374cc4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600066820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3600066820
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.871817221
Short name T13
Test name
Test status
Simulation time 164368151633 ps
CPU time 91.71 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:39:31 PM PDT 24
Peak memory 201468 kb
Host smart-8bee24fd-35c4-45b4-bd48-998c4555a5d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871817221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.871817221
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3729720175
Short name T500
Test name
Test status
Simulation time 164199077890 ps
CPU time 92.21 seconds
Started Jul 31 06:37:59 PM PDT 24
Finished Jul 31 06:39:32 PM PDT 24
Peak memory 201544 kb
Host smart-6d19a743-2092-428e-b54d-4eebafcf8d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729720175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3729720175
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.857823290
Short name T375
Test name
Test status
Simulation time 163274719665 ps
CPU time 375.38 seconds
Started Jul 31 06:38:06 PM PDT 24
Finished Jul 31 06:44:21 PM PDT 24
Peak memory 201436 kb
Host smart-fbf97075-f0d9-45c2-b9de-cf032e72905c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=857823290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.857823290
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1415407197
Short name T603
Test name
Test status
Simulation time 164232644442 ps
CPU time 104.37 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:39:45 PM PDT 24
Peak memory 201460 kb
Host smart-da08d74c-1f8e-4fcb-87fb-044c9938099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415407197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1415407197
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2347124534
Short name T572
Test name
Test status
Simulation time 163664620455 ps
CPU time 277.03 seconds
Started Jul 31 06:38:01 PM PDT 24
Finished Jul 31 06:42:38 PM PDT 24
Peak memory 201452 kb
Host smart-e7ee4663-6ca9-4899-b9b3-65e5550a86f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347124534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2347124534
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1000222195
Short name T336
Test name
Test status
Simulation time 570893272955 ps
CPU time 1239.13 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:58:40 PM PDT 24
Peak memory 201524 kb
Host smart-a8e14283-4cb8-41cf-9461-c2a82ee7ddb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000222195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1000222195
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1182463377
Short name T364
Test name
Test status
Simulation time 609878437014 ps
CPU time 637.39 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:48:38 PM PDT 24
Peak memory 201476 kb
Host smart-66f896c7-e7a2-4506-9b2b-34a7d379b6aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182463377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1182463377
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.656000844
Short name T349
Test name
Test status
Simulation time 119982935986 ps
CPU time 485.67 seconds
Started Jul 31 06:37:59 PM PDT 24
Finished Jul 31 06:46:05 PM PDT 24
Peak memory 201832 kb
Host smart-893a6f67-dd3b-4cd4-89e9-5e4154e88c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656000844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.656000844
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3872557597
Short name T363
Test name
Test status
Simulation time 27574049179 ps
CPU time 16.9 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:38:17 PM PDT 24
Peak memory 201360 kb
Host smart-8e400fda-1861-4e3a-bb07-3f8ab08f55fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872557597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3872557597
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1859549258
Short name T9
Test name
Test status
Simulation time 4784483227 ps
CPU time 3.46 seconds
Started Jul 31 06:38:01 PM PDT 24
Finished Jul 31 06:38:04 PM PDT 24
Peak memory 201344 kb
Host smart-bca77784-9166-4980-8b8a-294b3bd78c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859549258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1859549258
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3953575952
Short name T78
Test name
Test status
Simulation time 4184840566 ps
CPU time 10.63 seconds
Started Jul 31 06:38:01 PM PDT 24
Finished Jul 31 06:38:11 PM PDT 24
Peak memory 217248 kb
Host smart-6d7019b8-9586-48f1-a361-27d474405f17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953575952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3953575952
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2601636847
Short name T515
Test name
Test status
Simulation time 5985746408 ps
CPU time 4.01 seconds
Started Jul 31 06:37:55 PM PDT 24
Finished Jul 31 06:37:59 PM PDT 24
Peak memory 201356 kb
Host smart-54267b41-1ef6-456e-8d09-c67c8d03002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601636847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2601636847
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.564205806
Short name T703
Test name
Test status
Simulation time 5861398815 ps
CPU time 3.57 seconds
Started Jul 31 06:38:01 PM PDT 24
Finished Jul 31 06:38:05 PM PDT 24
Peak memory 201356 kb
Host smart-907e12e1-26f6-498d-ab6f-bbd195aa6511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564205806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.564205806
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2776251413
Short name T199
Test name
Test status
Simulation time 542305192986 ps
CPU time 1259.51 seconds
Started Jul 31 06:44:21 PM PDT 24
Finished Jul 31 07:05:21 PM PDT 24
Peak memory 201452 kb
Host smart-98a573db-83ae-4cdd-98f1-ed383982edf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776251413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2776251413
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2417250472
Short name T163
Test name
Test status
Simulation time 161951831155 ps
CPU time 93.14 seconds
Started Jul 31 06:44:16 PM PDT 24
Finished Jul 31 06:45:49 PM PDT 24
Peak memory 201492 kb
Host smart-6293a36e-f334-4a7c-8018-e0c65eca5d27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417250472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2417250472
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.701058302
Short name T7
Test name
Test status
Simulation time 349340310783 ps
CPU time 205.33 seconds
Started Jul 31 06:44:10 PM PDT 24
Finished Jul 31 06:47:36 PM PDT 24
Peak memory 201452 kb
Host smart-e34d9260-d447-4aa4-b5a9-e15af1763be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701058302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.701058302
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1192900116
Short name T437
Test name
Test status
Simulation time 164660409457 ps
CPU time 84.84 seconds
Started Jul 31 06:44:23 PM PDT 24
Finished Jul 31 06:45:48 PM PDT 24
Peak memory 201424 kb
Host smart-40d90397-79e7-49da-a2d3-f2909c7e6bb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192900116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1192900116
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.385423606
Short name T561
Test name
Test status
Simulation time 371847899219 ps
CPU time 190.91 seconds
Started Jul 31 06:44:16 PM PDT 24
Finished Jul 31 06:47:27 PM PDT 24
Peak memory 201452 kb
Host smart-0e98b8c7-bb58-4f0d-b85a-36df366ddb4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385423606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.385423606
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2150874637
Short name T521
Test name
Test status
Simulation time 614306834919 ps
CPU time 283.2 seconds
Started Jul 31 06:44:18 PM PDT 24
Finished Jul 31 06:49:02 PM PDT 24
Peak memory 201552 kb
Host smart-90cdee88-281d-49f1-9c3f-3bb089f3a906
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150874637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2150874637
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2143350729
Short name T351
Test name
Test status
Simulation time 100311312084 ps
CPU time 341.6 seconds
Started Jul 31 06:44:27 PM PDT 24
Finished Jul 31 06:50:08 PM PDT 24
Peak memory 201912 kb
Host smart-ce1c3dd4-b480-45be-acb3-cf2f72ea2be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143350729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2143350729
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3039483693
Short name T507
Test name
Test status
Simulation time 45137283992 ps
CPU time 110.21 seconds
Started Jul 31 06:44:34 PM PDT 24
Finished Jul 31 06:46:25 PM PDT 24
Peak memory 201384 kb
Host smart-4a0582d6-4c60-4a64-9448-d78388eb84f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039483693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3039483693
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1581983465
Short name T531
Test name
Test status
Simulation time 3171161597 ps
CPU time 7.47 seconds
Started Jul 31 06:44:35 PM PDT 24
Finished Jul 31 06:44:43 PM PDT 24
Peak memory 201308 kb
Host smart-37a124d8-b6f8-49dd-9896-b0ac99b18bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581983465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1581983465
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3902575627
Short name T441
Test name
Test status
Simulation time 5914612768 ps
CPU time 13.81 seconds
Started Jul 31 06:44:11 PM PDT 24
Finished Jul 31 06:44:25 PM PDT 24
Peak memory 201384 kb
Host smart-46e82b0f-f124-4315-97e0-2e850b5c4ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902575627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3902575627
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3309066723
Short name T37
Test name
Test status
Simulation time 137701219967 ps
CPU time 536.68 seconds
Started Jul 31 06:44:35 PM PDT 24
Finished Jul 31 06:53:32 PM PDT 24
Peak memory 210024 kb
Host smart-f444165a-2d2e-4569-8d4c-6125777ac3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309066723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3309066723
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1814968626
Short name T513
Test name
Test status
Simulation time 387045350 ps
CPU time 1.47 seconds
Started Jul 31 06:44:50 PM PDT 24
Finished Jul 31 06:44:51 PM PDT 24
Peak memory 201252 kb
Host smart-4be8c82d-a026-4837-8222-0186613a34e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814968626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1814968626
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1180952926
Short name T302
Test name
Test status
Simulation time 197198938807 ps
CPU time 115.53 seconds
Started Jul 31 06:44:44 PM PDT 24
Finished Jul 31 06:46:40 PM PDT 24
Peak memory 201500 kb
Host smart-3ecf2391-c617-4577-b101-d5b44bba258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180952926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1180952926
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.500882008
Short name T687
Test name
Test status
Simulation time 161229012007 ps
CPU time 180.43 seconds
Started Jul 31 06:44:38 PM PDT 24
Finished Jul 31 06:47:38 PM PDT 24
Peak memory 201460 kb
Host smart-983d7a32-c6e5-4001-b8c1-e210c4099ad4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=500882008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.500882008
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.4291498446
Short name T427
Test name
Test status
Simulation time 160631239062 ps
CPU time 34.49 seconds
Started Jul 31 06:44:36 PM PDT 24
Finished Jul 31 06:45:11 PM PDT 24
Peak memory 201376 kb
Host smart-405eeba4-9df6-4b04-9e10-afe68e60eeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291498446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4291498446
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1202456156
Short name T465
Test name
Test status
Simulation time 329358725708 ps
CPU time 188.51 seconds
Started Jul 31 06:44:38 PM PDT 24
Finished Jul 31 06:47:47 PM PDT 24
Peak memory 201448 kb
Host smart-8654f940-8d92-4d39-b7d8-c0681b9e83f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202456156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1202456156
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3955137917
Short name T483
Test name
Test status
Simulation time 361638593950 ps
CPU time 794.76 seconds
Started Jul 31 06:44:39 PM PDT 24
Finished Jul 31 06:57:54 PM PDT 24
Peak memory 201472 kb
Host smart-88eb786d-c89e-4734-981e-a560027c3585
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955137917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3955137917
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3866409919
Short name T711
Test name
Test status
Simulation time 204956934123 ps
CPU time 498.98 seconds
Started Jul 31 06:44:44 PM PDT 24
Finished Jul 31 06:53:03 PM PDT 24
Peak memory 201420 kb
Host smart-7d2e516e-67f6-4153-8a93-08a2ee15325e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866409919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3866409919
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2793957452
Short name T678
Test name
Test status
Simulation time 38768598169 ps
CPU time 89.51 seconds
Started Jul 31 06:44:45 PM PDT 24
Finished Jul 31 06:46:15 PM PDT 24
Peak memory 201356 kb
Host smart-0ff85121-d5b5-48fd-acbe-4df4071bed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793957452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2793957452
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1756890752
Short name T366
Test name
Test status
Simulation time 2716997157 ps
CPU time 6.83 seconds
Started Jul 31 06:44:44 PM PDT 24
Finished Jul 31 06:44:51 PM PDT 24
Peak memory 201336 kb
Host smart-b453c9c3-29eb-457a-b31b-a6528241a336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756890752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1756890752
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1499125234
Short name T685
Test name
Test status
Simulation time 5735252950 ps
CPU time 3.81 seconds
Started Jul 31 06:44:35 PM PDT 24
Finished Jul 31 06:44:39 PM PDT 24
Peak memory 201316 kb
Host smart-80687f23-84fa-4abd-9f55-9fab704e6929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499125234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1499125234
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1193801817
Short name T498
Test name
Test status
Simulation time 365846973048 ps
CPU time 210.37 seconds
Started Jul 31 06:44:50 PM PDT 24
Finished Jul 31 06:48:20 PM PDT 24
Peak memory 201456 kb
Host smart-57be8f04-9624-4b97-b243-fde83558bfb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193801817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1193801817
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3208989570
Short name T646
Test name
Test status
Simulation time 37485281171 ps
CPU time 79.28 seconds
Started Jul 31 06:44:49 PM PDT 24
Finished Jul 31 06:46:09 PM PDT 24
Peak memory 209728 kb
Host smart-3c5d2664-d754-4754-8288-73b1ddae35e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208989570 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3208989570
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2913777098
Short name T519
Test name
Test status
Simulation time 541956790 ps
CPU time 1.18 seconds
Started Jul 31 06:45:06 PM PDT 24
Finished Jul 31 06:45:07 PM PDT 24
Peak memory 201228 kb
Host smart-1542a00a-101c-4b07-a476-27a67375cb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913777098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2913777098
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3340788746
Short name T186
Test name
Test status
Simulation time 327264570490 ps
CPU time 135.58 seconds
Started Jul 31 06:45:02 PM PDT 24
Finished Jul 31 06:47:18 PM PDT 24
Peak memory 201400 kb
Host smart-1b0bceea-959d-4ca0-b8d6-bde9c335b8e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340788746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3340788746
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3688495587
Short name T241
Test name
Test status
Simulation time 160050265064 ps
CPU time 390.82 seconds
Started Jul 31 06:44:58 PM PDT 24
Finished Jul 31 06:51:29 PM PDT 24
Peak memory 201524 kb
Host smart-4aafcde7-0dc5-436b-af2f-6333b357f8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688495587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3688495587
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3367124869
Short name T714
Test name
Test status
Simulation time 335893146849 ps
CPU time 405.71 seconds
Started Jul 31 06:44:56 PM PDT 24
Finished Jul 31 06:51:42 PM PDT 24
Peak memory 201364 kb
Host smart-a8884853-4cf4-48e2-b5b2-97c889ed2523
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367124869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3367124869
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3840274886
Short name T285
Test name
Test status
Simulation time 162488215713 ps
CPU time 338.51 seconds
Started Jul 31 06:44:55 PM PDT 24
Finished Jul 31 06:50:33 PM PDT 24
Peak memory 201476 kb
Host smart-da2c9440-c986-4487-9dea-3fbcf8c78482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840274886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3840274886
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.281701045
Short name T431
Test name
Test status
Simulation time 332029483733 ps
CPU time 673.63 seconds
Started Jul 31 06:44:57 PM PDT 24
Finished Jul 31 06:56:11 PM PDT 24
Peak memory 201380 kb
Host smart-c1bfc221-d987-478c-b844-189075ff2ed7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=281701045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.281701045
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.523475471
Short name T657
Test name
Test status
Simulation time 204834747132 ps
CPU time 248.28 seconds
Started Jul 31 06:45:00 PM PDT 24
Finished Jul 31 06:49:09 PM PDT 24
Peak memory 201452 kb
Host smart-7992644b-5fec-4d4a-b7e4-923a9746165f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523475471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.523475471
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.4203068974
Short name T347
Test name
Test status
Simulation time 110514266231 ps
CPU time 556.76 seconds
Started Jul 31 06:45:07 PM PDT 24
Finished Jul 31 06:54:24 PM PDT 24
Peak memory 201836 kb
Host smart-897bff40-439b-4f59-bdcf-c87371e12919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203068974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.4203068974
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1974863391
Short name T428
Test name
Test status
Simulation time 42734189078 ps
CPU time 52.17 seconds
Started Jul 31 06:45:07 PM PDT 24
Finished Jul 31 06:45:59 PM PDT 24
Peak memory 201348 kb
Host smart-e77bb114-b1ca-4383-bf3a-02f4a1db8d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974863391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1974863391
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.233251116
Short name T479
Test name
Test status
Simulation time 4082231492 ps
CPU time 9.63 seconds
Started Jul 31 06:45:05 PM PDT 24
Finished Jul 31 06:45:15 PM PDT 24
Peak memory 201360 kb
Host smart-637b3bc2-33c4-43bf-ae6b-1fae36549cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233251116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.233251116
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3982167604
Short name T682
Test name
Test status
Simulation time 6120188458 ps
CPU time 7.58 seconds
Started Jul 31 06:44:49 PM PDT 24
Finished Jul 31 06:44:57 PM PDT 24
Peak memory 201356 kb
Host smart-07694d44-ecdd-4555-9ceb-bb337eaced8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982167604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3982167604
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3768704353
Short name T108
Test name
Test status
Simulation time 344097508889 ps
CPU time 842 seconds
Started Jul 31 06:45:07 PM PDT 24
Finished Jul 31 06:59:09 PM PDT 24
Peak memory 201500 kb
Host smart-e93c918a-3e60-49c7-a94d-a856a61da4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768704353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3768704353
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2999950000
Short name T684
Test name
Test status
Simulation time 108494007202 ps
CPU time 135.15 seconds
Started Jul 31 06:45:07 PM PDT 24
Finished Jul 31 06:47:22 PM PDT 24
Peak memory 216516 kb
Host smart-3b589493-a090-4e16-8b9f-86c825b75b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999950000 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2999950000
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2044149520
Short name T4
Test name
Test status
Simulation time 468647833 ps
CPU time 1.73 seconds
Started Jul 31 06:45:26 PM PDT 24
Finished Jul 31 06:45:27 PM PDT 24
Peak memory 201212 kb
Host smart-333c3d6e-491d-4611-bef3-96cedda92851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044149520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2044149520
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.907738303
Short name T106
Test name
Test status
Simulation time 369880676877 ps
CPU time 53 seconds
Started Jul 31 06:45:12 PM PDT 24
Finished Jul 31 06:46:05 PM PDT 24
Peak memory 201440 kb
Host smart-b3271a26-a2f7-4315-bb96-786c63fe9332
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907738303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.907738303
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3178235957
Short name T600
Test name
Test status
Simulation time 326399817700 ps
CPU time 100.63 seconds
Started Jul 31 06:45:11 PM PDT 24
Finished Jul 31 06:46:52 PM PDT 24
Peak memory 201452 kb
Host smart-42887561-c216-46a8-8b11-d9bd626c0fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178235957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3178235957
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.927991746
Short name T788
Test name
Test status
Simulation time 492984296575 ps
CPU time 1184.82 seconds
Started Jul 31 06:45:12 PM PDT 24
Finished Jul 31 07:04:57 PM PDT 24
Peak memory 201352 kb
Host smart-8a2a0b4f-8b9f-4ae5-aa74-5b265f1b5e3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=927991746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.927991746
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2311172254
Short name T206
Test name
Test status
Simulation time 491047893478 ps
CPU time 146.9 seconds
Started Jul 31 06:45:06 PM PDT 24
Finished Jul 31 06:47:33 PM PDT 24
Peak memory 201404 kb
Host smart-1f3d1eff-29a0-4fce-8d76-78c1fb1a44f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311172254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2311172254
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3122621701
Short name T502
Test name
Test status
Simulation time 333875238253 ps
CPU time 795.85 seconds
Started Jul 31 06:45:13 PM PDT 24
Finished Jul 31 06:58:29 PM PDT 24
Peak memory 201400 kb
Host smart-3dcc74a8-364a-4b95-92a2-d3df94fd4952
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122621701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3122621701
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1424801556
Short name T248
Test name
Test status
Simulation time 549410136376 ps
CPU time 650.89 seconds
Started Jul 31 06:45:14 PM PDT 24
Finished Jul 31 06:56:05 PM PDT 24
Peak memory 201420 kb
Host smart-546665f8-86d0-41f3-98a9-4d22b7015aaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424801556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1424801556
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1287748570
Short name T181
Test name
Test status
Simulation time 397920543088 ps
CPU time 207.21 seconds
Started Jul 31 06:45:12 PM PDT 24
Finished Jul 31 06:48:39 PM PDT 24
Peak memory 201460 kb
Host smart-d57fba47-caf0-4cd7-8a33-c45020c4a857
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287748570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1287748570
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3284341393
Short name T768
Test name
Test status
Simulation time 114944114070 ps
CPU time 426.67 seconds
Started Jul 31 06:45:18 PM PDT 24
Finished Jul 31 06:52:25 PM PDT 24
Peak memory 201804 kb
Host smart-97716227-1ada-4288-9a1f-d96a5dac85a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284341393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3284341393
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3278610027
Short name T701
Test name
Test status
Simulation time 30030638976 ps
CPU time 57.96 seconds
Started Jul 31 06:45:17 PM PDT 24
Finished Jul 31 06:46:15 PM PDT 24
Peak memory 201356 kb
Host smart-aec3de24-847f-4426-8faa-eb0eb14b0394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278610027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3278610027
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1264288587
Short name T564
Test name
Test status
Simulation time 4513272615 ps
CPU time 10.91 seconds
Started Jul 31 06:45:17 PM PDT 24
Finished Jul 31 06:45:28 PM PDT 24
Peak memory 201312 kb
Host smart-56e7817e-5f7d-4330-8f65-29d9125ff01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264288587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1264288587
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1625393836
Short name T722
Test name
Test status
Simulation time 5776818374 ps
CPU time 13.31 seconds
Started Jul 31 06:45:06 PM PDT 24
Finished Jul 31 06:45:19 PM PDT 24
Peak memory 201376 kb
Host smart-0f2f36f8-8e97-4fed-99bc-c92244a2c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625393836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1625393836
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3544239489
Short name T662
Test name
Test status
Simulation time 323339660137 ps
CPU time 739.31 seconds
Started Jul 31 06:45:25 PM PDT 24
Finished Jul 31 06:57:44 PM PDT 24
Peak memory 201392 kb
Host smart-3ce3953e-4132-4485-9530-729198b88efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544239489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3544239489
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1238240883
Short name T43
Test name
Test status
Simulation time 17301369967 ps
CPU time 38.06 seconds
Started Jul 31 06:45:17 PM PDT 24
Finished Jul 31 06:45:55 PM PDT 24
Peak memory 201656 kb
Host smart-360b2232-16f3-4e5c-9ad6-c71a1d964cce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238240883 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1238240883
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3795132113
Short name T544
Test name
Test status
Simulation time 481748635 ps
CPU time 1 seconds
Started Jul 31 06:45:48 PM PDT 24
Finished Jul 31 06:45:49 PM PDT 24
Peak memory 201228 kb
Host smart-dca50e90-6aee-49f9-a787-265bf72164af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795132113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3795132113
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.4006479865
Short name T185
Test name
Test status
Simulation time 540326399334 ps
CPU time 277.25 seconds
Started Jul 31 06:45:34 PM PDT 24
Finished Jul 31 06:50:11 PM PDT 24
Peak memory 201420 kb
Host smart-44a24889-6745-4ea4-acd4-97726776f736
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006479865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.4006479865
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.684952590
Short name T708
Test name
Test status
Simulation time 168518231716 ps
CPU time 31.02 seconds
Started Jul 31 06:45:34 PM PDT 24
Finished Jul 31 06:46:05 PM PDT 24
Peak memory 201476 kb
Host smart-67192fb8-f17b-4154-9ecb-2ba24e901dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684952590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.684952590
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3885989816
Short name T522
Test name
Test status
Simulation time 498378148251 ps
CPU time 1137.3 seconds
Started Jul 31 06:45:28 PM PDT 24
Finished Jul 31 07:04:25 PM PDT 24
Peak memory 201472 kb
Host smart-bd27d62e-682d-4e62-95f8-307b1d493309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885989816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3885989816
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3264588485
Short name T491
Test name
Test status
Simulation time 166040403964 ps
CPU time 101.79 seconds
Started Jul 31 06:45:28 PM PDT 24
Finished Jul 31 06:47:10 PM PDT 24
Peak memory 201472 kb
Host smart-cc9de533-21cd-4a96-8d84-3ec746b41269
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264588485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3264588485
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2664472894
Short name T176
Test name
Test status
Simulation time 494573094955 ps
CPU time 292.03 seconds
Started Jul 31 06:45:34 PM PDT 24
Finished Jul 31 06:50:26 PM PDT 24
Peak memory 201460 kb
Host smart-aa82adc2-f188-487c-9b50-9bee621a64ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664472894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2664472894
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1964219354
Short name T384
Test name
Test status
Simulation time 485420324079 ps
CPU time 202.96 seconds
Started Jul 31 06:45:28 PM PDT 24
Finished Jul 31 06:48:51 PM PDT 24
Peak memory 201436 kb
Host smart-7bfc2256-6771-4016-8f54-6827494d7867
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964219354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1964219354
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3655487311
Short name T333
Test name
Test status
Simulation time 356505695537 ps
CPU time 127.71 seconds
Started Jul 31 06:45:30 PM PDT 24
Finished Jul 31 06:47:37 PM PDT 24
Peak memory 201404 kb
Host smart-0a2a15e2-b47b-4871-9824-f492df76c055
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655487311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3655487311
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1516051229
Short name T669
Test name
Test status
Simulation time 202685254794 ps
CPU time 121.28 seconds
Started Jul 31 06:45:29 PM PDT 24
Finished Jul 31 06:47:30 PM PDT 24
Peak memory 201464 kb
Host smart-2dea482a-744a-43b2-8aa3-b2cdee02b4b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516051229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1516051229
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.103039044
Short name T743
Test name
Test status
Simulation time 132262652359 ps
CPU time 462.18 seconds
Started Jul 31 06:45:40 PM PDT 24
Finished Jul 31 06:53:22 PM PDT 24
Peak memory 201788 kb
Host smart-43d4937c-f9e5-41e2-9444-07bf492d31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103039044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.103039044
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2691053122
Short name T425
Test name
Test status
Simulation time 34226750786 ps
CPU time 63.17 seconds
Started Jul 31 06:45:40 PM PDT 24
Finished Jul 31 06:46:44 PM PDT 24
Peak memory 201392 kb
Host smart-921ad212-8384-4e58-b478-fe7d159b9778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691053122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2691053122
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1671984513
Short name T184
Test name
Test status
Simulation time 5441318362 ps
CPU time 3.69 seconds
Started Jul 31 06:45:34 PM PDT 24
Finished Jul 31 06:45:38 PM PDT 24
Peak memory 201344 kb
Host smart-4a391f61-7fe7-4b2e-8c23-666a131f9aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671984513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1671984513
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1992594330
Short name T659
Test name
Test status
Simulation time 5964925933 ps
CPU time 14.69 seconds
Started Jul 31 06:45:28 PM PDT 24
Finished Jul 31 06:45:43 PM PDT 24
Peak memory 201364 kb
Host smart-76dd2992-c383-4fa6-a99d-de206bee1894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992594330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1992594330
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2015187829
Short name T103
Test name
Test status
Simulation time 190451797995 ps
CPU time 146.21 seconds
Started Jul 31 06:45:47 PM PDT 24
Finished Jul 31 06:48:14 PM PDT 24
Peak memory 210144 kb
Host smart-3f0fff30-2bca-46b6-a3a9-f970d0d15777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015187829 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2015187829
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.631475552
Short name T443
Test name
Test status
Simulation time 423413727 ps
CPU time 1.14 seconds
Started Jul 31 06:46:06 PM PDT 24
Finished Jul 31 06:46:07 PM PDT 24
Peak memory 201256 kb
Host smart-e0ded828-9f4e-42b6-b54c-f23e4c41033a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631475552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.631475552
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2912973037
Short name T46
Test name
Test status
Simulation time 177058062168 ps
CPU time 100.26 seconds
Started Jul 31 06:45:50 PM PDT 24
Finished Jul 31 06:47:31 PM PDT 24
Peak memory 201444 kb
Host smart-31c6db9a-05ac-4427-b468-7aece13684fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912973037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2912973037
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1308131973
Short name T335
Test name
Test status
Simulation time 504192152269 ps
CPU time 1153.33 seconds
Started Jul 31 06:45:50 PM PDT 24
Finished Jul 31 07:05:03 PM PDT 24
Peak memory 201464 kb
Host smart-d1c5c939-c79e-4217-8595-40591b3df401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308131973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1308131973
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3423377634
Short name T789
Test name
Test status
Simulation time 159319142982 ps
CPU time 26.52 seconds
Started Jul 31 06:45:46 PM PDT 24
Finished Jul 31 06:46:13 PM PDT 24
Peak memory 201436 kb
Host smart-35c6b5c9-170a-4e91-8792-17a90d6ea079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423377634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3423377634
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2818007883
Short name T548
Test name
Test status
Simulation time 493298365547 ps
CPU time 283.65 seconds
Started Jul 31 06:45:45 PM PDT 24
Finished Jul 31 06:50:29 PM PDT 24
Peak memory 201420 kb
Host smart-7e841a74-9dd6-4f8c-aca5-0265669f87db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818007883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2818007883
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2151878593
Short name T414
Test name
Test status
Simulation time 171990231913 ps
CPU time 198.74 seconds
Started Jul 31 06:45:47 PM PDT 24
Finished Jul 31 06:49:06 PM PDT 24
Peak memory 201484 kb
Host smart-c8aaacaf-1862-4c13-ac96-dcd755d39b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151878593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2151878593
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.463239271
Short name T537
Test name
Test status
Simulation time 326343269004 ps
CPU time 79.85 seconds
Started Jul 31 06:45:47 PM PDT 24
Finished Jul 31 06:47:06 PM PDT 24
Peak memory 201412 kb
Host smart-dddba292-25c2-4569-bb12-60600cff7e4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=463239271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.463239271
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1858482413
Short name T315
Test name
Test status
Simulation time 187282851084 ps
CPU time 201.85 seconds
Started Jul 31 06:45:51 PM PDT 24
Finished Jul 31 06:49:13 PM PDT 24
Peak memory 201436 kb
Host smart-5d7437da-4a78-46a0-9b74-3eea6ab9e6e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858482413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1858482413
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.4090893929
Short name T379
Test name
Test status
Simulation time 391538613742 ps
CPU time 231.8 seconds
Started Jul 31 06:45:49 PM PDT 24
Finished Jul 31 06:49:41 PM PDT 24
Peak memory 201432 kb
Host smart-b087c1c0-480c-4690-b9dc-266987c37210
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090893929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.4090893929
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3234095200
Short name T63
Test name
Test status
Simulation time 100639825497 ps
CPU time 264.15 seconds
Started Jul 31 06:46:07 PM PDT 24
Finished Jul 31 06:50:31 PM PDT 24
Peak memory 201840 kb
Host smart-0c82bb53-6705-494b-8dbd-7949e9541b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234095200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3234095200
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3051148759
Short name T399
Test name
Test status
Simulation time 39468160698 ps
CPU time 44.58 seconds
Started Jul 31 06:45:54 PM PDT 24
Finished Jul 31 06:46:39 PM PDT 24
Peak memory 201316 kb
Host smart-68bf87a2-5f4f-4e1b-bc0e-c24210a05b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051148759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3051148759
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1669475006
Short name T474
Test name
Test status
Simulation time 5273478248 ps
CPU time 3.93 seconds
Started Jul 31 06:45:57 PM PDT 24
Finished Jul 31 06:46:01 PM PDT 24
Peak memory 201332 kb
Host smart-826cb50d-bd3a-40e2-bc80-9a2edbe41189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669475006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1669475006
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2224719198
Short name T398
Test name
Test status
Simulation time 5664380377 ps
CPU time 13.44 seconds
Started Jul 31 06:45:46 PM PDT 24
Finished Jul 31 06:45:59 PM PDT 24
Peak memory 201364 kb
Host smart-1072ec37-1636-43b5-bdcb-2aa24a9bac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224719198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2224719198
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3209544550
Short name T658
Test name
Test status
Simulation time 39456465769 ps
CPU time 89.05 seconds
Started Jul 31 06:46:06 PM PDT 24
Finished Jul 31 06:47:35 PM PDT 24
Peak memory 201452 kb
Host smart-31988977-77c3-4c29-b7a0-27fa98a06ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209544550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3209544550
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.513084250
Short name T558
Test name
Test status
Simulation time 162292223275 ps
CPU time 91.36 seconds
Started Jul 31 06:46:07 PM PDT 24
Finished Jul 31 06:47:39 PM PDT 24
Peak memory 217836 kb
Host smart-04a6461c-48b2-4961-8ce5-8839ec5aa423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513084250 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.513084250
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2213122174
Short name T358
Test name
Test status
Simulation time 506835935 ps
CPU time 1.66 seconds
Started Jul 31 06:46:33 PM PDT 24
Finished Jul 31 06:46:35 PM PDT 24
Peak memory 201228 kb
Host smart-964d1a91-b2e8-4385-a6df-f8310326b3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213122174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2213122174
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1694690916
Short name T625
Test name
Test status
Simulation time 533752018271 ps
CPU time 1252.85 seconds
Started Jul 31 06:46:28 PM PDT 24
Finished Jul 31 07:07:21 PM PDT 24
Peak memory 201488 kb
Host smart-cc1a4d58-d392-4985-9dbc-2e8e8f6eed3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694690916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1694690916
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2950929588
Short name T50
Test name
Test status
Simulation time 167590125207 ps
CPU time 404.63 seconds
Started Jul 31 06:46:17 PM PDT 24
Finished Jul 31 06:53:02 PM PDT 24
Peak memory 201532 kb
Host smart-2a7f7dc2-2371-40fa-bdec-3721d5577b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950929588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2950929588
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2001308826
Short name T417
Test name
Test status
Simulation time 327360372249 ps
CPU time 794.21 seconds
Started Jul 31 06:46:21 PM PDT 24
Finished Jul 31 06:59:36 PM PDT 24
Peak memory 201504 kb
Host smart-66ad71b1-5990-4ba5-86af-957b4776832e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001308826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2001308826
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3544307160
Short name T166
Test name
Test status
Simulation time 488546661801 ps
CPU time 263.98 seconds
Started Jul 31 06:46:16 PM PDT 24
Finished Jul 31 06:50:40 PM PDT 24
Peak memory 201448 kb
Host smart-6bbae9ce-7360-47bf-83cf-e059149106d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544307160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3544307160
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2226769685
Short name T633
Test name
Test status
Simulation time 159808912982 ps
CPU time 345.81 seconds
Started Jul 31 06:46:17 PM PDT 24
Finished Jul 31 06:52:03 PM PDT 24
Peak memory 201452 kb
Host smart-ff4cf4bf-847a-4a8c-bf32-3cce4fae5d36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226769685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2226769685
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2450095133
Short name T113
Test name
Test status
Simulation time 407527029871 ps
CPU time 174.7 seconds
Started Jul 31 06:46:22 PM PDT 24
Finished Jul 31 06:49:17 PM PDT 24
Peak memory 201376 kb
Host smart-122713e8-1050-48d1-9814-4a657b3385cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450095133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2450095133
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1377352572
Short name T386
Test name
Test status
Simulation time 115175735987 ps
CPU time 510.87 seconds
Started Jul 31 06:46:32 PM PDT 24
Finished Jul 31 06:55:03 PM PDT 24
Peak memory 201816 kb
Host smart-4ea2d678-462d-4917-a491-45bc60fd3eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377352572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1377352572
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.609379476
Short name T647
Test name
Test status
Simulation time 30121998453 ps
CPU time 16.19 seconds
Started Jul 31 06:46:27 PM PDT 24
Finished Jul 31 06:46:44 PM PDT 24
Peak memory 201388 kb
Host smart-73ccd222-4fa2-4052-b277-ccb3a158e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609379476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.609379476
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1340295727
Short name T745
Test name
Test status
Simulation time 3160083285 ps
CPU time 2.52 seconds
Started Jul 31 06:46:27 PM PDT 24
Finished Jul 31 06:46:30 PM PDT 24
Peak memory 201328 kb
Host smart-2fd0f344-87d3-4592-8cb2-c9dab20f0fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340295727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1340295727
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3714850590
Short name T545
Test name
Test status
Simulation time 5757508002 ps
CPU time 4.12 seconds
Started Jul 31 06:46:09 PM PDT 24
Finished Jul 31 06:46:13 PM PDT 24
Peak memory 201332 kb
Host smart-fe28bd5e-32f4-4ead-9090-1fc5e991a8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714850590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3714850590
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.308846668
Short name T370
Test name
Test status
Simulation time 396916577 ps
CPU time 1.52 seconds
Started Jul 31 06:46:45 PM PDT 24
Finished Jul 31 06:46:46 PM PDT 24
Peak memory 201260 kb
Host smart-27d1e59c-ee74-4e1b-9ea8-691fb6a204ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308846668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.308846668
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.84962739
Short name T70
Test name
Test status
Simulation time 492773639952 ps
CPU time 221.81 seconds
Started Jul 31 06:46:43 PM PDT 24
Finished Jul 31 06:50:25 PM PDT 24
Peak memory 201428 kb
Host smart-7ff4a7ac-7c96-4bc2-832e-ff58a1ecb1d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84962739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gatin
g.84962739
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1996399108
Short name T755
Test name
Test status
Simulation time 370962065715 ps
CPU time 422.45 seconds
Started Jul 31 06:46:49 PM PDT 24
Finished Jul 31 06:53:51 PM PDT 24
Peak memory 201512 kb
Host smart-0c1cf331-6ab6-4dcd-bb79-ed7a32f8c89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996399108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1996399108
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3513224727
Short name T726
Test name
Test status
Simulation time 490090395926 ps
CPU time 1084.62 seconds
Started Jul 31 06:46:38 PM PDT 24
Finished Jul 31 07:04:43 PM PDT 24
Peak memory 201456 kb
Host smart-b1c62068-16fb-4f7c-8250-7079d1ea6bc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513224727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3513224727
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2127217874
Short name T160
Test name
Test status
Simulation time 334403696008 ps
CPU time 185.51 seconds
Started Jul 31 06:46:32 PM PDT 24
Finished Jul 31 06:49:37 PM PDT 24
Peak memory 201416 kb
Host smart-f2341468-d545-48df-aa8e-9f286cd259ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127217874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2127217874
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3843138999
Short name T506
Test name
Test status
Simulation time 488821548270 ps
CPU time 317.01 seconds
Started Jul 31 06:46:38 PM PDT 24
Finished Jul 31 06:51:55 PM PDT 24
Peak memory 201452 kb
Host smart-d0a7976d-4caf-4d83-a4b9-4d8b904391ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843138999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3843138999
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3740617431
Short name T223
Test name
Test status
Simulation time 170269089663 ps
CPU time 191.52 seconds
Started Jul 31 06:46:39 PM PDT 24
Finished Jul 31 06:49:51 PM PDT 24
Peak memory 201428 kb
Host smart-5ff2a926-ac3a-4a2c-9b77-f3d95e238e93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740617431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3740617431
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.980817726
Short name T601
Test name
Test status
Simulation time 389214050983 ps
CPU time 878.64 seconds
Started Jul 31 06:46:39 PM PDT 24
Finished Jul 31 07:01:18 PM PDT 24
Peak memory 201476 kb
Host smart-cf2ab128-a6dd-4f82-a9f9-97a4b1e80fbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980817726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.980817726
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1263934748
Short name T618
Test name
Test status
Simulation time 65840739004 ps
CPU time 346.11 seconds
Started Jul 31 06:46:43 PM PDT 24
Finished Jul 31 06:52:30 PM PDT 24
Peak memory 201824 kb
Host smart-fbe363e3-164c-40b6-85d9-d7006a4869c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263934748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1263934748
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.124698735
Short name T724
Test name
Test status
Simulation time 21622241597 ps
CPU time 11.96 seconds
Started Jul 31 06:46:44 PM PDT 24
Finished Jul 31 06:46:56 PM PDT 24
Peak memory 201360 kb
Host smart-824be994-2003-4922-b4de-5813fd6f1ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124698735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.124698735
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.465930951
Short name T642
Test name
Test status
Simulation time 3530650749 ps
CPU time 2.65 seconds
Started Jul 31 06:46:44 PM PDT 24
Finished Jul 31 06:46:46 PM PDT 24
Peak memory 201396 kb
Host smart-92f20698-fbe6-444a-ae89-6e23c9a5c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465930951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.465930951
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4164342130
Short name T516
Test name
Test status
Simulation time 5966923009 ps
CPU time 2.35 seconds
Started Jul 31 06:46:31 PM PDT 24
Finished Jul 31 06:46:34 PM PDT 24
Peak memory 201352 kb
Host smart-21578dfb-8bdc-4afb-89db-08e2235307be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164342130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4164342130
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.539459465
Short name T291
Test name
Test status
Simulation time 395880304854 ps
CPU time 226.47 seconds
Started Jul 31 06:46:44 PM PDT 24
Finished Jul 31 06:50:30 PM PDT 24
Peak memory 201460 kb
Host smart-41bccf78-74d7-4e25-a6c1-9f7d0587d052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539459465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
539459465
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.366308749
Short name T22
Test name
Test status
Simulation time 32234437243 ps
CPU time 69.9 seconds
Started Jul 31 06:46:41 PM PDT 24
Finished Jul 31 06:47:51 PM PDT 24
Peak memory 201612 kb
Host smart-77e66674-fcb8-4ea5-b27e-fdc935dc3ce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366308749 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.366308749
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2727290400
Short name T556
Test name
Test status
Simulation time 476754891 ps
CPU time 1.68 seconds
Started Jul 31 06:47:00 PM PDT 24
Finished Jul 31 06:47:02 PM PDT 24
Peak memory 201204 kb
Host smart-3c5a8e7e-8148-48dd-9cf3-f48067409536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727290400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2727290400
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.404694810
Short name T590
Test name
Test status
Simulation time 328397920102 ps
CPU time 198.73 seconds
Started Jul 31 06:46:48 PM PDT 24
Finished Jul 31 06:50:07 PM PDT 24
Peak memory 201452 kb
Host smart-ea64e31e-fa88-404a-aff2-ac874fd55684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404694810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.404694810
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3112174716
Short name T555
Test name
Test status
Simulation time 486915931085 ps
CPU time 1024.5 seconds
Started Jul 31 06:46:49 PM PDT 24
Finished Jul 31 07:03:54 PM PDT 24
Peak memory 201452 kb
Host smart-93c77a3b-e0c8-46e3-89c5-a798301da4b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112174716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3112174716
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3815178190
Short name T754
Test name
Test status
Simulation time 501456851529 ps
CPU time 559.51 seconds
Started Jul 31 06:46:50 PM PDT 24
Finished Jul 31 06:56:10 PM PDT 24
Peak memory 201420 kb
Host smart-0cc0fee8-5f0c-42af-a87b-aae4a954ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815178190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3815178190
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2514777085
Short name T569
Test name
Test status
Simulation time 164867694972 ps
CPU time 42.17 seconds
Started Jul 31 06:46:49 PM PDT 24
Finished Jul 31 06:47:31 PM PDT 24
Peak memory 201372 kb
Host smart-38c169be-1b5a-47c3-ae0f-c68efa1c954a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514777085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2514777085
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1813920801
Short name T271
Test name
Test status
Simulation time 175998155700 ps
CPU time 184.45 seconds
Started Jul 31 06:46:48 PM PDT 24
Finished Jul 31 06:49:53 PM PDT 24
Peak memory 201452 kb
Host smart-b32bc2bc-50f7-4a0b-9cd8-080abaa67d1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813920801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1813920801
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2269622345
Short name T532
Test name
Test status
Simulation time 210396137511 ps
CPU time 509.19 seconds
Started Jul 31 06:46:56 PM PDT 24
Finished Jul 31 06:55:25 PM PDT 24
Peak memory 201444 kb
Host smart-add42ac4-5c15-4b9a-9c5d-c0c188105d50
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269622345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2269622345
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2998691478
Short name T220
Test name
Test status
Simulation time 86673782388 ps
CPU time 322.54 seconds
Started Jul 31 06:46:54 PM PDT 24
Finished Jul 31 06:52:17 PM PDT 24
Peak memory 201868 kb
Host smart-1a470fdb-2624-48ff-8329-9c675f793271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998691478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2998691478
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1360282394
Short name T652
Test name
Test status
Simulation time 31854163954 ps
CPU time 36.85 seconds
Started Jul 31 06:46:54 PM PDT 24
Finished Jul 31 06:47:31 PM PDT 24
Peak memory 201352 kb
Host smart-372aa125-5059-4df0-8e0b-85815ab913ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360282394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1360282394
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4086776693
Short name T533
Test name
Test status
Simulation time 3953027213 ps
CPU time 10.11 seconds
Started Jul 31 06:46:58 PM PDT 24
Finished Jul 31 06:47:08 PM PDT 24
Peak memory 201344 kb
Host smart-67e76c1e-00b7-4467-8d4d-34df0859e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086776693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4086776693
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1855856968
Short name T645
Test name
Test status
Simulation time 5721412544 ps
CPU time 4.25 seconds
Started Jul 31 06:46:53 PM PDT 24
Finished Jul 31 06:46:57 PM PDT 24
Peak memory 201380 kb
Host smart-9f455422-e6a6-42a5-a8f0-3cd848d09ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855856968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1855856968
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1721673110
Short name T762
Test name
Test status
Simulation time 343351287459 ps
CPU time 210.68 seconds
Started Jul 31 06:47:00 PM PDT 24
Finished Jul 31 06:50:31 PM PDT 24
Peak memory 201520 kb
Host smart-5223576a-7386-4425-9060-c7e9b7aaf4d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721673110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1721673110
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2568227359
Short name T17
Test name
Test status
Simulation time 102524806280 ps
CPU time 109.16 seconds
Started Jul 31 06:46:59 PM PDT 24
Finished Jul 31 06:48:48 PM PDT 24
Peak memory 209824 kb
Host smart-0d8e9285-ecf7-4fd1-bef1-dc6591a0af04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568227359 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2568227359
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.459755226
Short name T100
Test name
Test status
Simulation time 418847216 ps
CPU time 0.85 seconds
Started Jul 31 06:47:16 PM PDT 24
Finished Jul 31 06:47:17 PM PDT 24
Peak memory 201224 kb
Host smart-a9295bfa-a8b9-452e-a3d2-cd4568acfdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459755226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.459755226
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3504463213
Short name T276
Test name
Test status
Simulation time 331738226337 ps
CPU time 174.86 seconds
Started Jul 31 06:47:05 PM PDT 24
Finished Jul 31 06:50:00 PM PDT 24
Peak memory 201464 kb
Host smart-94517027-5ccb-4622-a02f-4332e6951191
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504463213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3504463213
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.229233195
Short name T253
Test name
Test status
Simulation time 512999652710 ps
CPU time 1124.52 seconds
Started Jul 31 06:47:10 PM PDT 24
Finished Jul 31 07:05:55 PM PDT 24
Peak memory 201452 kb
Host smart-79c5abbf-d93a-4511-83da-3d60c0d44460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229233195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.229233195
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.669862077
Short name T339
Test name
Test status
Simulation time 495515519264 ps
CPU time 299.56 seconds
Started Jul 31 06:46:59 PM PDT 24
Finished Jul 31 06:51:59 PM PDT 24
Peak memory 201460 kb
Host smart-e55159c8-d8e1-46b7-aaea-3b0264dc54f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669862077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.669862077
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2317110113
Short name T675
Test name
Test status
Simulation time 168874981578 ps
CPU time 403.99 seconds
Started Jul 31 06:47:09 PM PDT 24
Finished Jul 31 06:53:53 PM PDT 24
Peak memory 201504 kb
Host smart-6e791209-d095-41bb-bdac-4d775f710698
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317110113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2317110113
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1537026330
Short name T581
Test name
Test status
Simulation time 163085417930 ps
CPU time 97.19 seconds
Started Jul 31 06:46:59 PM PDT 24
Finished Jul 31 06:48:36 PM PDT 24
Peak memory 201416 kb
Host smart-81855e91-a2c3-43b1-8ec9-ee55521d7f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537026330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1537026330
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.873202059
Short name T42
Test name
Test status
Simulation time 330024474120 ps
CPU time 770.41 seconds
Started Jul 31 06:46:59 PM PDT 24
Finished Jul 31 06:59:50 PM PDT 24
Peak memory 201456 kb
Host smart-ed501288-77aa-49c8-b938-fcfaa06d8fea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=873202059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.873202059
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.184964707
Short name T696
Test name
Test status
Simulation time 356134663678 ps
CPU time 786.55 seconds
Started Jul 31 06:47:07 PM PDT 24
Finished Jul 31 07:00:13 PM PDT 24
Peak memory 201452 kb
Host smart-bdd6dbda-033e-47bb-ae0e-2b0cb9c80475
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184964707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.184964707
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2481910757
Short name T517
Test name
Test status
Simulation time 195695883130 ps
CPU time 447.47 seconds
Started Jul 31 06:47:09 PM PDT 24
Finished Jul 31 06:54:36 PM PDT 24
Peak memory 201452 kb
Host smart-d432a8fc-014e-4c82-8078-2c2aa7df1c93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481910757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2481910757
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.410856956
Short name T467
Test name
Test status
Simulation time 41877907359 ps
CPU time 47.49 seconds
Started Jul 31 06:47:17 PM PDT 24
Finished Jul 31 06:48:05 PM PDT 24
Peak memory 201328 kb
Host smart-4d92b80a-c2b4-466a-a802-39255655b285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410856956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.410856956
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3132021524
Short name T578
Test name
Test status
Simulation time 4275841459 ps
CPU time 11.26 seconds
Started Jul 31 06:47:14 PM PDT 24
Finished Jul 31 06:47:26 PM PDT 24
Peak memory 201356 kb
Host smart-ee4c4df5-47b9-4d9a-b4e6-e9e2c61e4f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132021524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3132021524
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1873243028
Short name T372
Test name
Test status
Simulation time 5641368645 ps
CPU time 12.33 seconds
Started Jul 31 06:46:58 PM PDT 24
Finished Jul 31 06:47:11 PM PDT 24
Peak memory 201404 kb
Host smart-b7653c2e-4309-40a3-ae42-71a4ab74cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873243028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1873243028
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2364646454
Short name T527
Test name
Test status
Simulation time 188427105054 ps
CPU time 221.24 seconds
Started Jul 31 06:47:16 PM PDT 24
Finished Jul 31 06:50:57 PM PDT 24
Peak memory 201444 kb
Host smart-3b392b04-3ec5-40c1-84bc-90f4e1f36ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364646454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2364646454
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3066757970
Short name T741
Test name
Test status
Simulation time 216087446484 ps
CPU time 140.66 seconds
Started Jul 31 06:47:15 PM PDT 24
Finished Jul 31 06:49:36 PM PDT 24
Peak memory 210144 kb
Host smart-165a4c97-8c2f-4ab7-b9d1-69108f523808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066757970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3066757970
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3386735161
Short name T471
Test name
Test status
Simulation time 391194278 ps
CPU time 1.54 seconds
Started Jul 31 06:38:14 PM PDT 24
Finished Jul 31 06:38:15 PM PDT 24
Peak memory 201232 kb
Host smart-bfd62624-9eb2-43ca-bbcd-0abb908374d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386735161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3386735161
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.640776210
Short name T97
Test name
Test status
Simulation time 174446886607 ps
CPU time 376.68 seconds
Started Jul 31 06:38:10 PM PDT 24
Finished Jul 31 06:44:27 PM PDT 24
Peak memory 201516 kb
Host smart-82187732-2954-4246-a46e-94b678008a01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640776210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.640776210
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.856164647
Short name T670
Test name
Test status
Simulation time 486115633300 ps
CPU time 1204.81 seconds
Started Jul 31 06:38:07 PM PDT 24
Finished Jul 31 06:58:12 PM PDT 24
Peak memory 201484 kb
Host smart-7dbc5ea1-45fe-4fbf-935e-6af6aa32a4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856164647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.856164647
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2251130823
Short name T300
Test name
Test status
Simulation time 496622469918 ps
CPU time 198.17 seconds
Started Jul 31 06:38:07 PM PDT 24
Finished Jul 31 06:41:26 PM PDT 24
Peak memory 201468 kb
Host smart-008bb2ee-28cd-4457-b930-c0ff569513b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251130823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2251130823
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3238958216
Short name T650
Test name
Test status
Simulation time 328680704827 ps
CPU time 792.12 seconds
Started Jul 31 06:38:06 PM PDT 24
Finished Jul 31 06:51:18 PM PDT 24
Peak memory 201464 kb
Host smart-e7e1d33c-b232-42ab-8b26-b8d111656d73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238958216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3238958216
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.208637848
Short name T530
Test name
Test status
Simulation time 327288276371 ps
CPU time 783.93 seconds
Started Jul 31 06:38:00 PM PDT 24
Finished Jul 31 06:51:04 PM PDT 24
Peak memory 201484 kb
Host smart-b8350a57-41da-48c5-83ac-000d36deecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208637848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.208637848
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.454948888
Short name T612
Test name
Test status
Simulation time 160288051856 ps
CPU time 374.51 seconds
Started Jul 31 06:38:05 PM PDT 24
Finished Jul 31 06:44:19 PM PDT 24
Peak memory 201480 kb
Host smart-53687521-09bd-45bd-ad56-995a897a2a31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=454948888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.454948888
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1712347047
Short name T501
Test name
Test status
Simulation time 134995557963 ps
CPU time 693.8 seconds
Started Jul 31 06:38:12 PM PDT 24
Finished Jul 31 06:49:46 PM PDT 24
Peak memory 201864 kb
Host smart-8e76e296-b5a7-4c9d-a8c5-848477efac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712347047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1712347047
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.638718979
Short name T774
Test name
Test status
Simulation time 43454267155 ps
CPU time 96.03 seconds
Started Jul 31 06:38:11 PM PDT 24
Finished Jul 31 06:39:47 PM PDT 24
Peak memory 201296 kb
Host smart-0120ac6f-2337-40ef-9e99-cdc2b5556191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638718979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.638718979
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2798033726
Short name T143
Test name
Test status
Simulation time 5021413530 ps
CPU time 6.75 seconds
Started Jul 31 06:38:15 PM PDT 24
Finished Jul 31 06:38:21 PM PDT 24
Peak memory 201332 kb
Host smart-cfb4534c-e804-4a4c-95ec-10cca3ca87bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798033726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2798033726
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.517564276
Short name T90
Test name
Test status
Simulation time 4278074772 ps
CPU time 4.62 seconds
Started Jul 31 06:38:15 PM PDT 24
Finished Jul 31 06:38:20 PM PDT 24
Peak memory 217120 kb
Host smart-08912140-aae6-4a94-a27e-8551a7672e6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517564276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.517564276
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.4211970247
Short name T403
Test name
Test status
Simulation time 5585191672 ps
CPU time 3.49 seconds
Started Jul 31 06:38:02 PM PDT 24
Finished Jul 31 06:38:05 PM PDT 24
Peak memory 201392 kb
Host smart-e96aaebc-678f-443b-a47b-2560a55ef70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211970247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4211970247
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2276540823
Short name T38
Test name
Test status
Simulation time 166494135609 ps
CPU time 99.87 seconds
Started Jul 31 06:38:12 PM PDT 24
Finished Jul 31 06:39:52 PM PDT 24
Peak memory 201512 kb
Host smart-f5565b29-b011-4b3a-a4a6-8effa5c06595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276540823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2276540823
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1857036239
Short name T649
Test name
Test status
Simulation time 17665468385 ps
CPU time 41.05 seconds
Started Jul 31 06:38:14 PM PDT 24
Finished Jul 31 06:38:55 PM PDT 24
Peak memory 209816 kb
Host smart-cd36773c-e05d-4d75-b327-d7f00d5a8b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857036239 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1857036239
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3365238493
Short name T605
Test name
Test status
Simulation time 306684914 ps
CPU time 0.98 seconds
Started Jul 31 06:47:38 PM PDT 24
Finished Jul 31 06:47:39 PM PDT 24
Peak memory 201240 kb
Host smart-1d3df9b7-17b7-413e-8d39-fd1b9c1a89fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365238493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3365238493
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3084619916
Short name T279
Test name
Test status
Simulation time 380767711939 ps
CPU time 406.99 seconds
Started Jul 31 06:47:27 PM PDT 24
Finished Jul 31 06:54:14 PM PDT 24
Peak memory 201452 kb
Host smart-bf3fdec4-bc51-4703-822a-972e0329ffa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084619916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3084619916
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4179582305
Short name T158
Test name
Test status
Simulation time 169764545346 ps
CPU time 104.5 seconds
Started Jul 31 06:47:21 PM PDT 24
Finished Jul 31 06:49:06 PM PDT 24
Peak memory 201464 kb
Host smart-28bbe491-b2fa-43df-b844-253b9ac3f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179582305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4179582305
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1401918751
Short name T31
Test name
Test status
Simulation time 329598718347 ps
CPU time 729.62 seconds
Started Jul 31 06:47:22 PM PDT 24
Finished Jul 31 06:59:32 PM PDT 24
Peak memory 201444 kb
Host smart-6e63babc-9efb-45b6-83b7-e3b469aef4db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401918751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1401918751
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.208725743
Short name T6
Test name
Test status
Simulation time 165938841671 ps
CPU time 383.6 seconds
Started Jul 31 06:47:24 PM PDT 24
Finished Jul 31 06:53:47 PM PDT 24
Peak memory 201452 kb
Host smart-569f873b-e529-4b8d-9211-7e1bf6f61b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208725743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.208725743
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3497503303
Short name T402
Test name
Test status
Simulation time 161884728022 ps
CPU time 96.02 seconds
Started Jul 31 06:47:20 PM PDT 24
Finished Jul 31 06:48:56 PM PDT 24
Peak memory 201376 kb
Host smart-c20ce647-d2ac-4d40-a4b6-d83fa96d79ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497503303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3497503303
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.790277511
Short name T787
Test name
Test status
Simulation time 530563385738 ps
CPU time 625.86 seconds
Started Jul 31 06:47:22 PM PDT 24
Finished Jul 31 06:57:48 PM PDT 24
Peak memory 201476 kb
Host smart-a40f5e99-fe02-4ebc-b372-08480ab50bf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790277511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.790277511
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2257740519
Short name T644
Test name
Test status
Simulation time 585090754769 ps
CPU time 1272.11 seconds
Started Jul 31 06:47:29 PM PDT 24
Finished Jul 31 07:08:41 PM PDT 24
Peak memory 201428 kb
Host smart-e8c2bf0b-d651-4649-9af8-f01e7d306284
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257740519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2257740519
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3825882361
Short name T518
Test name
Test status
Simulation time 70023752696 ps
CPU time 361.62 seconds
Started Jul 31 06:47:32 PM PDT 24
Finished Jul 31 06:53:34 PM PDT 24
Peak memory 201840 kb
Host smart-9a53696f-8fbe-436c-9b87-fd54bef11eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825882361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3825882361
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3362785362
Short name T655
Test name
Test status
Simulation time 37532488985 ps
CPU time 8.92 seconds
Started Jul 31 06:47:34 PM PDT 24
Finished Jul 31 06:47:43 PM PDT 24
Peak memory 201380 kb
Host smart-bfeb7b19-b678-4189-a8fa-3373281f4db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362785362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3362785362
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2791896423
Short name T757
Test name
Test status
Simulation time 4713657063 ps
CPU time 5.32 seconds
Started Jul 31 06:47:28 PM PDT 24
Finished Jul 31 06:47:33 PM PDT 24
Peak memory 201280 kb
Host smart-70d5be5e-da9c-4097-bddf-4e248e8439d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791896423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2791896423
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1338202968
Short name T432
Test name
Test status
Simulation time 5974787171 ps
CPU time 4 seconds
Started Jul 31 06:47:21 PM PDT 24
Finished Jul 31 06:47:25 PM PDT 24
Peak memory 201388 kb
Host smart-fbe6af39-ad46-439b-984c-e7820ae04ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338202968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1338202968
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1215470032
Short name T265
Test name
Test status
Simulation time 99938488808 ps
CPU time 50.81 seconds
Started Jul 31 06:47:34 PM PDT 24
Finished Jul 31 06:48:25 PM PDT 24
Peak memory 210156 kb
Host smart-9d249c4a-5775-49c7-8245-ace66001bc8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215470032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1215470032
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.881867656
Short name T673
Test name
Test status
Simulation time 420937394 ps
CPU time 1.52 seconds
Started Jul 31 06:47:59 PM PDT 24
Finished Jul 31 06:48:01 PM PDT 24
Peak memory 201228 kb
Host smart-348186c5-5b28-471a-837c-dcdf91b19cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881867656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.881867656
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2022519451
Short name T337
Test name
Test status
Simulation time 508436994374 ps
CPU time 1212.81 seconds
Started Jul 31 06:47:54 PM PDT 24
Finished Jul 31 07:08:07 PM PDT 24
Peak memory 201556 kb
Host smart-3149580d-0251-48ad-8413-c9d7d40d25f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022519451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2022519451
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3848688537
Short name T705
Test name
Test status
Simulation time 331856763595 ps
CPU time 172.48 seconds
Started Jul 31 06:47:45 PM PDT 24
Finished Jul 31 06:50:37 PM PDT 24
Peak memory 201424 kb
Host smart-f5676f12-efd1-482e-8713-3057b5f57d55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848688537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3848688537
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1072025367
Short name T340
Test name
Test status
Simulation time 170355529852 ps
CPU time 391 seconds
Started Jul 31 06:47:43 PM PDT 24
Finished Jul 31 06:54:14 PM PDT 24
Peak memory 201460 kb
Host smart-c59e29df-857d-4371-a847-652f3f15aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072025367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1072025367
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3397004972
Short name T182
Test name
Test status
Simulation time 486422282529 ps
CPU time 293.6 seconds
Started Jul 31 06:47:46 PM PDT 24
Finished Jul 31 06:52:40 PM PDT 24
Peak memory 201448 kb
Host smart-d46fdaa3-3b58-46e9-832f-b9cd66ff8cd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397004972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3397004972
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3656073555
Short name T224
Test name
Test status
Simulation time 623900052701 ps
CPU time 1164.53 seconds
Started Jul 31 06:47:49 PM PDT 24
Finished Jul 31 07:07:14 PM PDT 24
Peak memory 201508 kb
Host smart-1547db4d-e558-40b5-9655-f0a215944979
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656073555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3656073555
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.146254226
Short name T47
Test name
Test status
Simulation time 399060606724 ps
CPU time 896.3 seconds
Started Jul 31 06:47:50 PM PDT 24
Finished Jul 31 07:02:46 PM PDT 24
Peak memory 201460 kb
Host smart-07fe4166-c3aa-433b-a782-c10c5223eaea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146254226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.146254226
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2921166824
Short name T64
Test name
Test status
Simulation time 107604391427 ps
CPU time 373.1 seconds
Started Jul 31 06:47:54 PM PDT 24
Finished Jul 31 06:54:07 PM PDT 24
Peak memory 201840 kb
Host smart-69b7589d-ae98-4ecd-88c6-9d85535cf054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921166824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2921166824
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.646036316
Short name T761
Test name
Test status
Simulation time 34326459268 ps
CPU time 41.62 seconds
Started Jul 31 06:47:56 PM PDT 24
Finished Jul 31 06:48:37 PM PDT 24
Peak memory 201376 kb
Host smart-d0c50f50-116f-4cb0-8581-052f33acfacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646036316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.646036316
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1171727803
Short name T514
Test name
Test status
Simulation time 4563503542 ps
CPU time 2.69 seconds
Started Jul 31 06:47:55 PM PDT 24
Finished Jul 31 06:47:57 PM PDT 24
Peak memory 201360 kb
Host smart-360dcfec-1d1c-46de-8c5e-698a80e34805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171727803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1171727803
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2393633191
Short name T591
Test name
Test status
Simulation time 6012973847 ps
CPU time 14.14 seconds
Started Jul 31 06:47:37 PM PDT 24
Finished Jul 31 06:47:52 PM PDT 24
Peak memory 201352 kb
Host smart-ab234410-dfe4-4da3-98dc-b52a77096bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393633191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2393633191
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.903808331
Short name T288
Test name
Test status
Simulation time 171172373781 ps
CPU time 108.8 seconds
Started Jul 31 06:48:00 PM PDT 24
Finished Jul 31 06:49:48 PM PDT 24
Peak memory 201436 kb
Host smart-a714f241-7a7a-4bad-9c2c-097786cef7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903808331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
903808331
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.653608467
Short name T19
Test name
Test status
Simulation time 259412425949 ps
CPU time 409.75 seconds
Started Jul 31 06:48:01 PM PDT 24
Finished Jul 31 06:54:51 PM PDT 24
Peak memory 210244 kb
Host smart-ddd28e31-1432-4305-a4a7-3fbcec1c75d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653608467 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.653608467
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.899965638
Short name T481
Test name
Test status
Simulation time 475295143 ps
CPU time 0.9 seconds
Started Jul 31 06:48:11 PM PDT 24
Finished Jul 31 06:48:12 PM PDT 24
Peak memory 201184 kb
Host smart-5c3d5fcb-af42-4f98-ae8e-12783f1b77bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899965638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.899965638
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.827184408
Short name T715
Test name
Test status
Simulation time 498567813093 ps
CPU time 1133.9 seconds
Started Jul 31 06:48:10 PM PDT 24
Finished Jul 31 07:07:04 PM PDT 24
Peak memory 201520 kb
Host smart-67fca546-1484-4d25-b058-92d6b538c1af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827184408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.827184408
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2933081376
Short name T292
Test name
Test status
Simulation time 331238348584 ps
CPU time 367.06 seconds
Started Jul 31 06:48:13 PM PDT 24
Finished Jul 31 06:54:20 PM PDT 24
Peak memory 201420 kb
Host smart-a9748014-e1be-4961-8c25-31c5c847b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933081376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2933081376
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3798299787
Short name T286
Test name
Test status
Simulation time 160868274635 ps
CPU time 185.21 seconds
Started Jul 31 06:48:00 PM PDT 24
Finished Jul 31 06:51:06 PM PDT 24
Peak memory 201488 kb
Host smart-ff157550-8db5-4bfd-87b1-606c6823dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798299787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3798299787
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3694440932
Short name T769
Test name
Test status
Simulation time 336039810617 ps
CPU time 742.12 seconds
Started Jul 31 06:48:10 PM PDT 24
Finished Jul 31 07:00:33 PM PDT 24
Peak memory 201428 kb
Host smart-74e2e4ee-0fa6-4bf5-ad26-2b271ee9d44f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694440932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3694440932
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2294021666
Short name T321
Test name
Test status
Simulation time 489553365369 ps
CPU time 588.63 seconds
Started Jul 31 06:48:00 PM PDT 24
Finished Jul 31 06:57:49 PM PDT 24
Peak memory 201520 kb
Host smart-2c54e015-16f5-479b-a642-cc55e077bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294021666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2294021666
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2516983614
Short name T14
Test name
Test status
Simulation time 162283961607 ps
CPU time 58.79 seconds
Started Jul 31 06:48:00 PM PDT 24
Finished Jul 31 06:48:59 PM PDT 24
Peak memory 201452 kb
Host smart-b132d1f5-2225-4d72-a9ab-292295cb837e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516983614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2516983614
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3265107627
Short name T653
Test name
Test status
Simulation time 598567983385 ps
CPU time 1282.04 seconds
Started Jul 31 06:48:04 PM PDT 24
Finished Jul 31 07:09:27 PM PDT 24
Peak memory 201448 kb
Host smart-ac654561-940b-43b6-991b-9a4ab5953c53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265107627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3265107627
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2295649929
Short name T376
Test name
Test status
Simulation time 196330143615 ps
CPU time 302.71 seconds
Started Jul 31 06:48:06 PM PDT 24
Finished Jul 31 06:53:08 PM PDT 24
Peak memory 201432 kb
Host smart-595d203d-595d-4239-a49e-8a6993655737
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295649929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2295649929
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4232782541
Short name T426
Test name
Test status
Simulation time 70028476692 ps
CPU time 258.08 seconds
Started Jul 31 06:48:10 PM PDT 24
Finished Jul 31 06:52:28 PM PDT 24
Peak memory 201864 kb
Host smart-8c7f555b-5272-4370-8a5e-1bb5a1d817c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232782541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4232782541
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3767865495
Short name T621
Test name
Test status
Simulation time 27840288079 ps
CPU time 30.56 seconds
Started Jul 31 06:48:11 PM PDT 24
Finished Jul 31 06:48:41 PM PDT 24
Peak memory 201356 kb
Host smart-b7ee6a6b-4ab9-4c90-b4d4-a0181cb9815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767865495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3767865495
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.356748665
Short name T413
Test name
Test status
Simulation time 5009250589 ps
CPU time 1.62 seconds
Started Jul 31 06:48:12 PM PDT 24
Finished Jul 31 06:48:13 PM PDT 24
Peak memory 201356 kb
Host smart-c2087ad0-7dbb-4c33-9fc4-80f9f522d9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356748665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.356748665
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.195556492
Short name T429
Test name
Test status
Simulation time 6035557476 ps
CPU time 4.28 seconds
Started Jul 31 06:47:59 PM PDT 24
Finished Jul 31 06:48:03 PM PDT 24
Peak memory 201432 kb
Host smart-9e66056f-1d64-4b42-a588-1c13cdcd5508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195556492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.195556492
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1684563387
Short name T81
Test name
Test status
Simulation time 280100901 ps
CPU time 1.28 seconds
Started Jul 31 06:48:27 PM PDT 24
Finished Jul 31 06:48:29 PM PDT 24
Peak memory 201220 kb
Host smart-5cd05d33-6706-46f2-b22a-14f47c38b35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684563387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1684563387
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.30421997
Short name T273
Test name
Test status
Simulation time 352446100125 ps
CPU time 813.71 seconds
Started Jul 31 06:48:23 PM PDT 24
Finished Jul 31 07:01:57 PM PDT 24
Peak memory 201488 kb
Host smart-24d4c5ef-6891-49cf-abd0-0e0e39af671c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30421997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gatin
g.30421997
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3766203720
Short name T275
Test name
Test status
Simulation time 515424369271 ps
CPU time 330.35 seconds
Started Jul 31 06:48:24 PM PDT 24
Finished Jul 31 06:53:55 PM PDT 24
Peak memory 201496 kb
Host smart-51e22830-a7c7-47d2-a149-3f017b7a1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766203720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3766203720
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1884825724
Short name T243
Test name
Test status
Simulation time 166768526229 ps
CPU time 103.33 seconds
Started Jul 31 06:48:16 PM PDT 24
Finished Jul 31 06:50:00 PM PDT 24
Peak memory 201444 kb
Host smart-5141f342-6f53-43dc-a671-bcb2af04b2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884825724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1884825724
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1256619647
Short name T720
Test name
Test status
Simulation time 323258963969 ps
CPU time 196.6 seconds
Started Jul 31 06:48:17 PM PDT 24
Finished Jul 31 06:51:33 PM PDT 24
Peak memory 201412 kb
Host smart-78570306-911b-495a-a4af-272a3efeb3a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256619647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1256619647
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3827099248
Short name T28
Test name
Test status
Simulation time 162046908838 ps
CPU time 361.35 seconds
Started Jul 31 06:48:16 PM PDT 24
Finished Jul 31 06:54:18 PM PDT 24
Peak memory 201480 kb
Host smart-c8505d43-39cb-4ae5-b521-6051392bbeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827099248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3827099248
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3602396382
Short name T541
Test name
Test status
Simulation time 332898092349 ps
CPU time 790.56 seconds
Started Jul 31 06:48:15 PM PDT 24
Finished Jul 31 07:01:26 PM PDT 24
Peak memory 201420 kb
Host smart-67e437dc-bb4d-401c-9f70-1072dff08dc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602396382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3602396382
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2481405802
Short name T324
Test name
Test status
Simulation time 374704777691 ps
CPU time 215.7 seconds
Started Jul 31 06:48:17 PM PDT 24
Finished Jul 31 06:51:52 PM PDT 24
Peak memory 201476 kb
Host smart-a508ff1f-899d-4974-9b2e-3aac7ea27b0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481405802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2481405802
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1856719834
Short name T767
Test name
Test status
Simulation time 412648153888 ps
CPU time 478.92 seconds
Started Jul 31 06:48:16 PM PDT 24
Finished Jul 31 06:56:15 PM PDT 24
Peak memory 201456 kb
Host smart-ef970c17-26e7-424c-8668-3f1fed1da952
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856719834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1856719834
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4202885575
Short name T575
Test name
Test status
Simulation time 88860286223 ps
CPU time 454.93 seconds
Started Jul 31 06:48:23 PM PDT 24
Finished Jul 31 06:55:58 PM PDT 24
Peak memory 201836 kb
Host smart-fab73ffd-c8ab-4274-9137-548cc23366d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202885575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4202885575
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3574272722
Short name T512
Test name
Test status
Simulation time 28887244096 ps
CPU time 32.56 seconds
Started Jul 31 06:48:23 PM PDT 24
Finished Jul 31 06:48:56 PM PDT 24
Peak memory 201312 kb
Host smart-8df0764a-0112-4741-bd31-dc4a83386486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574272722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3574272722
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3438736696
Short name T780
Test name
Test status
Simulation time 4911958039 ps
CPU time 2.73 seconds
Started Jul 31 06:48:22 PM PDT 24
Finished Jul 31 06:48:25 PM PDT 24
Peak memory 201384 kb
Host smart-f7f76007-2e9a-4145-9101-01b03be2711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438736696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3438736696
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.784422836
Short name T549
Test name
Test status
Simulation time 6018432087 ps
CPU time 13.99 seconds
Started Jul 31 06:48:16 PM PDT 24
Finished Jul 31 06:48:30 PM PDT 24
Peak memory 201340 kb
Host smart-3f9d7512-d729-485f-a9c5-a5007891818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784422836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.784422836
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1250663462
Short name T781
Test name
Test status
Simulation time 398766783237 ps
CPU time 987.78 seconds
Started Jul 31 06:48:29 PM PDT 24
Finished Jul 31 07:04:57 PM PDT 24
Peak memory 211964 kb
Host smart-00fee959-5962-4ff0-b6f0-e6f38cd18bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250663462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1250663462
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.888783006
Short name T619
Test name
Test status
Simulation time 537937461 ps
CPU time 0.91 seconds
Started Jul 31 06:48:50 PM PDT 24
Finished Jul 31 06:48:51 PM PDT 24
Peak memory 201236 kb
Host smart-ca4f6dc5-7cac-4abf-83a9-3c1492e4da2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888783006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.888783006
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3376733550
Short name T688
Test name
Test status
Simulation time 163561773117 ps
CPU time 7.27 seconds
Started Jul 31 06:48:44 PM PDT 24
Finished Jul 31 06:48:52 PM PDT 24
Peak memory 201376 kb
Host smart-3a79509d-e2a6-4804-8c02-1047b3179005
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376733550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3376733550
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3866812982
Short name T255
Test name
Test status
Simulation time 332591277196 ps
CPU time 574.11 seconds
Started Jul 31 06:48:45 PM PDT 24
Finished Jul 31 06:58:19 PM PDT 24
Peak memory 201584 kb
Host smart-eac9564f-1feb-4e68-b9cc-269705720c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866812982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3866812982
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2934141096
Short name T731
Test name
Test status
Simulation time 162434275853 ps
CPU time 86.57 seconds
Started Jul 31 06:48:32 PM PDT 24
Finished Jul 31 06:49:58 PM PDT 24
Peak memory 201480 kb
Host smart-4b2c3a7e-9454-4f70-a40f-203ae05f234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934141096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2934141096
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3976945845
Short name T424
Test name
Test status
Simulation time 475233081957 ps
CPU time 1105.07 seconds
Started Jul 31 06:48:39 PM PDT 24
Finished Jul 31 07:07:05 PM PDT 24
Peak memory 201416 kb
Host smart-5a0a04c8-394c-49da-84da-fe3d485420db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976945845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3976945845
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3773914916
Short name T661
Test name
Test status
Simulation time 489504158795 ps
CPU time 1005.03 seconds
Started Jul 31 06:48:32 PM PDT 24
Finished Jul 31 07:05:18 PM PDT 24
Peak memory 201496 kb
Host smart-29e44582-a953-47ae-93b4-c65568d017c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773914916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3773914916
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.183457416
Short name T543
Test name
Test status
Simulation time 327626661863 ps
CPU time 707.7 seconds
Started Jul 31 06:48:33 PM PDT 24
Finished Jul 31 07:00:21 PM PDT 24
Peak memory 201464 kb
Host smart-59f082d0-5f66-4f38-8af3-e935310d39cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=183457416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.183457416
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.947862904
Short name T380
Test name
Test status
Simulation time 199407178562 ps
CPU time 439.84 seconds
Started Jul 31 06:48:38 PM PDT 24
Finished Jul 31 06:55:58 PM PDT 24
Peak memory 201488 kb
Host smart-668391a7-ab39-40b6-b3e8-6553c8b61bc5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947862904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.947862904
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.11323849
Short name T346
Test name
Test status
Simulation time 67832559157 ps
CPU time 213.03 seconds
Started Jul 31 06:48:43 PM PDT 24
Finished Jul 31 06:52:16 PM PDT 24
Peak memory 201860 kb
Host smart-d0ab9998-069a-4ed1-9713-9f972aa9dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11323849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.11323849
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2266611927
Short name T699
Test name
Test status
Simulation time 45607117721 ps
CPU time 105.4 seconds
Started Jul 31 06:48:43 PM PDT 24
Finished Jul 31 06:50:29 PM PDT 24
Peak memory 201396 kb
Host smart-a8eaedcb-1ff8-448a-984c-a22bb5a76a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266611927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2266611927
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2475918737
Short name T359
Test name
Test status
Simulation time 5391330434 ps
CPU time 12.35 seconds
Started Jul 31 06:48:43 PM PDT 24
Finished Jul 31 06:48:56 PM PDT 24
Peak memory 201384 kb
Host smart-5705e1b7-c147-40c8-9d40-2e82f270b459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475918737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2475918737
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1929934187
Short name T485
Test name
Test status
Simulation time 5941630442 ps
CPU time 6.7 seconds
Started Jul 31 06:48:27 PM PDT 24
Finished Jul 31 06:48:34 PM PDT 24
Peak memory 201364 kb
Host smart-012bc19c-4917-4195-bfbf-8da400362d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929934187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1929934187
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.791499823
Short name T225
Test name
Test status
Simulation time 525795824190 ps
CPU time 290.75 seconds
Started Jul 31 06:48:44 PM PDT 24
Finished Jul 31 06:53:34 PM PDT 24
Peak memory 217332 kb
Host smart-79460ca2-6b49-4e88-8f39-c9e06cdb1ea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791499823 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.791499823
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.605056555
Short name T511
Test name
Test status
Simulation time 434315432 ps
CPU time 0.8 seconds
Started Jul 31 06:49:06 PM PDT 24
Finished Jul 31 06:49:07 PM PDT 24
Peak memory 201184 kb
Host smart-11194430-9f2a-489b-867f-235f9761031b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605056555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.605056555
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2077003801
Short name T262
Test name
Test status
Simulation time 159310149280 ps
CPU time 91.98 seconds
Started Jul 31 06:49:01 PM PDT 24
Finished Jul 31 06:50:33 PM PDT 24
Peak memory 201440 kb
Host smart-b43a0bd8-b94c-4b92-b403-401e937478e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077003801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2077003801
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1368772868
Short name T153
Test name
Test status
Simulation time 162161709334 ps
CPU time 102.16 seconds
Started Jul 31 06:48:59 PM PDT 24
Finished Jul 31 06:50:42 PM PDT 24
Peak memory 201476 kb
Host smart-dceb4bc9-cd51-444a-b4f7-ec4fd458cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368772868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1368772868
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3022038258
Short name T756
Test name
Test status
Simulation time 492049869815 ps
CPU time 118 seconds
Started Jul 31 06:48:55 PM PDT 24
Finished Jul 31 06:50:53 PM PDT 24
Peak memory 201464 kb
Host smart-51d1a610-0272-4991-9b92-786c50eee486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022038258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3022038258
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1328551087
Short name T573
Test name
Test status
Simulation time 487967704428 ps
CPU time 1080.03 seconds
Started Jul 31 06:48:57 PM PDT 24
Finished Jul 31 07:06:57 PM PDT 24
Peak memory 201488 kb
Host smart-5364c520-378a-4b3e-88db-625966445dd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328551087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1328551087
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2615310686
Short name T538
Test name
Test status
Simulation time 163661386559 ps
CPU time 218.96 seconds
Started Jul 31 06:48:48 PM PDT 24
Finished Jul 31 06:52:27 PM PDT 24
Peak memory 201432 kb
Host smart-d288a01c-26ea-4658-b14b-f56a44394f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615310686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2615310686
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2641614782
Short name T504
Test name
Test status
Simulation time 328441187116 ps
CPU time 103.39 seconds
Started Jul 31 06:48:54 PM PDT 24
Finished Jul 31 06:50:38 PM PDT 24
Peak memory 201448 kb
Host smart-0fa4b8cd-e0ad-4f0a-8f83-799d9883eac8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641614782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2641614782
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3252294724
Short name T377
Test name
Test status
Simulation time 609417416751 ps
CPU time 688.36 seconds
Started Jul 31 06:49:00 PM PDT 24
Finished Jul 31 07:00:29 PM PDT 24
Peak memory 201424 kb
Host smart-e21a9207-a8b1-4822-9af6-a382586ec138
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252294724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3252294724
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1110054986
Short name T116
Test name
Test status
Simulation time 123083597495 ps
CPU time 605.27 seconds
Started Jul 31 06:48:59 PM PDT 24
Finished Jul 31 06:59:04 PM PDT 24
Peak memory 201856 kb
Host smart-4ca1799b-90e6-4d84-8b66-dbe27f2b3b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110054986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1110054986
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.436516248
Short name T355
Test name
Test status
Simulation time 29242431569 ps
CPU time 67.31 seconds
Started Jul 31 06:48:59 PM PDT 24
Finished Jul 31 06:50:07 PM PDT 24
Peak memory 201356 kb
Host smart-c3e8ea27-8c01-43c6-97b3-24cbb8c681b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436516248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.436516248
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3828549381
Short name T526
Test name
Test status
Simulation time 3549940823 ps
CPU time 4.67 seconds
Started Jul 31 06:48:59 PM PDT 24
Finished Jul 31 06:49:04 PM PDT 24
Peak memory 201360 kb
Host smart-8347be7c-b13f-4105-a257-4e6d49af9b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828549381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3828549381
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3106269710
Short name T362
Test name
Test status
Simulation time 5961997629 ps
CPU time 4.69 seconds
Started Jul 31 06:48:49 PM PDT 24
Finished Jul 31 06:48:53 PM PDT 24
Peak memory 201348 kb
Host smart-8eca0b03-e6c6-4396-aa25-3b39aeb99601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106269710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3106269710
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1168803206
Short name T244
Test name
Test status
Simulation time 168184516150 ps
CPU time 62.47 seconds
Started Jul 31 06:49:10 PM PDT 24
Finished Jul 31 06:50:12 PM PDT 24
Peak memory 201452 kb
Host smart-f5f38a5e-1863-4a8e-a4cb-850dc60eb7b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168803206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1168803206
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1860683552
Short name T21
Test name
Test status
Simulation time 68306875361 ps
CPU time 154.05 seconds
Started Jul 31 06:49:05 PM PDT 24
Finished Jul 31 06:51:39 PM PDT 24
Peak memory 209812 kb
Host smart-e8672e99-7e2a-47ce-98b3-9fc2071099bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860683552 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1860683552
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2116278011
Short name T439
Test name
Test status
Simulation time 440248213 ps
CPU time 1.57 seconds
Started Jul 31 06:49:24 PM PDT 24
Finished Jul 31 06:49:26 PM PDT 24
Peak memory 201260 kb
Host smart-17402686-92ae-4c78-a32a-fb68239d1fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116278011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2116278011
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4284503431
Short name T577
Test name
Test status
Simulation time 160314118002 ps
CPU time 106.39 seconds
Started Jul 31 06:49:11 PM PDT 24
Finished Jul 31 06:50:58 PM PDT 24
Peak memory 201500 kb
Host smart-6de54a4e-fa40-495f-a921-6ba5e1c907bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284503431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4284503431
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3243947684
Short name T710
Test name
Test status
Simulation time 345127692369 ps
CPU time 223.93 seconds
Started Jul 31 06:49:10 PM PDT 24
Finished Jul 31 06:52:54 PM PDT 24
Peak memory 201468 kb
Host smart-4bd9fecf-dd0f-46f1-914f-980626254e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243947684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3243947684
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.591249726
Short name T232
Test name
Test status
Simulation time 494473834874 ps
CPU time 300.15 seconds
Started Jul 31 06:49:10 PM PDT 24
Finished Jul 31 06:54:10 PM PDT 24
Peak memory 201480 kb
Host smart-8b22a0e9-5a66-4918-8c69-09904aba0bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591249726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.591249726
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3071912655
Short name T497
Test name
Test status
Simulation time 329755772297 ps
CPU time 766.65 seconds
Started Jul 31 06:49:14 PM PDT 24
Finished Jul 31 07:02:01 PM PDT 24
Peak memory 201480 kb
Host smart-bc3f73ae-c09c-436b-95ca-97d2ba99a173
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071912655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3071912655
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.938983831
Short name T221
Test name
Test status
Simulation time 327025287445 ps
CPU time 413.49 seconds
Started Jul 31 06:49:07 PM PDT 24
Finished Jul 31 06:56:00 PM PDT 24
Peak memory 201472 kb
Host smart-aabffd33-cddb-43e9-a6ea-e941c1059524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938983831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.938983831
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4046319596
Short name T589
Test name
Test status
Simulation time 328817824751 ps
CPU time 297.1 seconds
Started Jul 31 06:49:14 PM PDT 24
Finished Jul 31 06:54:12 PM PDT 24
Peak memory 201436 kb
Host smart-b292e61c-7696-4ce6-992c-49a7d387327c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046319596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4046319596
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2144626816
Short name T737
Test name
Test status
Simulation time 366023737353 ps
CPU time 233.94 seconds
Started Jul 31 06:49:11 PM PDT 24
Finished Jul 31 06:53:05 PM PDT 24
Peak memory 201432 kb
Host smart-7e33ab3b-ec1a-4aaa-b627-b07f57584658
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144626816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2144626816
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1075710014
Short name T450
Test name
Test status
Simulation time 190916689621 ps
CPU time 215.92 seconds
Started Jul 31 06:49:15 PM PDT 24
Finished Jul 31 06:52:51 PM PDT 24
Peak memory 201372 kb
Host smart-759ea135-309c-425a-a996-8b05e2c6f59a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075710014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1075710014
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1396579702
Short name T776
Test name
Test status
Simulation time 88220968419 ps
CPU time 295.58 seconds
Started Jul 31 06:49:18 PM PDT 24
Finished Jul 31 06:54:13 PM PDT 24
Peak memory 201800 kb
Host smart-ab800b4a-4d09-4a39-9bf1-9a4f709c24f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396579702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1396579702
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1041400034
Short name T525
Test name
Test status
Simulation time 24353557305 ps
CPU time 23.01 seconds
Started Jul 31 06:49:18 PM PDT 24
Finished Jul 31 06:49:41 PM PDT 24
Peak memory 201368 kb
Host smart-2bdecb7b-f336-4905-9ef3-463c425efead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041400034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1041400034
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2484213250
Short name T115
Test name
Test status
Simulation time 3118879023 ps
CPU time 1.56 seconds
Started Jul 31 06:49:15 PM PDT 24
Finished Jul 31 06:49:17 PM PDT 24
Peak memory 201320 kb
Host smart-7cc74f97-0d0d-4a14-9099-738bd5b98e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484213250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2484213250
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2126705988
Short name T486
Test name
Test status
Simulation time 5635800097 ps
CPU time 14.12 seconds
Started Jul 31 06:49:07 PM PDT 24
Finished Jul 31 06:49:22 PM PDT 24
Peak memory 201380 kb
Host smart-e59f43af-7158-46a9-9456-1f31ef43a6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126705988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2126705988
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3261581770
Short name T717
Test name
Test status
Simulation time 20916895822 ps
CPU time 41.15 seconds
Started Jul 31 06:49:15 PM PDT 24
Finished Jul 31 06:49:57 PM PDT 24
Peak memory 209800 kb
Host smart-f77dad7b-50e2-4054-b401-2465523f9513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261581770 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3261581770
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.250181230
Short name T357
Test name
Test status
Simulation time 370355067 ps
CPU time 1.48 seconds
Started Jul 31 06:49:34 PM PDT 24
Finished Jul 31 06:49:35 PM PDT 24
Peak memory 201228 kb
Host smart-4b5fff4b-1a0a-4175-8025-aa472c4da997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250181230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.250181230
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2095351018
Short name T771
Test name
Test status
Simulation time 203496720406 ps
CPU time 455.33 seconds
Started Jul 31 06:49:29 PM PDT 24
Finished Jul 31 06:57:05 PM PDT 24
Peak memory 201496 kb
Host smart-af67f971-71be-4736-bc03-85876a0bf477
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095351018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2095351018
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2392373843
Short name T301
Test name
Test status
Simulation time 188444493077 ps
CPU time 227.67 seconds
Started Jul 31 06:49:32 PM PDT 24
Finished Jul 31 06:53:20 PM PDT 24
Peak memory 201560 kb
Host smart-7c7debf3-f07b-446b-a2fa-b91e06d1815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392373843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2392373843
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.202877250
Short name T420
Test name
Test status
Simulation time 168675031633 ps
CPU time 387.67 seconds
Started Jul 31 06:49:30 PM PDT 24
Finished Jul 31 06:55:58 PM PDT 24
Peak memory 201440 kb
Host smart-5a762e7b-1432-4eb6-850f-8bb662fb70af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=202877250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.202877250
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2623869114
Short name T332
Test name
Test status
Simulation time 488218022960 ps
CPU time 1173.55 seconds
Started Jul 31 06:49:28 PM PDT 24
Finished Jul 31 07:09:02 PM PDT 24
Peak memory 201372 kb
Host smart-b2f9e6fa-3702-490c-85b9-6661f73e5224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623869114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2623869114
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1168401576
Short name T721
Test name
Test status
Simulation time 165836598041 ps
CPU time 394.63 seconds
Started Jul 31 06:49:28 PM PDT 24
Finished Jul 31 06:56:03 PM PDT 24
Peak memory 201400 kb
Host smart-76579b8f-7258-4660-8929-cac9a058fc61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168401576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1168401576
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.241634753
Short name T155
Test name
Test status
Simulation time 414884574910 ps
CPU time 251.6 seconds
Started Jul 31 06:49:28 PM PDT 24
Finished Jul 31 06:53:40 PM PDT 24
Peak memory 201476 kb
Host smart-4bee98c7-6287-4668-aaf4-2a32a3b9d6bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241634753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.241634753
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.664210598
Short name T61
Test name
Test status
Simulation time 101981519989 ps
CPU time 426.37 seconds
Started Jul 31 06:49:36 PM PDT 24
Finished Jul 31 06:56:42 PM PDT 24
Peak memory 201848 kb
Host smart-36043e2c-76cb-4ba3-b081-50b3c02985b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664210598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.664210598
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3444595976
Short name T484
Test name
Test status
Simulation time 25471349338 ps
CPU time 15.77 seconds
Started Jul 31 06:49:34 PM PDT 24
Finished Jul 31 06:49:50 PM PDT 24
Peak memory 201384 kb
Host smart-80f0ff82-a5a1-4490-862d-76546b8f8b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444595976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3444595976
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2497260522
Short name T637
Test name
Test status
Simulation time 3275462181 ps
CPU time 2.46 seconds
Started Jul 31 06:49:28 PM PDT 24
Finished Jul 31 06:49:30 PM PDT 24
Peak memory 201388 kb
Host smart-a7a0990e-2f1e-4816-95dc-0ffbdb7eb42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497260522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2497260522
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3603223765
Short name T448
Test name
Test status
Simulation time 5953842621 ps
CPU time 1.75 seconds
Started Jul 31 06:49:30 PM PDT 24
Finished Jul 31 06:49:32 PM PDT 24
Peak memory 201388 kb
Host smart-386f661e-6300-4142-b9a0-4a4d2402c6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603223765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3603223765
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3598239317
Short name T430
Test name
Test status
Simulation time 352812165 ps
CPU time 1.43 seconds
Started Jul 31 06:49:52 PM PDT 24
Finished Jul 31 06:49:53 PM PDT 24
Peak memory 201256 kb
Host smart-42ed1ab7-944f-4692-99c0-1602de610f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598239317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3598239317
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.925277641
Short name T234
Test name
Test status
Simulation time 521149374728 ps
CPU time 814.79 seconds
Started Jul 31 06:49:39 PM PDT 24
Finished Jul 31 07:03:14 PM PDT 24
Peak memory 201484 kb
Host smart-347bf2ec-a7ab-4ba4-ae90-c56d1004ffb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925277641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.925277641
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1250455249
Short name T227
Test name
Test status
Simulation time 557291574510 ps
CPU time 1328.07 seconds
Started Jul 31 06:49:43 PM PDT 24
Finished Jul 31 07:11:52 PM PDT 24
Peak memory 201440 kb
Host smart-95550639-4085-48cb-9535-f3722d12390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250455249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1250455249
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3999838066
Short name T272
Test name
Test status
Simulation time 162301525793 ps
CPU time 152.9 seconds
Started Jul 31 06:49:40 PM PDT 24
Finished Jul 31 06:52:13 PM PDT 24
Peak memory 201464 kb
Host smart-85581888-c868-4a8a-8c4f-fa1ade0ce22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999838066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3999838066
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1327713851
Short name T418
Test name
Test status
Simulation time 161852626799 ps
CPU time 63.14 seconds
Started Jul 31 06:49:40 PM PDT 24
Finished Jul 31 06:50:43 PM PDT 24
Peak memory 201352 kb
Host smart-e504a493-c6bd-45bd-b572-6abaa23eb109
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327713851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1327713851
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1254949296
Short name T152
Test name
Test status
Simulation time 332458066456 ps
CPU time 386.42 seconds
Started Jul 31 06:49:35 PM PDT 24
Finished Jul 31 06:56:02 PM PDT 24
Peak memory 201456 kb
Host smart-fe66b65a-a868-4852-883b-bd67522362f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254949296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1254949296
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.830171017
Short name T3
Test name
Test status
Simulation time 170287052429 ps
CPU time 104.51 seconds
Started Jul 31 06:49:40 PM PDT 24
Finished Jul 31 06:51:24 PM PDT 24
Peak memory 201436 kb
Host smart-47bc222d-5f59-4422-8549-1e395abaf9c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=830171017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.830171017
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2873621114
Short name T546
Test name
Test status
Simulation time 403455348363 ps
CPU time 846.56 seconds
Started Jul 31 06:49:46 PM PDT 24
Finished Jul 31 07:03:53 PM PDT 24
Peak memory 201420 kb
Host smart-c4d4cec8-e0b8-49de-ab4a-4069c034ec78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873621114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2873621114
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.79342256
Short name T681
Test name
Test status
Simulation time 78953377088 ps
CPU time 392.15 seconds
Started Jul 31 06:49:51 PM PDT 24
Finished Jul 31 06:56:24 PM PDT 24
Peak memory 201820 kb
Host smart-4519c576-4381-4365-b21f-7ad498968dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79342256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.79342256
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.485281989
Short name T683
Test name
Test status
Simulation time 22734942304 ps
CPU time 53.53 seconds
Started Jul 31 06:49:45 PM PDT 24
Finished Jul 31 06:50:39 PM PDT 24
Peak memory 201368 kb
Host smart-46891294-2ba8-45e0-8176-a02b3a61585f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485281989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.485281989
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1282996356
Short name T408
Test name
Test status
Simulation time 4017463518 ps
CPU time 5.34 seconds
Started Jul 31 06:49:45 PM PDT 24
Finished Jul 31 06:49:50 PM PDT 24
Peak memory 201360 kb
Host smart-5fdecc3c-1ab7-4514-89b0-c275171017a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282996356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1282996356
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4013958810
Short name T396
Test name
Test status
Simulation time 5661256733 ps
CPU time 6.03 seconds
Started Jul 31 06:49:34 PM PDT 24
Finished Jul 31 06:49:40 PM PDT 24
Peak memory 201380 kb
Host smart-bc6d4e4f-ce26-4510-9bb2-c0e91004d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013958810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4013958810
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2720244048
Short name T175
Test name
Test status
Simulation time 168433601762 ps
CPU time 379.97 seconds
Started Jul 31 06:49:49 PM PDT 24
Finished Jul 31 06:56:10 PM PDT 24
Peak memory 201388 kb
Host smart-a29bef19-14b8-4cba-b5bc-233bcbc5f0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720244048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2720244048
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.163555847
Short name T552
Test name
Test status
Simulation time 528477261 ps
CPU time 1.23 seconds
Started Jul 31 06:50:08 PM PDT 24
Finished Jul 31 06:50:09 PM PDT 24
Peak memory 201260 kb
Host smart-75b90061-99e4-4947-93d0-59b09e8117dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163555847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.163555847
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3820202948
Short name T111
Test name
Test status
Simulation time 495956826794 ps
CPU time 1209.44 seconds
Started Jul 31 06:49:58 PM PDT 24
Finished Jul 31 07:10:08 PM PDT 24
Peak memory 201520 kb
Host smart-c9b5246d-fe8d-4b88-aeae-89a0e23d9784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820202948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3820202948
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1010152253
Short name T290
Test name
Test status
Simulation time 162353837694 ps
CPU time 138.15 seconds
Started Jul 31 06:49:56 PM PDT 24
Finished Jul 31 06:52:15 PM PDT 24
Peak memory 201480 kb
Host smart-dcdca7c9-9ad5-4041-8c7f-7e6b63115a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010152253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1010152253
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1278952895
Short name T608
Test name
Test status
Simulation time 497427416544 ps
CPU time 1147.84 seconds
Started Jul 31 06:49:57 PM PDT 24
Finished Jul 31 07:09:05 PM PDT 24
Peak memory 201480 kb
Host smart-2e6c37cd-d60d-424a-93fb-44dc65ba6af8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278952895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1278952895
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4283555584
Short name T289
Test name
Test status
Simulation time 166079404184 ps
CPU time 99.01 seconds
Started Jul 31 06:49:53 PM PDT 24
Finished Jul 31 06:51:32 PM PDT 24
Peak memory 201448 kb
Host smart-f9f9be3c-d2be-45b3-ba65-e2a51c5113fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283555584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4283555584
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1506531323
Short name T665
Test name
Test status
Simulation time 482420163436 ps
CPU time 524.26 seconds
Started Jul 31 06:49:51 PM PDT 24
Finished Jul 31 06:58:36 PM PDT 24
Peak memory 201456 kb
Host smart-d8fd9658-4138-4266-946c-d48554761ce3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506531323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1506531323
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2500469107
Short name T677
Test name
Test status
Simulation time 360415207414 ps
CPU time 209.72 seconds
Started Jul 31 06:49:57 PM PDT 24
Finished Jul 31 06:53:26 PM PDT 24
Peak memory 201428 kb
Host smart-67474e29-4d72-44a0-873a-8c3b3cf335c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500469107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2500469107
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4121063579
Short name T93
Test name
Test status
Simulation time 607518455199 ps
CPU time 198.67 seconds
Started Jul 31 06:49:57 PM PDT 24
Finished Jul 31 06:53:16 PM PDT 24
Peak memory 201424 kb
Host smart-276d9324-c0c1-4f85-8c15-2537fef724a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121063579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.4121063579
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2138376287
Short name T611
Test name
Test status
Simulation time 118587275176 ps
CPU time 426.1 seconds
Started Jul 31 06:50:01 PM PDT 24
Finished Jul 31 06:57:08 PM PDT 24
Peak memory 201848 kb
Host smart-3676e66c-bcc8-4fde-abca-f7828db2f3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138376287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2138376287
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1999831389
Short name T718
Test name
Test status
Simulation time 45932898901 ps
CPU time 38.32 seconds
Started Jul 31 06:50:01 PM PDT 24
Finished Jul 31 06:50:40 PM PDT 24
Peak memory 201324 kb
Host smart-04f2dfdf-bf6a-4812-9ed0-b546307f34e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999831389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1999831389
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2612124256
Short name T121
Test name
Test status
Simulation time 4031236899 ps
CPU time 9.7 seconds
Started Jul 31 06:49:57 PM PDT 24
Finished Jul 31 06:50:07 PM PDT 24
Peak memory 201356 kb
Host smart-b0f9184e-3497-4e1b-af53-46ab63370e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612124256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2612124256
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.704974340
Short name T583
Test name
Test status
Simulation time 6074426538 ps
CPU time 15.19 seconds
Started Jul 31 06:49:51 PM PDT 24
Finished Jul 31 06:50:07 PM PDT 24
Peak memory 201316 kb
Host smart-a16442a4-837b-4e29-98fd-c1151f70c08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704974340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.704974340
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1097716137
Short name T694
Test name
Test status
Simulation time 172056936208 ps
CPU time 204.58 seconds
Started Jul 31 06:50:08 PM PDT 24
Finished Jul 31 06:53:33 PM PDT 24
Peak memory 201472 kb
Host smart-be1cfe22-e6b9-4c91-b622-3a553c35e5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097716137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1097716137
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1916979262
Short name T606
Test name
Test status
Simulation time 84414523309 ps
CPU time 106.16 seconds
Started Jul 31 06:50:02 PM PDT 24
Finished Jul 31 06:51:48 PM PDT 24
Peak memory 210112 kb
Host smart-090d9213-84f5-4a83-a119-9f2d6a81da60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916979262 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1916979262
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.832972463
Short name T27
Test name
Test status
Simulation time 336266216 ps
CPU time 1.41 seconds
Started Jul 31 06:38:24 PM PDT 24
Finished Jul 31 06:38:26 PM PDT 24
Peak memory 201288 kb
Host smart-d5a1c72b-1018-415a-a4c5-1e39a4cbe8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832972463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.832972463
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.865255845
Short name T280
Test name
Test status
Simulation time 526249897146 ps
CPU time 590.99 seconds
Started Jul 31 06:38:17 PM PDT 24
Finished Jul 31 06:48:08 PM PDT 24
Peak memory 201464 kb
Host smart-be487edb-5ed8-49e5-b1e4-0688a810f433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865255845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.865255845
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3180329257
Short name T631
Test name
Test status
Simulation time 497115477722 ps
CPU time 276.27 seconds
Started Jul 31 06:38:16 PM PDT 24
Finished Jul 31 06:42:52 PM PDT 24
Peak memory 201528 kb
Host smart-38344003-1759-4b0f-906a-e87a1d433f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180329257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3180329257
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1909754512
Short name T613
Test name
Test status
Simulation time 325396489891 ps
CPU time 199.63 seconds
Started Jul 31 06:38:17 PM PDT 24
Finished Jul 31 06:41:37 PM PDT 24
Peak memory 201448 kb
Host smart-9d202627-9587-4a4a-918c-04d93cfcc634
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909754512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1909754512
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.350900056
Short name T666
Test name
Test status
Simulation time 332156622394 ps
CPU time 724.82 seconds
Started Jul 31 06:38:12 PM PDT 24
Finished Jul 31 06:50:17 PM PDT 24
Peak memory 201452 kb
Host smart-0178a6ae-cbc3-45c5-9cd2-0c26693621e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350900056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.350900056
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3722039807
Short name T643
Test name
Test status
Simulation time 170037400894 ps
CPU time 395.91 seconds
Started Jul 31 06:38:15 PM PDT 24
Finished Jul 31 06:44:51 PM PDT 24
Peak memory 201408 kb
Host smart-fe04c525-d3b1-4212-ba8e-f6c323bfe4d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722039807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3722039807
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3359576296
Short name T169
Test name
Test status
Simulation time 364793616199 ps
CPU time 397.7 seconds
Started Jul 31 06:38:18 PM PDT 24
Finished Jul 31 06:44:56 PM PDT 24
Peak memory 201436 kb
Host smart-e5b8381e-9dde-43d7-bde5-58020f19f44d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359576296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3359576296
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2373624127
Short name T624
Test name
Test status
Simulation time 205622910888 ps
CPU time 343.98 seconds
Started Jul 31 06:38:18 PM PDT 24
Finished Jul 31 06:44:02 PM PDT 24
Peak memory 201448 kb
Host smart-5f315d5f-1929-4b89-960b-1f842f375fd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373624127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2373624127
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3410110362
Short name T213
Test name
Test status
Simulation time 93744792142 ps
CPU time 363.58 seconds
Started Jul 31 06:38:25 PM PDT 24
Finished Jul 31 06:44:28 PM PDT 24
Peak memory 201864 kb
Host smart-51f000fb-424b-410a-9500-add457bfb0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410110362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3410110362
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3318728397
Short name T10
Test name
Test status
Simulation time 43004390027 ps
CPU time 96.61 seconds
Started Jul 31 06:38:25 PM PDT 24
Finished Jul 31 06:40:02 PM PDT 24
Peak memory 201392 kb
Host smart-cc19fef6-e9ec-44af-a8bd-f2d275e5c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318728397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3318728397
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1310586983
Short name T360
Test name
Test status
Simulation time 2957993838 ps
CPU time 1.83 seconds
Started Jul 31 06:38:21 PM PDT 24
Finished Jul 31 06:38:23 PM PDT 24
Peak memory 201368 kb
Host smart-92ac7e8d-0656-4a38-b092-0b8cf4021b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310586983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1310586983
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.265599443
Short name T91
Test name
Test status
Simulation time 4033964170 ps
CPU time 9.09 seconds
Started Jul 31 06:38:23 PM PDT 24
Finished Jul 31 06:38:33 PM PDT 24
Peak memory 217056 kb
Host smart-33a15d71-1741-4ab6-83c8-7e9859e10e56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265599443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.265599443
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.92675515
Short name T510
Test name
Test status
Simulation time 5876533612 ps
CPU time 7.88 seconds
Started Jul 31 06:38:13 PM PDT 24
Finished Jul 31 06:38:21 PM PDT 24
Peak memory 201392 kb
Host smart-f5d0e67b-0c82-42c4-991b-b7bf019d6be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92675515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.92675515
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.881930489
Short name T62
Test name
Test status
Simulation time 292945171824 ps
CPU time 510.92 seconds
Started Jul 31 06:38:22 PM PDT 24
Finished Jul 31 06:46:53 PM PDT 24
Peak memory 210032 kb
Host smart-0af925df-e858-43cb-b005-a02ee497631c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881930489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.881930489
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2015784743
Short name T740
Test name
Test status
Simulation time 476827574 ps
CPU time 1.62 seconds
Started Jul 31 06:50:31 PM PDT 24
Finished Jul 31 06:50:33 PM PDT 24
Peak memory 201268 kb
Host smart-2bf7ad94-3097-4833-a63d-d48466df54a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015784743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2015784743
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3614489800
Short name T99
Test name
Test status
Simulation time 345399667348 ps
CPU time 186.05 seconds
Started Jul 31 06:50:22 PM PDT 24
Finished Jul 31 06:53:28 PM PDT 24
Peak memory 201524 kb
Host smart-6d134a84-ab3d-4e4c-bf89-62f065aeca07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614489800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3614489800
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3825084037
Short name T156
Test name
Test status
Simulation time 415491228502 ps
CPU time 110.33 seconds
Started Jul 31 06:50:20 PM PDT 24
Finished Jul 31 06:52:11 PM PDT 24
Peak memory 201464 kb
Host smart-1f5fe3ef-f9d6-4338-8840-1328953830df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825084037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3825084037
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1167577639
Short name T30
Test name
Test status
Simulation time 328193956937 ps
CPU time 358.68 seconds
Started Jul 31 06:50:14 PM PDT 24
Finished Jul 31 06:56:13 PM PDT 24
Peak memory 201532 kb
Host smart-cc81ed18-bd13-4405-b97d-0e6b0e1933ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167577639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1167577639
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2056077041
Short name T49
Test name
Test status
Simulation time 320193740314 ps
CPU time 309.93 seconds
Started Jul 31 06:50:14 PM PDT 24
Finished Jul 31 06:55:24 PM PDT 24
Peak memory 201424 kb
Host smart-ed1d1723-9306-4d51-aeb3-595dfc648f65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056077041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2056077041
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.377319654
Short name T146
Test name
Test status
Simulation time 493935066395 ps
CPU time 1213.81 seconds
Started Jul 31 06:50:06 PM PDT 24
Finished Jul 31 07:10:20 PM PDT 24
Peak memory 201468 kb
Host smart-c1b9720e-7128-4d15-8984-a62eddf9ff85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377319654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.377319654
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2577941852
Short name T410
Test name
Test status
Simulation time 162466455897 ps
CPU time 63.03 seconds
Started Jul 31 06:50:08 PM PDT 24
Finished Jul 31 06:51:11 PM PDT 24
Peak memory 201464 kb
Host smart-a07ec447-8a68-4888-a92f-80b01d584d1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577941852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2577941852
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.928150074
Short name T553
Test name
Test status
Simulation time 176537329522 ps
CPU time 23.31 seconds
Started Jul 31 06:50:15 PM PDT 24
Finished Jul 31 06:50:39 PM PDT 24
Peak memory 201448 kb
Host smart-e3763258-8f0e-4500-bb91-de2e70aa3c59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928150074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.928150074
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2321144594
Short name T747
Test name
Test status
Simulation time 604302741838 ps
CPU time 1290.16 seconds
Started Jul 31 06:50:15 PM PDT 24
Finished Jul 31 07:11:46 PM PDT 24
Peak memory 201508 kb
Host smart-85543ffe-8e2c-4091-8ab4-affe3177864c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321144594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2321144594
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.426406547
Short name T212
Test name
Test status
Simulation time 62670307286 ps
CPU time 256.64 seconds
Started Jul 31 06:50:22 PM PDT 24
Finished Jul 31 06:54:39 PM PDT 24
Peak memory 201856 kb
Host smart-57547f1d-7f8d-4376-a75e-178520b0aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426406547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.426406547
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2519191064
Short name T369
Test name
Test status
Simulation time 25067079864 ps
CPU time 15.43 seconds
Started Jul 31 06:50:22 PM PDT 24
Finished Jul 31 06:50:37 PM PDT 24
Peak memory 200716 kb
Host smart-00320871-c849-4e2a-8d2c-2eaff60f50f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519191064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2519191064
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3194075217
Short name T547
Test name
Test status
Simulation time 3085030008 ps
CPU time 7.51 seconds
Started Jul 31 06:50:22 PM PDT 24
Finished Jul 31 06:50:30 PM PDT 24
Peak memory 200584 kb
Host smart-96eb797e-58b3-4863-a0af-a9442f0ba939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194075217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3194075217
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3149391141
Short name T409
Test name
Test status
Simulation time 5749407191 ps
CPU time 7.13 seconds
Started Jul 31 06:50:09 PM PDT 24
Finished Jul 31 06:50:16 PM PDT 24
Peak memory 201364 kb
Host smart-b6b7fa0f-f0eb-4c29-8ed9-2510e7732c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149391141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3149391141
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1237137243
Short name T278
Test name
Test status
Simulation time 355512147494 ps
CPU time 320.32 seconds
Started Jul 31 06:50:30 PM PDT 24
Finished Jul 31 06:55:50 PM PDT 24
Peak memory 201464 kb
Host smart-b0cc538e-7b9d-4be8-9fe9-6b02ac3fa0fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237137243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1237137243
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3564913786
Short name T23
Test name
Test status
Simulation time 251779502901 ps
CPU time 161.48 seconds
Started Jul 31 06:50:27 PM PDT 24
Finished Jul 31 06:53:08 PM PDT 24
Peak memory 209784 kb
Host smart-56ecb901-b34c-4ceb-b164-6f606e13ed31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564913786 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3564913786
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3617824016
Short name T587
Test name
Test status
Simulation time 294335527 ps
CPU time 1.28 seconds
Started Jul 31 06:50:44 PM PDT 24
Finished Jul 31 06:50:46 PM PDT 24
Peak memory 201276 kb
Host smart-383270ba-d330-4013-89a2-fce97ffac218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617824016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3617824016
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2908220013
Short name T782
Test name
Test status
Simulation time 359404030754 ps
CPU time 190.62 seconds
Started Jul 31 06:50:39 PM PDT 24
Finished Jul 31 06:53:50 PM PDT 24
Peak memory 201468 kb
Host smart-d01d62c4-d4d6-4e34-ab3c-7bb07fc7f92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908220013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2908220013
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2889793784
Short name T630
Test name
Test status
Simulation time 160583873171 ps
CPU time 96.12 seconds
Started Jul 31 06:50:30 PM PDT 24
Finished Jul 31 06:52:06 PM PDT 24
Peak memory 201472 kb
Host smart-03c45096-9d8e-4dbd-8b5d-304a375f3396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889793784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2889793784
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3771265459
Short name T759
Test name
Test status
Simulation time 333290660610 ps
CPU time 221.27 seconds
Started Jul 31 06:50:35 PM PDT 24
Finished Jul 31 06:54:16 PM PDT 24
Peak memory 201460 kb
Host smart-c82c63fa-652d-41ea-9112-71104b2e05d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771265459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3771265459
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2354836061
Short name T563
Test name
Test status
Simulation time 163585233011 ps
CPU time 365.07 seconds
Started Jul 31 06:50:28 PM PDT 24
Finished Jul 31 06:56:34 PM PDT 24
Peak memory 201464 kb
Host smart-852760fb-6473-456c-b677-d41e93ca090a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354836061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2354836061
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3606121692
Short name T208
Test name
Test status
Simulation time 376628226303 ps
CPU time 177.06 seconds
Started Jul 31 06:50:33 PM PDT 24
Finished Jul 31 06:53:30 PM PDT 24
Peak memory 201440 kb
Host smart-40c9f2d0-9885-4dc5-9755-24e803ea437a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606121692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3606121692
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1219604109
Short name T529
Test name
Test status
Simulation time 585828488142 ps
CPU time 225.45 seconds
Started Jul 31 06:50:35 PM PDT 24
Finished Jul 31 06:54:21 PM PDT 24
Peak memory 201532 kb
Host smart-d4774203-49a2-4b4c-9c48-dc853a408a03
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219604109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1219604109
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3767805843
Short name T596
Test name
Test status
Simulation time 127902221519 ps
CPU time 619.01 seconds
Started Jul 31 06:50:39 PM PDT 24
Finished Jul 31 07:00:58 PM PDT 24
Peak memory 201888 kb
Host smart-0417a9eb-65aa-4044-93bd-5d5feca845c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767805843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3767805843
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3785495842
Short name T389
Test name
Test status
Simulation time 23451195026 ps
CPU time 53.59 seconds
Started Jul 31 06:50:40 PM PDT 24
Finished Jul 31 06:51:33 PM PDT 24
Peak memory 201352 kb
Host smart-9f0c6397-3122-4e0a-a78d-1e1af5a7b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785495842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3785495842
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4251280225
Short name T394
Test name
Test status
Simulation time 5277160892 ps
CPU time 5.39 seconds
Started Jul 31 06:50:39 PM PDT 24
Finished Jul 31 06:50:44 PM PDT 24
Peak memory 201356 kb
Host smart-48d1b73a-61b2-454f-bcd0-514212f67da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251280225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4251280225
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2290717729
Short name T557
Test name
Test status
Simulation time 5675040010 ps
CPU time 14.73 seconds
Started Jul 31 06:50:27 PM PDT 24
Finished Jul 31 06:50:42 PM PDT 24
Peak memory 201356 kb
Host smart-548255fa-5f14-4c9f-be76-91ec47743455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290717729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2290717729
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1048557527
Short name T482
Test name
Test status
Simulation time 1112289983799 ps
CPU time 829.91 seconds
Started Jul 31 06:50:45 PM PDT 24
Finished Jul 31 07:04:35 PM PDT 24
Peak memory 212184 kb
Host smart-cfef9a79-f58b-437c-b462-fb3bd833c262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048557527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1048557527
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3220507973
Short name T466
Test name
Test status
Simulation time 375804800 ps
CPU time 1.45 seconds
Started Jul 31 06:51:02 PM PDT 24
Finished Jul 31 06:51:03 PM PDT 24
Peak memory 201212 kb
Host smart-7941782e-5c1c-4b62-a4cf-05f66bc3475a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220507973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3220507973
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1733467896
Short name T786
Test name
Test status
Simulation time 518270914107 ps
CPU time 1081.91 seconds
Started Jul 31 06:50:50 PM PDT 24
Finished Jul 31 07:08:52 PM PDT 24
Peak memory 201512 kb
Host smart-256f41c5-eb41-438e-a12e-58a4efaaa537
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733467896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1733467896
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3986267124
Short name T749
Test name
Test status
Simulation time 158641619972 ps
CPU time 338.75 seconds
Started Jul 31 06:50:49 PM PDT 24
Finished Jul 31 06:56:28 PM PDT 24
Peak memory 201488 kb
Host smart-60dc8f0a-ce60-48ad-91f6-ec6062232b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986267124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3986267124
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3521971889
Short name T586
Test name
Test status
Simulation time 168311133781 ps
CPU time 94.14 seconds
Started Jul 31 06:50:44 PM PDT 24
Finished Jul 31 06:52:18 PM PDT 24
Peak memory 201500 kb
Host smart-d5f48a6d-ceb9-44b0-9757-cbe3318b463a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521971889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3521971889
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4273597411
Short name T566
Test name
Test status
Simulation time 500440733358 ps
CPU time 1032.33 seconds
Started Jul 31 06:50:44 PM PDT 24
Finished Jul 31 07:07:56 PM PDT 24
Peak memory 201460 kb
Host smart-6ecde145-7116-4e5e-ab23-d379dc533b28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273597411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4273597411
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3423078727
Short name T760
Test name
Test status
Simulation time 563816232516 ps
CPU time 222.55 seconds
Started Jul 31 06:50:45 PM PDT 24
Finished Jul 31 06:54:28 PM PDT 24
Peak memory 201400 kb
Host smart-7e03e54b-64e6-4249-8090-9688327f589c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423078727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3423078727
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1030022823
Short name T451
Test name
Test status
Simulation time 593720817245 ps
CPU time 530.75 seconds
Started Jul 31 06:50:54 PM PDT 24
Finished Jul 31 06:59:45 PM PDT 24
Peak memory 201560 kb
Host smart-293e7ab0-97ed-4e84-8763-02961df7b1a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030022823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1030022823
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.762943878
Short name T8
Test name
Test status
Simulation time 88586661957 ps
CPU time 480.09 seconds
Started Jul 31 06:51:03 PM PDT 24
Finished Jul 31 06:59:03 PM PDT 24
Peak memory 201856 kb
Host smart-835e4d50-7a69-465d-b4bc-c6c6ea1daae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762943878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.762943878
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1523152842
Short name T387
Test name
Test status
Simulation time 39539355714 ps
CPU time 7.84 seconds
Started Jul 31 06:50:56 PM PDT 24
Finished Jul 31 06:51:04 PM PDT 24
Peak memory 201356 kb
Host smart-51fd2802-594d-48b6-857d-8b0cbfbb0b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523152842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1523152842
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3659057200
Short name T746
Test name
Test status
Simulation time 3019759209 ps
CPU time 6.77 seconds
Started Jul 31 06:50:55 PM PDT 24
Finished Jul 31 06:51:02 PM PDT 24
Peak memory 201388 kb
Host smart-2f30105c-3ff0-4448-b58b-af74252cb066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659057200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3659057200
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3683509340
Short name T607
Test name
Test status
Simulation time 5707372174 ps
CPU time 4.48 seconds
Started Jul 31 06:50:49 PM PDT 24
Finished Jul 31 06:50:54 PM PDT 24
Peak memory 201380 kb
Host smart-cbab3cfb-0751-48e9-9c14-9752bd860786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683509340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3683509340
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.958133093
Short name T310
Test name
Test status
Simulation time 653747956749 ps
CPU time 1472.99 seconds
Started Jul 31 06:51:02 PM PDT 24
Finished Jul 31 07:15:35 PM PDT 24
Peak memory 218144 kb
Host smart-1242718e-671a-420c-80e5-6d7ac7eae5cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958133093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
958133093
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.654536567
Short name T778
Test name
Test status
Simulation time 417452235 ps
CPU time 0.76 seconds
Started Jul 31 06:51:11 PM PDT 24
Finished Jul 31 06:51:12 PM PDT 24
Peak memory 201268 kb
Host smart-c78d2069-87b5-464a-895e-4fbd6271d620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654536567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.654536567
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2029025563
Short name T727
Test name
Test status
Simulation time 162744050932 ps
CPU time 352.98 seconds
Started Jul 31 06:51:09 PM PDT 24
Finished Jul 31 06:57:02 PM PDT 24
Peak memory 201480 kb
Host smart-949c5f58-dd0b-40f2-baad-e8069de16391
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029025563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2029025563
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.268415223
Short name T664
Test name
Test status
Simulation time 158175366207 ps
CPU time 389.62 seconds
Started Jul 31 06:51:07 PM PDT 24
Finished Jul 31 06:57:37 PM PDT 24
Peak memory 201492 kb
Host smart-161a3c0f-09c3-489e-8234-eb37836cc843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268415223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.268415223
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2430751531
Short name T785
Test name
Test status
Simulation time 328473255889 ps
CPU time 372.74 seconds
Started Jul 31 06:51:06 PM PDT 24
Finished Jul 31 06:57:19 PM PDT 24
Peak memory 201508 kb
Host smart-5570a569-dc63-49da-9492-062ec3a838f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430751531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2430751531
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1953548512
Short name T615
Test name
Test status
Simulation time 494621772005 ps
CPU time 309.23 seconds
Started Jul 31 06:51:08 PM PDT 24
Finished Jul 31 06:56:17 PM PDT 24
Peak memory 201452 kb
Host smart-ba2882c8-8e51-4174-a545-aaa1eab2cef7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953548512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1953548512
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2161449551
Short name T458
Test name
Test status
Simulation time 161038454511 ps
CPU time 74.79 seconds
Started Jul 31 06:51:08 PM PDT 24
Finished Jul 31 06:52:23 PM PDT 24
Peak memory 201376 kb
Host smart-dfa34c36-32e8-4163-b180-c48eb546f622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161449551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2161449551
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1324451605
Short name T592
Test name
Test status
Simulation time 325725417804 ps
CPU time 50.42 seconds
Started Jul 31 06:51:07 PM PDT 24
Finished Jul 31 06:51:57 PM PDT 24
Peak memory 201480 kb
Host smart-8c398f78-f963-4e08-a69c-b711737030bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324451605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1324451605
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3492861448
Short name T209
Test name
Test status
Simulation time 196860298762 ps
CPU time 60.79 seconds
Started Jul 31 06:51:07 PM PDT 24
Finished Jul 31 06:52:08 PM PDT 24
Peak memory 201476 kb
Host smart-527951ca-2123-4a7e-9dc0-2eb9004a8bee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492861448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3492861448
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1780216866
Short name T456
Test name
Test status
Simulation time 613495901993 ps
CPU time 231.84 seconds
Started Jul 31 06:51:09 PM PDT 24
Finished Jul 31 06:55:01 PM PDT 24
Peak memory 201380 kb
Host smart-b7b44b55-3795-40c9-8b4b-f122c3c4e05e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780216866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1780216866
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.724387788
Short name T602
Test name
Test status
Simulation time 61919545505 ps
CPU time 221.19 seconds
Started Jul 31 06:51:11 PM PDT 24
Finished Jul 31 06:54:52 PM PDT 24
Peak memory 201896 kb
Host smart-75e38ca1-cc6a-4c87-9bdd-780adf819251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724387788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.724387788
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3072996940
Short name T744
Test name
Test status
Simulation time 33107184915 ps
CPU time 40.83 seconds
Started Jul 31 06:51:07 PM PDT 24
Finished Jul 31 06:51:48 PM PDT 24
Peak memory 201360 kb
Host smart-5653ce14-640d-48c3-be26-c891661f32ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072996940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3072996940
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4270670185
Short name T496
Test name
Test status
Simulation time 5425003848 ps
CPU time 13.87 seconds
Started Jul 31 06:51:06 PM PDT 24
Finished Jul 31 06:51:20 PM PDT 24
Peak memory 201360 kb
Host smart-7b660298-db81-496e-a3b2-901036da406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270670185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4270670185
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.4122703157
Short name T772
Test name
Test status
Simulation time 5732845036 ps
CPU time 4.08 seconds
Started Jul 31 06:51:02 PM PDT 24
Finished Jul 31 06:51:06 PM PDT 24
Peak memory 201364 kb
Host smart-6cd800c6-92ce-45a2-829d-bb62f1460178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122703157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.4122703157
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.653155887
Short name T679
Test name
Test status
Simulation time 162605917278 ps
CPU time 181.58 seconds
Started Jul 31 06:51:11 PM PDT 24
Finished Jul 31 06:54:13 PM PDT 24
Peak memory 201448 kb
Host smart-1459f986-a20e-4832-8efb-d3e89785a41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653155887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
653155887
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3000313506
Short name T365
Test name
Test status
Simulation time 503582384 ps
CPU time 0.81 seconds
Started Jul 31 06:51:27 PM PDT 24
Finished Jul 31 06:51:28 PM PDT 24
Peak memory 201252 kb
Host smart-6edd2240-5e62-409b-a809-fcf28f1ddf77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000313506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3000313506
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.589930931
Short name T316
Test name
Test status
Simulation time 556205009567 ps
CPU time 1358.36 seconds
Started Jul 31 06:51:17 PM PDT 24
Finished Jul 31 07:13:56 PM PDT 24
Peak memory 201500 kb
Host smart-257c2437-36b2-4b0b-a056-fe07e94135bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589930931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.589930931
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2925399668
Short name T585
Test name
Test status
Simulation time 326135099983 ps
CPU time 389.07 seconds
Started Jul 31 06:51:18 PM PDT 24
Finished Jul 31 06:57:47 PM PDT 24
Peak memory 201448 kb
Host smart-d96916c4-e25e-493c-8e0b-326544a37a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925399668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2925399668
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1030348975
Short name T395
Test name
Test status
Simulation time 162376053308 ps
CPU time 399.05 seconds
Started Jul 31 06:51:17 PM PDT 24
Finished Jul 31 06:57:56 PM PDT 24
Peak memory 201496 kb
Host smart-c7664643-5ffe-4ae6-8ef3-0394d1a73aef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030348975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1030348975
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2807366758
Short name T117
Test name
Test status
Simulation time 324423326766 ps
CPU time 739.31 seconds
Started Jul 31 06:51:23 PM PDT 24
Finished Jul 31 07:03:43 PM PDT 24
Peak memory 201356 kb
Host smart-45387f6a-b936-4d8b-8c83-f1da960a1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807366758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2807366758
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2804200268
Short name T766
Test name
Test status
Simulation time 485652556933 ps
CPU time 519.67 seconds
Started Jul 31 06:51:16 PM PDT 24
Finished Jul 31 06:59:56 PM PDT 24
Peak memory 201424 kb
Host smart-944839ba-73e9-483f-8b58-7d9aab9a8be6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804200268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2804200268
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1372827441
Short name T250
Test name
Test status
Simulation time 175713392549 ps
CPU time 121.28 seconds
Started Jul 31 06:51:19 PM PDT 24
Finished Jul 31 06:53:20 PM PDT 24
Peak memory 201428 kb
Host smart-5430a46a-6d69-403f-ace1-2c11f3471e02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372827441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1372827441
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.711758585
Short name T412
Test name
Test status
Simulation time 628979478151 ps
CPU time 327.56 seconds
Started Jul 31 06:51:17 PM PDT 24
Finished Jul 31 06:56:44 PM PDT 24
Peak memory 201452 kb
Host smart-c95c713c-7b74-45a6-b899-de97d20f9011
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711758585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.711758585
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1231844791
Short name T528
Test name
Test status
Simulation time 96115202721 ps
CPU time 338.45 seconds
Started Jul 31 06:51:21 PM PDT 24
Finished Jul 31 06:56:59 PM PDT 24
Peak memory 201836 kb
Host smart-63e04e9c-0f18-4e86-92dc-a647ad5734f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231844791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1231844791
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3119628817
Short name T392
Test name
Test status
Simulation time 25037238512 ps
CPU time 55.34 seconds
Started Jul 31 06:51:18 PM PDT 24
Finished Jul 31 06:52:13 PM PDT 24
Peak memory 201360 kb
Host smart-dbcbbb1a-1b60-40ae-b607-01a40073ab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119628817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3119628817
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1568788750
Short name T593
Test name
Test status
Simulation time 4448474413 ps
CPU time 2.98 seconds
Started Jul 31 06:51:17 PM PDT 24
Finished Jul 31 06:51:20 PM PDT 24
Peak memory 201316 kb
Host smart-206caa71-e7f1-48e0-aec0-ff116e56c8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568788750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1568788750
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.594129870
Short name T142
Test name
Test status
Simulation time 6087227590 ps
CPU time 3.82 seconds
Started Jul 31 06:51:11 PM PDT 24
Finished Jul 31 06:51:15 PM PDT 24
Peak memory 201360 kb
Host smart-378ea684-7fc3-4bcd-ae53-975f580c3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594129870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.594129870
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2983108883
Short name T251
Test name
Test status
Simulation time 492396235208 ps
CPU time 151.6 seconds
Started Jul 31 06:51:29 PM PDT 24
Finished Jul 31 06:54:00 PM PDT 24
Peak memory 201444 kb
Host smart-bbee938d-b18b-4dcf-b5a7-05a291f66f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983108883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2983108883
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.575871992
Short name T416
Test name
Test status
Simulation time 327171983 ps
CPU time 0.78 seconds
Started Jul 31 06:51:46 PM PDT 24
Finished Jul 31 06:51:47 PM PDT 24
Peak memory 201280 kb
Host smart-11916aa2-aef4-489b-84ea-842f6f435157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575871992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.575871992
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1905709302
Short name T790
Test name
Test status
Simulation time 351713168069 ps
CPU time 198.86 seconds
Started Jul 31 06:51:39 PM PDT 24
Finished Jul 31 06:54:58 PM PDT 24
Peak memory 201428 kb
Host smart-d7a05f66-0dfc-4437-a724-dcbda2ef5a6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905709302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1905709302
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.991732756
Short name T178
Test name
Test status
Simulation time 358299973630 ps
CPU time 454.9 seconds
Started Jul 31 06:51:39 PM PDT 24
Finished Jul 31 06:59:15 PM PDT 24
Peak memory 201464 kb
Host smart-7f06a0cf-ae19-47e7-87dd-64601b7d2cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991732756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.991732756
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3867452547
Short name T195
Test name
Test status
Simulation time 328616649263 ps
CPU time 705.26 seconds
Started Jul 31 06:51:34 PM PDT 24
Finished Jul 31 07:03:19 PM PDT 24
Peak memory 201472 kb
Host smart-b1da70c9-b092-4d3d-901e-76da47a557af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867452547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3867452547
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.592273184
Short name T167
Test name
Test status
Simulation time 329819818393 ps
CPU time 285.65 seconds
Started Jul 31 06:51:32 PM PDT 24
Finished Jul 31 06:56:18 PM PDT 24
Peak memory 201368 kb
Host smart-f7a15358-6e30-4607-a84d-919196ecfe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592273184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.592273184
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2571927795
Short name T110
Test name
Test status
Simulation time 328133846883 ps
CPU time 718.23 seconds
Started Jul 31 06:51:28 PM PDT 24
Finished Jul 31 07:03:26 PM PDT 24
Peak memory 201468 kb
Host smart-a1e8473c-f8f1-42c5-9ef2-f2584975b6d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571927795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2571927795
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.993819980
Short name T112
Test name
Test status
Simulation time 552900179799 ps
CPU time 1272.97 seconds
Started Jul 31 06:51:35 PM PDT 24
Finished Jul 31 07:12:49 PM PDT 24
Peak memory 201476 kb
Host smart-5362b35f-5880-4ea3-93ad-b5f0a2c1135b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993819980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.993819980
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2408333272
Short name T660
Test name
Test status
Simulation time 406933766608 ps
CPU time 953.81 seconds
Started Jul 31 06:51:37 PM PDT 24
Finished Jul 31 07:07:31 PM PDT 24
Peak memory 201468 kb
Host smart-fc48b4aa-a7da-4697-a549-46bd34de759f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408333272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2408333272
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2977314084
Short name T214
Test name
Test status
Simulation time 120942246125 ps
CPU time 419.29 seconds
Started Jul 31 06:51:40 PM PDT 24
Finished Jul 31 06:58:39 PM PDT 24
Peak memory 201772 kb
Host smart-22831973-f490-47bf-bea0-604cd8faf5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977314084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2977314084
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.4152403308
Short name T404
Test name
Test status
Simulation time 45301382197 ps
CPU time 52.18 seconds
Started Jul 31 06:51:39 PM PDT 24
Finished Jul 31 06:52:31 PM PDT 24
Peak memory 201388 kb
Host smart-8375a93d-a534-4459-92be-899eb6ec2191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152403308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.4152403308
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2684515285
Short name T729
Test name
Test status
Simulation time 3806847613 ps
CPU time 4.7 seconds
Started Jul 31 06:51:40 PM PDT 24
Finished Jul 31 06:51:44 PM PDT 24
Peak memory 201344 kb
Host smart-3aeec7f9-5110-4b6a-b50e-1aa5ed162ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684515285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2684515285
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2644542300
Short name T435
Test name
Test status
Simulation time 5950318070 ps
CPU time 5.96 seconds
Started Jul 31 06:51:28 PM PDT 24
Finished Jul 31 06:51:34 PM PDT 24
Peak memory 201356 kb
Host smart-2138f6c4-92ab-4c44-896a-6dada6386cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644542300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2644542300
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1782990914
Short name T196
Test name
Test status
Simulation time 505226893995 ps
CPU time 932.33 seconds
Started Jul 31 06:51:45 PM PDT 24
Finished Jul 31 07:07:17 PM PDT 24
Peak memory 201752 kb
Host smart-2060ebe6-1573-4bfa-bbf6-94826df7ed14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782990914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1782990914
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.298191956
Short name T55
Test name
Test status
Simulation time 34721159453 ps
CPU time 108.91 seconds
Started Jul 31 06:51:46 PM PDT 24
Finished Jul 31 06:53:35 PM PDT 24
Peak memory 210156 kb
Host smart-5d9f8db6-719f-4f50-8e41-0c883abc803b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298191956 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.298191956
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3573864745
Short name T667
Test name
Test status
Simulation time 377070447 ps
CPU time 1.5 seconds
Started Jul 31 06:52:09 PM PDT 24
Finished Jul 31 06:52:11 PM PDT 24
Peak memory 201272 kb
Host smart-a9d27be6-b982-4bf3-b63f-b6cc8c66c4e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573864745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3573864745
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3308461625
Short name T639
Test name
Test status
Simulation time 512821666166 ps
CPU time 185.16 seconds
Started Jul 31 06:51:58 PM PDT 24
Finished Jul 31 06:55:03 PM PDT 24
Peak memory 201452 kb
Host smart-8f84d44b-d997-45b4-9a65-b7dfdfac5bc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308461625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3308461625
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.650601471
Short name T29
Test name
Test status
Simulation time 164192250248 ps
CPU time 59.72 seconds
Started Jul 31 06:51:51 PM PDT 24
Finished Jul 31 06:52:51 PM PDT 24
Peak memory 201452 kb
Host smart-2af6d9fb-3887-4f9e-aeb1-969cc696b610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650601471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.650601471
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1819336164
Short name T629
Test name
Test status
Simulation time 331862344138 ps
CPU time 174.61 seconds
Started Jul 31 06:51:58 PM PDT 24
Finished Jul 31 06:54:53 PM PDT 24
Peak memory 201368 kb
Host smart-19986d1c-ae10-442e-809a-6473ccfbc3a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819336164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1819336164
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4274414163
Short name T476
Test name
Test status
Simulation time 166121093251 ps
CPU time 99.38 seconds
Started Jul 31 06:51:50 PM PDT 24
Finished Jul 31 06:53:30 PM PDT 24
Peak memory 201516 kb
Host smart-e5ddcff1-6569-4c8d-a299-f86744f6fc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274414163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4274414163
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1816842356
Short name T478
Test name
Test status
Simulation time 161724267502 ps
CPU time 381.1 seconds
Started Jul 31 06:51:52 PM PDT 24
Finished Jul 31 06:58:13 PM PDT 24
Peak memory 201492 kb
Host smart-2dd15311-9d86-473b-b080-f8c07256f109
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816842356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1816842356
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.799966802
Short name T716
Test name
Test status
Simulation time 354723390973 ps
CPU time 206.23 seconds
Started Jul 31 06:51:57 PM PDT 24
Finished Jul 31 06:55:23 PM PDT 24
Peak memory 201456 kb
Host smart-ca5d2dc3-26d8-442f-a92e-b9013e2a1931
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799966802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.799966802
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1443698509
Short name T173
Test name
Test status
Simulation time 603429994614 ps
CPU time 111.85 seconds
Started Jul 31 06:51:58 PM PDT 24
Finished Jul 31 06:53:50 PM PDT 24
Peak memory 201464 kb
Host smart-538f3769-0985-428a-a255-4078c22f44d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443698509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1443698509
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1659871986
Short name T469
Test name
Test status
Simulation time 67738290652 ps
CPU time 275.71 seconds
Started Jul 31 06:52:04 PM PDT 24
Finished Jul 31 06:56:39 PM PDT 24
Peak memory 201804 kb
Host smart-44db50a3-8973-4ef0-9009-85695aa7027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659871986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1659871986
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2848182742
Short name T610
Test name
Test status
Simulation time 30392320408 ps
CPU time 19 seconds
Started Jul 31 06:52:05 PM PDT 24
Finished Jul 31 06:52:24 PM PDT 24
Peak memory 201360 kb
Host smart-b7966a53-2a6e-4b93-a045-69670704c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848182742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2848182742
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1759524954
Short name T739
Test name
Test status
Simulation time 4860016532 ps
CPU time 3.64 seconds
Started Jul 31 06:52:04 PM PDT 24
Finished Jul 31 06:52:08 PM PDT 24
Peak memory 201360 kb
Host smart-1c3f7b63-29c8-4bae-8ce8-053fcc51b4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759524954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1759524954
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3846923410
Short name T692
Test name
Test status
Simulation time 5683035844 ps
CPU time 3.58 seconds
Started Jul 31 06:51:45 PM PDT 24
Finished Jul 31 06:51:48 PM PDT 24
Peak memory 201364 kb
Host smart-bce1d153-0d0e-44ff-ae5c-35a6d6de2b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846923410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3846923410
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.196161315
Short name T338
Test name
Test status
Simulation time 164595631709 ps
CPU time 394.99 seconds
Started Jul 31 06:52:06 PM PDT 24
Finished Jul 31 06:58:42 PM PDT 24
Peak memory 201444 kb
Host smart-425b8123-787e-4664-82d4-ffcc709e7abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196161315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
196161315
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1434324017
Short name T105
Test name
Test status
Simulation time 99996132605 ps
CPU time 59.2 seconds
Started Jul 31 06:52:03 PM PDT 24
Finished Jul 31 06:53:02 PM PDT 24
Peak memory 209776 kb
Host smart-a8240193-0a52-415d-b883-e0318f86d3f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434324017 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1434324017
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.360166054
Short name T86
Test name
Test status
Simulation time 444848222 ps
CPU time 0.97 seconds
Started Jul 31 06:52:28 PM PDT 24
Finished Jul 31 06:52:30 PM PDT 24
Peak memory 201160 kb
Host smart-d351ff49-eba0-4cd6-b1d7-4d375299bfe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360166054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.360166054
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3090578574
Short name T266
Test name
Test status
Simulation time 164656210841 ps
CPU time 407.36 seconds
Started Jul 31 06:52:16 PM PDT 24
Finished Jul 31 06:59:04 PM PDT 24
Peak memory 201452 kb
Host smart-1197ddd6-199f-4a6c-ad40-1d132c87218a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090578574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3090578574
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3002351197
Short name T636
Test name
Test status
Simulation time 327628522536 ps
CPU time 400.15 seconds
Started Jul 31 06:52:09 PM PDT 24
Finished Jul 31 06:58:49 PM PDT 24
Peak memory 201464 kb
Host smart-7ad35341-ec8d-44bf-8b6e-e49a4b04a526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002351197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3002351197
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2763459057
Short name T401
Test name
Test status
Simulation time 160361598478 ps
CPU time 366.61 seconds
Started Jul 31 06:52:10 PM PDT 24
Finished Jul 31 06:58:16 PM PDT 24
Peak memory 201532 kb
Host smart-78703f72-2d48-4f19-86c5-b4d2b8e88fde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763459057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2763459057
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.4062148324
Short name T490
Test name
Test status
Simulation time 163667907091 ps
CPU time 365.78 seconds
Started Jul 31 06:52:09 PM PDT 24
Finished Jul 31 06:58:15 PM PDT 24
Peak memory 201464 kb
Host smart-144e5e16-fa16-475f-b5c1-c54efe8efb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062148324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.4062148324
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2082941857
Short name T419
Test name
Test status
Simulation time 328798249589 ps
CPU time 176.64 seconds
Started Jul 31 06:52:09 PM PDT 24
Finished Jul 31 06:55:06 PM PDT 24
Peak memory 201388 kb
Host smart-628e33b3-2329-471b-a6d9-fb08fc6b8c74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082941857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2082941857
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2375558281
Short name T550
Test name
Test status
Simulation time 170279228471 ps
CPU time 361.69 seconds
Started Jul 31 06:52:09 PM PDT 24
Finished Jul 31 06:58:10 PM PDT 24
Peak memory 201540 kb
Host smart-73b9e344-fe24-4df1-9f49-b3745c5f713b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375558281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2375558281
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.709393784
Short name T542
Test name
Test status
Simulation time 614218749474 ps
CPU time 665.64 seconds
Started Jul 31 06:52:16 PM PDT 24
Finished Jul 31 07:03:22 PM PDT 24
Peak memory 201460 kb
Host smart-ea136799-dcad-460a-9387-5770b6e44794
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709393784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.709393784
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2754777987
Short name T26
Test name
Test status
Simulation time 97853871845 ps
CPU time 328.14 seconds
Started Jul 31 06:52:29 PM PDT 24
Finished Jul 31 06:57:58 PM PDT 24
Peak memory 201908 kb
Host smart-0ceb0e85-23be-47e8-89b9-67653e985bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754777987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2754777987
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.306587995
Short name T725
Test name
Test status
Simulation time 27294563914 ps
CPU time 12.35 seconds
Started Jul 31 06:52:29 PM PDT 24
Finished Jul 31 06:52:41 PM PDT 24
Peak memory 201368 kb
Host smart-d99fa263-0ade-4d8d-8693-0b85d201d197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306587995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.306587995
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1922507574
Short name T690
Test name
Test status
Simulation time 5247482447 ps
CPU time 6.48 seconds
Started Jul 31 06:52:22 PM PDT 24
Finished Jul 31 06:52:28 PM PDT 24
Peak memory 201316 kb
Host smart-d1a8dc68-0c62-478c-bfda-61e07e1fa60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922507574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1922507574
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.7724258
Short name T183
Test name
Test status
Simulation time 5885876527 ps
CPU time 4.61 seconds
Started Jul 31 06:52:13 PM PDT 24
Finished Jul 31 06:52:18 PM PDT 24
Peak memory 201352 kb
Host smart-d816d593-6c5f-42bb-903f-5e1b75e8bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7724258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.7724258
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4184150492
Short name T24
Test name
Test status
Simulation time 93328438463 ps
CPU time 173.29 seconds
Started Jul 31 06:52:29 PM PDT 24
Finished Jul 31 06:55:22 PM PDT 24
Peak memory 212672 kb
Host smart-d1530eb8-0043-4923-a75d-269753db2a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184150492 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.4184150492
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1593371543
Short name T540
Test name
Test status
Simulation time 396074591 ps
CPU time 1.5 seconds
Started Jul 31 06:52:45 PM PDT 24
Finished Jul 31 06:52:46 PM PDT 24
Peak memory 201268 kb
Host smart-5e0a2620-db43-474f-8bdd-44a821e9d365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593371543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1593371543
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3207013554
Short name T263
Test name
Test status
Simulation time 502537484302 ps
CPU time 294.31 seconds
Started Jul 31 06:52:34 PM PDT 24
Finished Jul 31 06:57:28 PM PDT 24
Peak memory 201484 kb
Host smart-375ee4a0-5d3d-4c01-bf40-bfda8205dfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207013554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3207013554
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3732977923
Short name T508
Test name
Test status
Simulation time 165356879359 ps
CPU time 89.8 seconds
Started Jul 31 06:52:34 PM PDT 24
Finished Jul 31 06:54:04 PM PDT 24
Peak memory 201464 kb
Host smart-c84bc39b-d811-42e1-89ce-40d6e8be1389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732977923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3732977923
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3675394689
Short name T599
Test name
Test status
Simulation time 165061143473 ps
CPU time 88.3 seconds
Started Jul 31 06:52:32 PM PDT 24
Finished Jul 31 06:54:00 PM PDT 24
Peak memory 201432 kb
Host smart-4d43f6cb-719a-47ed-9417-d16dd857688b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675394689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3675394689
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1476574764
Short name T260
Test name
Test status
Simulation time 495109622821 ps
CPU time 1175.03 seconds
Started Jul 31 06:52:30 PM PDT 24
Finished Jul 31 07:12:06 PM PDT 24
Peak memory 201452 kb
Host smart-d5b60ea2-7fac-4b14-ad57-c9b13af616dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476574764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1476574764
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1612996488
Short name T449
Test name
Test status
Simulation time 158169904077 ps
CPU time 63.49 seconds
Started Jul 31 06:52:29 PM PDT 24
Finished Jul 31 06:53:33 PM PDT 24
Peak memory 201456 kb
Host smart-1c319c37-bebd-4bfb-8c6a-fed977a4de9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612996488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1612996488
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.761668041
Short name T95
Test name
Test status
Simulation time 208035055980 ps
CPU time 471.31 seconds
Started Jul 31 06:52:33 PM PDT 24
Finished Jul 31 07:00:24 PM PDT 24
Peak memory 201476 kb
Host smart-48e71e4e-e4ee-46bc-8526-e01ddb2717ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761668041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.761668041
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4174104677
Short name T350
Test name
Test status
Simulation time 107985956525 ps
CPU time 336.09 seconds
Started Jul 31 06:52:39 PM PDT 24
Finished Jul 31 06:58:15 PM PDT 24
Peak memory 201772 kb
Host smart-828e6172-e6d8-44eb-a938-b55f91003d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174104677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4174104677
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1079070419
Short name T700
Test name
Test status
Simulation time 22297510390 ps
CPU time 24.54 seconds
Started Jul 31 06:52:40 PM PDT 24
Finished Jul 31 06:53:04 PM PDT 24
Peak memory 201372 kb
Host smart-87679dad-c375-4e00-9078-f39ee3dd2c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079070419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1079070419
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.519896162
Short name T122
Test name
Test status
Simulation time 4457094122 ps
CPU time 5.97 seconds
Started Jul 31 06:52:36 PM PDT 24
Finished Jul 31 06:52:42 PM PDT 24
Peak memory 201332 kb
Host smart-6a4a54e7-d177-4207-9a59-3f5674b8b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519896162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.519896162
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2571621412
Short name T535
Test name
Test status
Simulation time 6211079964 ps
CPU time 2.84 seconds
Started Jul 31 06:52:28 PM PDT 24
Finished Jul 31 06:52:31 PM PDT 24
Peak memory 201412 kb
Host smart-42d2b373-83bb-4519-93fa-f69d34123c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571621412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2571621412
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3836965061
Short name T648
Test name
Test status
Simulation time 174740537432 ps
CPU time 93.72 seconds
Started Jul 31 06:52:47 PM PDT 24
Finished Jul 31 06:54:21 PM PDT 24
Peak memory 201428 kb
Host smart-b11bddc4-455f-401b-8362-13dd1fa7acfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836965061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3836965061
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2709356971
Short name T39
Test name
Test status
Simulation time 160328181677 ps
CPU time 139.55 seconds
Started Jul 31 06:52:40 PM PDT 24
Finished Jul 31 06:54:59 PM PDT 24
Peak memory 212700 kb
Host smart-65bce575-4969-43a4-b755-e4d3188f02d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709356971 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2709356971
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3423983096
Short name T763
Test name
Test status
Simulation time 362858749 ps
CPU time 1.36 seconds
Started Jul 31 06:52:56 PM PDT 24
Finished Jul 31 06:52:58 PM PDT 24
Peak memory 201276 kb
Host smart-2fe5cd90-6ff7-49e5-84da-cd78c6970708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423983096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3423983096
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3867362416
Short name T194
Test name
Test status
Simulation time 352462194547 ps
CPU time 60.21 seconds
Started Jul 31 06:52:52 PM PDT 24
Finished Jul 31 06:53:52 PM PDT 24
Peak memory 201408 kb
Host smart-2de94fba-d782-4497-bd88-3519cac73ea7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867362416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3867362416
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3124565655
Short name T233
Test name
Test status
Simulation time 526031150228 ps
CPU time 629.88 seconds
Started Jul 31 06:52:50 PM PDT 24
Finished Jul 31 07:03:20 PM PDT 24
Peak memory 201528 kb
Host smart-22edf649-5268-4a47-b8b8-fa18b10c94be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124565655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3124565655
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1030338377
Short name T328
Test name
Test status
Simulation time 324108975823 ps
CPU time 758.45 seconds
Started Jul 31 06:52:47 PM PDT 24
Finished Jul 31 07:05:26 PM PDT 24
Peak memory 201504 kb
Host smart-3b3b0eda-352a-405e-aa47-843fd07d8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030338377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1030338377
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2895646215
Short name T422
Test name
Test status
Simulation time 164610851708 ps
CPU time 373.08 seconds
Started Jul 31 06:52:44 PM PDT 24
Finished Jul 31 06:58:57 PM PDT 24
Peak memory 201468 kb
Host smart-d5ab7a8e-612f-4d23-8755-46b3efc75c16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895646215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2895646215
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2346588599
Short name T634
Test name
Test status
Simulation time 326818009971 ps
CPU time 187.88 seconds
Started Jul 31 06:52:48 PM PDT 24
Finished Jul 31 06:55:56 PM PDT 24
Peak memory 201464 kb
Host smart-8fce7304-403f-41f9-bbce-39f0dced3b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346588599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2346588599
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1685650848
Short name T473
Test name
Test status
Simulation time 164784773824 ps
CPU time 185.06 seconds
Started Jul 31 06:52:45 PM PDT 24
Finished Jul 31 06:55:50 PM PDT 24
Peak memory 201424 kb
Host smart-20ab2d30-2141-4906-abe2-c2cf84e82238
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685650848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1685650848
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2330321933
Short name T254
Test name
Test status
Simulation time 539154303019 ps
CPU time 1157.13 seconds
Started Jul 31 06:52:50 PM PDT 24
Finished Jul 31 07:12:08 PM PDT 24
Peak memory 201448 kb
Host smart-9c8a0b34-cb63-4a0f-bb9d-5c0e0183efaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330321933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2330321933
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2910905335
Short name T594
Test name
Test status
Simulation time 194561507627 ps
CPU time 111.17 seconds
Started Jul 31 06:52:52 PM PDT 24
Finished Jul 31 06:54:43 PM PDT 24
Peak memory 201408 kb
Host smart-2f761a32-7a38-4f1b-895d-4be5a3248814
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910905335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2910905335
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3528773131
Short name T765
Test name
Test status
Simulation time 85506091726 ps
CPU time 387.15 seconds
Started Jul 31 06:52:50 PM PDT 24
Finished Jul 31 06:59:17 PM PDT 24
Peak memory 201904 kb
Host smart-c49d7f6a-d46a-4aed-b6d0-d5c7aee6d901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528773131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3528773131
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3950358766
Short name T383
Test name
Test status
Simulation time 22811067826 ps
CPU time 13.33 seconds
Started Jul 31 06:52:50 PM PDT 24
Finished Jul 31 06:53:04 PM PDT 24
Peak memory 201340 kb
Host smart-228ca1b5-dede-4911-9978-f74789af9fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950358766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3950358766
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.891535225
Short name T698
Test name
Test status
Simulation time 3115100536 ps
CPU time 4.42 seconds
Started Jul 31 06:52:49 PM PDT 24
Finished Jul 31 06:52:54 PM PDT 24
Peak memory 201384 kb
Host smart-c3d7cc5f-6612-405b-9223-0c43cdeca847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891535225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.891535225
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4214482928
Short name T197
Test name
Test status
Simulation time 6038758046 ps
CPU time 15.95 seconds
Started Jul 31 06:52:46 PM PDT 24
Finished Jul 31 06:53:02 PM PDT 24
Peak memory 201388 kb
Host smart-bbd707a7-7e97-40dc-8fbc-703acf5d8959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214482928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4214482928
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3090926662
Short name T240
Test name
Test status
Simulation time 178180434980 ps
CPU time 20.89 seconds
Started Jul 31 06:52:52 PM PDT 24
Finished Jul 31 06:53:13 PM PDT 24
Peak memory 201448 kb
Host smart-82fc6792-58e8-443a-a572-6243763b7da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090926662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3090926662
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3652907024
Short name T25
Test name
Test status
Simulation time 55123774995 ps
CPU time 198.45 seconds
Started Jul 31 06:52:52 PM PDT 24
Finished Jul 31 06:56:10 PM PDT 24
Peak memory 210128 kb
Host smart-92dd4de3-0287-45e4-a744-c1e3c38bb7d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652907024 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3652907024
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2209712914
Short name T438
Test name
Test status
Simulation time 336515978 ps
CPU time 1.4 seconds
Started Jul 31 06:38:37 PM PDT 24
Finished Jul 31 06:38:39 PM PDT 24
Peak memory 201256 kb
Host smart-f07308f4-33bf-453e-956e-170c59821ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209712914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2209712914
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2857603323
Short name T204
Test name
Test status
Simulation time 514463015242 ps
CPU time 118.87 seconds
Started Jul 31 06:38:34 PM PDT 24
Finished Jul 31 06:40:33 PM PDT 24
Peak memory 201472 kb
Host smart-771a0302-1834-4ebe-948a-5b4038ced742
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857603323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2857603323
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3475624774
Short name T191
Test name
Test status
Simulation time 485656243883 ps
CPU time 97.52 seconds
Started Jul 31 06:38:29 PM PDT 24
Finished Jul 31 06:40:06 PM PDT 24
Peak memory 201432 kb
Host smart-c834e859-9182-447e-a18f-e57ab6da9c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475624774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3475624774
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1869935872
Short name T444
Test name
Test status
Simulation time 162646416685 ps
CPU time 350.64 seconds
Started Jul 31 06:38:28 PM PDT 24
Finished Jul 31 06:44:19 PM PDT 24
Peak memory 201380 kb
Host smart-8bbd1a61-56b7-48cb-943a-cb1021360109
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869935872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1869935872
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1065364062
Short name T211
Test name
Test status
Simulation time 504391816577 ps
CPU time 291.56 seconds
Started Jul 31 06:38:30 PM PDT 24
Finished Jul 31 06:43:21 PM PDT 24
Peak memory 201460 kb
Host smart-c558f7af-9803-465a-aacd-21535e41e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065364062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1065364062
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2549355654
Short name T368
Test name
Test status
Simulation time 171575188832 ps
CPU time 381.22 seconds
Started Jul 31 06:38:29 PM PDT 24
Finished Jul 31 06:44:50 PM PDT 24
Peak memory 201420 kb
Host smart-0d407cc8-4f13-41c8-ba5f-940f79948a2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549355654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2549355654
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1073978190
Short name T98
Test name
Test status
Simulation time 191155625269 ps
CPU time 147.9 seconds
Started Jul 31 06:38:32 PM PDT 24
Finished Jul 31 06:41:00 PM PDT 24
Peak memory 201428 kb
Host smart-d46d3c7f-110d-420a-a13e-1e3b188b261a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073978190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1073978190
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.227029057
Short name T576
Test name
Test status
Simulation time 599568058908 ps
CPU time 1425.2 seconds
Started Jul 31 06:38:38 PM PDT 24
Finished Jul 31 07:02:23 PM PDT 24
Peak memory 201380 kb
Host smart-41f2f8fe-0cef-4898-a8b1-a11493ac07ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227029057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.227029057
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.558285592
Short name T353
Test name
Test status
Simulation time 69871173197 ps
CPU time 251.35 seconds
Started Jul 31 06:38:39 PM PDT 24
Finished Jul 31 06:42:50 PM PDT 24
Peak memory 201824 kb
Host smart-7aa0bf3d-e819-4b60-b76d-930e0f114681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558285592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.558285592
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1552989695
Short name T628
Test name
Test status
Simulation time 35857262300 ps
CPU time 8.04 seconds
Started Jul 31 06:38:34 PM PDT 24
Finished Jul 31 06:38:42 PM PDT 24
Peak memory 201328 kb
Host smart-78e3817d-2ffb-4235-b376-9c9e85dc64ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552989695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1552989695
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.926611155
Short name T616
Test name
Test status
Simulation time 3677290285 ps
CPU time 2.83 seconds
Started Jul 31 06:38:33 PM PDT 24
Finished Jul 31 06:38:36 PM PDT 24
Peak memory 201384 kb
Host smart-200fc465-af7c-45f8-a041-49edd1561b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926611155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.926611155
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2196016353
Short name T406
Test name
Test status
Simulation time 5793109240 ps
CPU time 2.82 seconds
Started Jul 31 06:38:32 PM PDT 24
Finished Jul 31 06:38:35 PM PDT 24
Peak memory 201432 kb
Host smart-84f248ab-ed5f-47f0-a3eb-f1d9b3fb1323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196016353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2196016353
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1483738291
Short name T732
Test name
Test status
Simulation time 495428168823 ps
CPU time 1131.66 seconds
Started Jul 31 06:38:39 PM PDT 24
Finished Jul 31 06:57:31 PM PDT 24
Peak memory 201512 kb
Host smart-e83890b4-1914-40c6-92e8-595811bdb10a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483738291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1483738291
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1770340610
Short name T18
Test name
Test status
Simulation time 420431095471 ps
CPU time 102.05 seconds
Started Jul 31 06:38:39 PM PDT 24
Finished Jul 31 06:40:21 PM PDT 24
Peak memory 209872 kb
Host smart-47447e1b-af13-47ab-bb98-dbc8bb299a98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770340610 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1770340610
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4226903433
Short name T361
Test name
Test status
Simulation time 363238810 ps
CPU time 1.37 seconds
Started Jul 31 06:38:54 PM PDT 24
Finished Jul 31 06:38:55 PM PDT 24
Peak memory 201252 kb
Host smart-936a1201-7702-4664-b1f9-6cbca819fca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226903433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4226903433
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.381069024
Short name T165
Test name
Test status
Simulation time 335862502138 ps
CPU time 311.35 seconds
Started Jul 31 06:38:43 PM PDT 24
Finished Jul 31 06:43:54 PM PDT 24
Peak memory 201452 kb
Host smart-5d343364-b33a-4bb1-bf70-1bf81de69db2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381069024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.381069024
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.565474315
Short name T118
Test name
Test status
Simulation time 163831885266 ps
CPU time 68.91 seconds
Started Jul 31 06:38:48 PM PDT 24
Finished Jul 31 06:39:57 PM PDT 24
Peak memory 201448 kb
Host smart-775a6876-abf7-4731-9a9e-e5bcfb75cc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565474315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.565474315
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2039048996
Short name T461
Test name
Test status
Simulation time 164242685354 ps
CPU time 32.17 seconds
Started Jul 31 06:38:48 PM PDT 24
Finished Jul 31 06:39:21 PM PDT 24
Peak memory 201512 kb
Host smart-ff352634-b64c-4b53-9b06-046604e08824
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039048996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2039048996
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.880292644
Short name T210
Test name
Test status
Simulation time 486797823698 ps
CPU time 130.84 seconds
Started Jul 31 06:38:42 PM PDT 24
Finished Jul 31 06:40:53 PM PDT 24
Peak memory 201420 kb
Host smart-8d9d9874-a4e6-4224-97b6-5454cf52b9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880292644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.880292644
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3882511477
Short name T200
Test name
Test status
Simulation time 166390844592 ps
CPU time 102.28 seconds
Started Jul 31 06:38:43 PM PDT 24
Finished Jul 31 06:40:26 PM PDT 24
Peak memory 201416 kb
Host smart-cbe05f5a-c011-4f39-b866-79406238d0a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882511477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3882511477
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3812583189
Short name T312
Test name
Test status
Simulation time 352034464455 ps
CPU time 786.88 seconds
Started Jul 31 06:38:44 PM PDT 24
Finished Jul 31 06:51:51 PM PDT 24
Peak memory 201496 kb
Host smart-2f78696c-d9d3-40ff-9f1b-5ae0397da962
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812583189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3812583189
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.807148582
Short name T388
Test name
Test status
Simulation time 595364732931 ps
CPU time 346.36 seconds
Started Jul 31 06:38:42 PM PDT 24
Finished Jul 31 06:44:29 PM PDT 24
Peak memory 201408 kb
Host smart-53768378-369d-40b5-a781-2e567875935f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807148582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.807148582
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1376985337
Short name T218
Test name
Test status
Simulation time 113256632318 ps
CPU time 377.22 seconds
Started Jul 31 06:38:54 PM PDT 24
Finished Jul 31 06:45:11 PM PDT 24
Peak memory 201876 kb
Host smart-85dbfc83-4933-4379-bce5-31a2affb9c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376985337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1376985337
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3638513345
Short name T434
Test name
Test status
Simulation time 40015410140 ps
CPU time 91.04 seconds
Started Jul 31 06:38:48 PM PDT 24
Finished Jul 31 06:40:19 PM PDT 24
Peak memory 201312 kb
Host smart-8713fd3e-1e78-4bce-8dc9-b2883ac1ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638513345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3638513345
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.110137371
Short name T492
Test name
Test status
Simulation time 3909113896 ps
CPU time 10.09 seconds
Started Jul 31 06:38:49 PM PDT 24
Finished Jul 31 06:38:59 PM PDT 24
Peak memory 201372 kb
Host smart-dc6f3a1f-bbe2-41ed-9c7e-72aaf8409638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110137371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.110137371
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2814970177
Short name T477
Test name
Test status
Simulation time 5687577440 ps
CPU time 1.57 seconds
Started Jul 31 06:38:38 PM PDT 24
Finished Jul 31 06:38:39 PM PDT 24
Peak memory 201380 kb
Host smart-9be974e0-1449-416b-ba2a-04fa2ce023ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814970177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2814970177
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3967734705
Short name T695
Test name
Test status
Simulation time 204371394352 ps
CPU time 131.09 seconds
Started Jul 31 06:38:53 PM PDT 24
Finished Jul 31 06:41:04 PM PDT 24
Peak memory 201488 kb
Host smart-830d1147-889f-46f6-bace-c814b2e11771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967734705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3967734705
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4093874278
Short name T331
Test name
Test status
Simulation time 197735387168 ps
CPU time 329.31 seconds
Started Jul 31 06:38:53 PM PDT 24
Finished Jul 31 06:44:22 PM PDT 24
Peak memory 217584 kb
Host smart-fb61603b-1168-44a4-ab21-c95a629d1217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093874278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4093874278
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2594751989
Short name T455
Test name
Test status
Simulation time 611979624 ps
CPU time 0.72 seconds
Started Jul 31 06:39:09 PM PDT 24
Finished Jul 31 06:39:10 PM PDT 24
Peak memory 201252 kb
Host smart-22f77da3-8c0d-4da5-a278-ea0c6790fa46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594751989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2594751989
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3714272162
Short name T311
Test name
Test status
Simulation time 179202770813 ps
CPU time 114.39 seconds
Started Jul 31 06:39:00 PM PDT 24
Finished Jul 31 06:40:54 PM PDT 24
Peak memory 201492 kb
Host smart-448f70d3-f103-468e-9080-41ee8af4ba72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714272162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3714272162
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1951833541
Short name T686
Test name
Test status
Simulation time 163391623380 ps
CPU time 28.94 seconds
Started Jul 31 06:38:57 PM PDT 24
Finished Jul 31 06:39:26 PM PDT 24
Peak memory 201480 kb
Host smart-86908c16-440d-48ea-9fc0-17b10810308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951833541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1951833541
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3141309259
Short name T188
Test name
Test status
Simulation time 157753914711 ps
CPU time 91.22 seconds
Started Jul 31 06:38:59 PM PDT 24
Finished Jul 31 06:40:31 PM PDT 24
Peak memory 201460 kb
Host smart-cf9f6602-f2ff-4e76-a97c-c792134cb101
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141309259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3141309259
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2035854980
Short name T597
Test name
Test status
Simulation time 162299963082 ps
CPU time 65.2 seconds
Started Jul 31 06:39:03 PM PDT 24
Finished Jul 31 06:40:08 PM PDT 24
Peak memory 201488 kb
Host smart-e64d415d-634e-496f-b7c1-e618b13483a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035854980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2035854980
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.579476621
Short name T651
Test name
Test status
Simulation time 169923028114 ps
CPU time 104.45 seconds
Started Jul 31 06:38:59 PM PDT 24
Finished Jul 31 06:40:43 PM PDT 24
Peak memory 201452 kb
Host smart-23d88883-e1a8-4e8a-9c7d-0771c6cc2feb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579476621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.579476621
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1874133996
Short name T730
Test name
Test status
Simulation time 398765153101 ps
CPU time 201.67 seconds
Started Jul 31 06:38:57 PM PDT 24
Finished Jul 31 06:42:19 PM PDT 24
Peak memory 201464 kb
Host smart-514f05ad-e8d5-4456-b7a5-f25d79cd1bef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874133996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1874133996
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1284735118
Short name T344
Test name
Test status
Simulation time 118378140039 ps
CPU time 438.17 seconds
Started Jul 31 06:39:03 PM PDT 24
Finished Jul 31 06:46:21 PM PDT 24
Peak memory 201860 kb
Host smart-c1f05d3b-bc77-41e7-884a-bfa46ec7ba68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284735118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1284735118
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1812296426
Short name T495
Test name
Test status
Simulation time 26630010013 ps
CPU time 56.73 seconds
Started Jul 31 06:39:03 PM PDT 24
Finished Jul 31 06:40:00 PM PDT 24
Peak memory 201360 kb
Host smart-a1d7a097-9787-4dca-ae9c-8be83354195b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812296426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1812296426
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.325088700
Short name T201
Test name
Test status
Simulation time 4245218705 ps
CPU time 3.32 seconds
Started Jul 31 06:39:00 PM PDT 24
Finished Jul 31 06:39:03 PM PDT 24
Peak memory 201336 kb
Host smart-883cd4ae-b00e-4c91-ba4f-342981138e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325088700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.325088700
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3051021252
Short name T494
Test name
Test status
Simulation time 5570708580 ps
CPU time 7.78 seconds
Started Jul 31 06:38:57 PM PDT 24
Finished Jul 31 06:39:05 PM PDT 24
Peak memory 201400 kb
Host smart-23d78973-c5ae-44d8-9b7b-0632bf187623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051021252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3051021252
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2643342154
Short name T308
Test name
Test status
Simulation time 172717370650 ps
CPU time 105.61 seconds
Started Jul 31 06:39:02 PM PDT 24
Finished Jul 31 06:40:48 PM PDT 24
Peak memory 201364 kb
Host smart-30f1860d-cb0d-4b9d-9563-97a56750e2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643342154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2643342154
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1393892390
Short name T20
Test name
Test status
Simulation time 42291009625 ps
CPU time 20.49 seconds
Started Jul 31 06:39:02 PM PDT 24
Finished Jul 31 06:39:23 PM PDT 24
Peak memory 209880 kb
Host smart-736c82c0-c2df-42b9-ad45-03131779d0d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393892390 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1393892390
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.669096991
Short name T570
Test name
Test status
Simulation time 437535541 ps
CPU time 0.85 seconds
Started Jul 31 06:39:19 PM PDT 24
Finished Jul 31 06:39:20 PM PDT 24
Peak memory 201220 kb
Host smart-13d482df-4145-4eb7-a9fa-8743e0299607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669096991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.669096991
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.521607513
Short name T190
Test name
Test status
Simulation time 160820682270 ps
CPU time 37.45 seconds
Started Jul 31 06:39:14 PM PDT 24
Finished Jul 31 06:39:51 PM PDT 24
Peak memory 201492 kb
Host smart-069d1e6c-3795-4e51-8060-a3076102d4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521607513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.521607513
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1877137932
Short name T307
Test name
Test status
Simulation time 491712440629 ps
CPU time 998.88 seconds
Started Jul 31 06:39:13 PM PDT 24
Finished Jul 31 06:55:52 PM PDT 24
Peak memory 201420 kb
Host smart-656b55a5-a0f3-4312-b0f0-c5b80e47e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877137932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1877137932
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4269533033
Short name T374
Test name
Test status
Simulation time 325952504091 ps
CPU time 202.76 seconds
Started Jul 31 06:39:14 PM PDT 24
Finished Jul 31 06:42:37 PM PDT 24
Peak memory 201504 kb
Host smart-24b2522c-be56-4d66-b2ea-68c8133462e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269533033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.4269533033
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3598235063
Short name T327
Test name
Test status
Simulation time 167586830896 ps
CPU time 417.03 seconds
Started Jul 31 06:39:14 PM PDT 24
Finished Jul 31 06:46:11 PM PDT 24
Peak memory 201448 kb
Host smart-e162221b-06b1-4a69-b99c-269e9085c819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598235063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3598235063
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.807613554
Short name T390
Test name
Test status
Simulation time 498217856252 ps
CPU time 541.38 seconds
Started Jul 31 06:39:16 PM PDT 24
Finished Jul 31 06:48:17 PM PDT 24
Peak memory 201444 kb
Host smart-482ee358-0425-455e-8c76-0aa2271148a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=807613554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.807613554
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.968370266
Short name T733
Test name
Test status
Simulation time 353020267732 ps
CPU time 206.62 seconds
Started Jul 31 06:39:16 PM PDT 24
Finished Jul 31 06:42:43 PM PDT 24
Peak memory 201500 kb
Host smart-27e729c9-332a-488e-b7e9-34517a4a0050
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968370266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.968370266
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3240681711
Short name T45
Test name
Test status
Simulation time 200300240576 ps
CPU time 238.96 seconds
Started Jul 31 06:39:15 PM PDT 24
Finished Jul 31 06:43:14 PM PDT 24
Peak memory 201460 kb
Host smart-5ea50988-fe01-4e96-b168-b591f566d14d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240681711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3240681711
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.963101161
Short name T440
Test name
Test status
Simulation time 68902733129 ps
CPU time 290.44 seconds
Started Jul 31 06:39:14 PM PDT 24
Finished Jul 31 06:44:04 PM PDT 24
Peak memory 201800 kb
Host smart-20dc2ac0-911f-4483-8222-4a4fdc2bd9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963101161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.963101161
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2345063835
Short name T524
Test name
Test status
Simulation time 33597229548 ps
CPU time 25.41 seconds
Started Jul 31 06:39:16 PM PDT 24
Finished Jul 31 06:39:42 PM PDT 24
Peak memory 201400 kb
Host smart-82a17c24-a984-4ee1-ab2a-3088b1d784ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345063835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2345063835
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2362542004
Short name T617
Test name
Test status
Simulation time 3916217735 ps
CPU time 9.08 seconds
Started Jul 31 06:39:14 PM PDT 24
Finished Jul 31 06:39:23 PM PDT 24
Peak memory 201332 kb
Host smart-c91b41c8-c67d-48a6-b229-822e8efb804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362542004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2362542004
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2376524085
Short name T445
Test name
Test status
Simulation time 5735578883 ps
CPU time 14.5 seconds
Started Jul 31 06:39:11 PM PDT 24
Finished Jul 31 06:39:25 PM PDT 24
Peak memory 201368 kb
Host smart-ec8ce09b-388c-4e39-b437-0a7eb49bcb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376524085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2376524085
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.483168881
Short name T480
Test name
Test status
Simulation time 13561664126 ps
CPU time 8.24 seconds
Started Jul 31 06:39:21 PM PDT 24
Finished Jul 31 06:39:29 PM PDT 24
Peak memory 201384 kb
Host smart-cccdd533-ab2a-4184-8e4b-1b77941c3b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483168881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.483168881
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.4140013988
Short name T305
Test name
Test status
Simulation time 188608125059 ps
CPU time 94.19 seconds
Started Jul 31 06:39:17 PM PDT 24
Finished Jul 31 06:40:51 PM PDT 24
Peak memory 209808 kb
Host smart-1627c99e-a02c-4b7a-93cb-83ae53d4f44b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140013988 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.4140013988
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.8162847
Short name T707
Test name
Test status
Simulation time 289497799 ps
CPU time 0.93 seconds
Started Jul 31 06:40:04 PM PDT 24
Finished Jul 31 06:40:05 PM PDT 24
Peak memory 201172 kb
Host smart-545c5945-9429-401e-8d34-1314d5d39bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8162847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.8162847
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1569546672
Short name T627
Test name
Test status
Simulation time 168611290542 ps
CPU time 274.49 seconds
Started Jul 31 06:39:54 PM PDT 24
Finished Jul 31 06:44:28 PM PDT 24
Peak memory 201404 kb
Host smart-702bd516-db09-42a0-991a-6da96bd19e54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569546672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1569546672
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.643341116
Short name T775
Test name
Test status
Simulation time 333257824422 ps
CPU time 401.22 seconds
Started Jul 31 06:39:41 PM PDT 24
Finished Jul 31 06:46:22 PM PDT 24
Peak memory 201448 kb
Host smart-e8cacd4e-0209-4d36-a22e-727ca6d2fe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643341116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.643341116
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4037898644
Short name T568
Test name
Test status
Simulation time 493149206515 ps
CPU time 306.88 seconds
Started Jul 31 06:39:41 PM PDT 24
Finished Jul 31 06:44:48 PM PDT 24
Peak memory 201448 kb
Host smart-e4754a9d-6099-468c-a03a-1d6499360960
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037898644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4037898644
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4231831965
Short name T264
Test name
Test status
Simulation time 174811708370 ps
CPU time 408.76 seconds
Started Jul 31 06:39:34 PM PDT 24
Finished Jul 31 06:46:23 PM PDT 24
Peak memory 201452 kb
Host smart-17cc6cb3-5d3f-4b27-acee-bd43304d3ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231831965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4231831965
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.897161683
Short name T632
Test name
Test status
Simulation time 493900748666 ps
CPU time 525.05 seconds
Started Jul 31 06:39:37 PM PDT 24
Finished Jul 31 06:48:22 PM PDT 24
Peak memory 201412 kb
Host smart-9bae91ce-077a-412f-9897-3ba93e51cf59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=897161683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.897161683
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1218616262
Short name T520
Test name
Test status
Simulation time 178221009293 ps
CPU time 71.81 seconds
Started Jul 31 06:39:45 PM PDT 24
Finished Jul 31 06:40:57 PM PDT 24
Peak memory 201448 kb
Host smart-f8e4ee94-878a-436e-8b68-5dd18021102e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218616262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1218616262
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2799031969
Short name T551
Test name
Test status
Simulation time 385425883352 ps
CPU time 818.82 seconds
Started Jul 31 06:39:46 PM PDT 24
Finished Jul 31 06:53:25 PM PDT 24
Peak memory 201448 kb
Host smart-c24ff1a5-d978-409b-aaf6-1ef3955bc936
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799031969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2799031969
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3041951816
Short name T680
Test name
Test status
Simulation time 110452509917 ps
CPU time 600.77 seconds
Started Jul 31 06:39:58 PM PDT 24
Finished Jul 31 06:49:59 PM PDT 24
Peak memory 201920 kb
Host smart-75ab7c2a-be91-4a1a-be19-7082b3d2ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041951816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3041951816
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1294586120
Short name T371
Test name
Test status
Simulation time 41303380403 ps
CPU time 19.74 seconds
Started Jul 31 06:39:57 PM PDT 24
Finished Jul 31 06:40:17 PM PDT 24
Peak memory 201296 kb
Host smart-b120fa37-4aed-41be-bfc7-ae94a8966353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294586120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1294586120
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.794441483
Short name T562
Test name
Test status
Simulation time 3774704030 ps
CPU time 2.87 seconds
Started Jul 31 06:39:57 PM PDT 24
Finished Jul 31 06:40:00 PM PDT 24
Peak memory 201356 kb
Host smart-d3d17d3c-2aa0-48cf-a53f-e2a547538379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794441483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.794441483
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2556906792
Short name T198
Test name
Test status
Simulation time 5691870688 ps
CPU time 13.3 seconds
Started Jul 31 06:39:35 PM PDT 24
Finished Jul 31 06:39:48 PM PDT 24
Peak memory 201388 kb
Host smart-e9e1c22b-758e-4560-ad77-58c942e1d195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556906792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2556906792
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.969942820
Short name T574
Test name
Test status
Simulation time 128536231651 ps
CPU time 338.69 seconds
Started Jul 31 06:40:03 PM PDT 24
Finished Jul 31 06:45:42 PM PDT 24
Peak memory 210760 kb
Host smart-b238be5d-b2f1-42a1-be6a-ae1eb6c2f2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969942820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.969942820
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2397461562
Short name T697
Test name
Test status
Simulation time 131254029990 ps
CPU time 45.78 seconds
Started Jul 31 06:40:02 PM PDT 24
Finished Jul 31 06:40:48 PM PDT 24
Peak memory 210140 kb
Host smart-ee1cedf7-9f3d-473b-b532-1cd0128485cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397461562 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2397461562
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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