Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7266	1			T1	16		T3	66		T4	20
testmodes[AdcCtrlTestmodeNormal]	5669	1			T1	22		T3	42		T5	122
testmodes[AdcCtrlTestmodeLowpower]	6051	1			T1	25		T2	2		T3	42
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3946	1			T1	4		T3	30		T4	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1813	1			T1	6		T3	16		T5	28
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1399	1			T1	6		T3	20		T5	29
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1816	1			T1	8		T3	15		T5	34
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2047	1			T1	7		T3	12		T5	55
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1457	1			T1	7		T3	15		T5	33
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1389	1			T1	4		T3	21		T5	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1475	1			T1	9		T3	13		T5	39
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2946	1			T1	11		T2	1		T3	7