Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23331

1

T1

64

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3982

1

T5

4

T58

2

T147

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20981

1

T1

64

T3

150

T4

20

auto[1]

6332

1

T2

18

T5

5

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T217	27		-	-		-	-
values[0]	40	1			T149	20		T218	1		T219	18
values[1]	601	1			T1	3		T57	7		T153	9
values[2]	782	1			T14	10		T58	1		T148	3
values[3]	772	1			T65	37		T157	36		T51	1
values[4]	2964	1			T2	18		T7	2		T9	30
values[5]	649	1			T147	2		T155	38		T48	12
values[6]	747	1			T12	14		T57	1		T64	25
values[7]	672	1			T5	5		T147	1		T176	21
values[8]	660	1			T58	1		T59	9		T157	1
values[9]	1369	1			T12	4		T148	11		T64	16
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	818	1			T1	3		T14	10		T57	7
values[1]	814	1			T58	1		T65	37		T153	3
values[2]	746	1			T157	12		T51	1		T151	3
values[3]	3022	1			T2	18		T7	2		T9	30
values[4]	613	1			T147	2		T161	1		T155	33
values[5]	691	1			T5	1		T12	14		T147	1
values[6]	717	1			T57	1		T58	1		T59	9
values[7]	618	1			T5	4		T64	16		T49	9
values[8]	1083	1			T12	4		T148	11		T65	16
values[9]	161	1			T74	8		T62	10		T26	9
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	2		T14	10		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T148	1		T153	9		T149	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T153	3		T162	17		T69	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T58	1		T65	22		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	11		T185	1		T36	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T157	1		T51	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	18		T7	2		T9	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T60	7		T221	14		T181	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T147	1		T161	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T147	1		T155	18		T48	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T12	10		T64	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T147	1		T99	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T57	1		T59	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T58	1		T176	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T64	10		T49	6		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	3		T177	1		T103	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	2		T148	1		T65	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T153	14		T156	18		T111	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T74	5		T170	10		T223	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T62	6		T26	9		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T57	6		T162	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T148	2		T149	11		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T162	5		T69	13		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T65	15		T157	12		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T152	11		T185	1		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T157	11		T151	2		T33	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T148	5		T174	9		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T60	2		T221	11		T181	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T16	1		T225	4		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T155	15		T48	3		T104	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	4		T64	10		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T183	2		T184	9		T226	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T59	8		T16	2		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T176	18		T227	17		T185	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T64	6		T49	3		T151	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T103	15		T111	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	2		T148	10		T65	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T156	17		T111	9		T104	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T74	3		T223	11		T23	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T62	4		T224	3		T228	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T217	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	9		T219	10		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	2		T57	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T153	9		T61	2		T229	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	10		T153	3		T162	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T58	1		T148	1		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T152	11		T185	1		T36	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T65	22		T157	13		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T2	18		T7	2		T9	30
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T151	1		T60	7		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T147	1		T155	1		T103	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T147	1		T155	18		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	10		T57	1		T64	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T158	1		T36	3		T104	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T206	2		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	3		T147	1		T176	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T59	1		T49	6		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T58	1		T157	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T12	2		T148	1		T64	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T153	14		T156	18		T62	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T217	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T149	11		T219	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T57	6		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T61	1		T226	10		T230	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T162	7		T69	13		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T148	2		T155	13		T151	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T152	11		T185	1		T167	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T65	15		T157	23		T33	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T148	5		T174	9		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T151	2		T60	2		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T155	4		T103	6		T31	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T155	15		T48	3		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	4		T64	10		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T104	2		T181	12		T183	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	2		T44	12		T232	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T176	18		T227	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T59	8		T49	3		T151	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T103	15		T111	8		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T12	2		T148	10		T64	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T156	17		T62	4		T111	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	3		T14	1		T57	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T148	3		T153	1		T149	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T153	1		T162	6		T69	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T58	1		T65	17		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T152	12		T185	2		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T157	12		T51	1		T151	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T2	2		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T60	4		T221	12		T181	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T147	1		T161	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T147	1		T155	16		T48	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T12	8		T64	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T147	1		T99	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	1		T59	9		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T58	1		T176	19		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T64	7		T49	5		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	3		T177	1		T103	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T12	4		T148	11		T65	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T153	1		T156	18		T111	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T74	4		T170	1		T223	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T62	7		T26	1		T224	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	9		T162	8		T146	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T153	8		T149	8		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T153	2		T162	16		T69	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T65	20		T157	11		T61	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T152	10		T36	12		T198	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T33	6		T17	1		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T2	16		T9	28		T13	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T60	5		T221	13		T181	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T110	5		T16	1		T170	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T155	17		T48	3		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	6		T64	14		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T184	2		T233	16		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T206	1		T26	6		T44	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T176	2		T227	14		T185	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T64	9		T49	4		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T103	17		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T65	8		T47	2		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T153	13		T156	17		T111	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T74	4		T170	9		T223	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T62	3		T26	8		T189	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T217	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T149	12		T219	9		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	3		T57	7		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T153	1		T61	2		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	1		T153	1		T162	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T58	1		T148	3		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T152	12		T185	2		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T65	17		T157	25		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T2	2		T7	2		T9	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T151	3		T60	4		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T147	1		T155	5		T103	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T147	1		T155	16		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	8		T57	1		T64	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T158	1		T36	1		T104	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T206	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	3		T147	1		T176	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T59	9		T49	5		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T58	1		T157	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T12	4		T148	11		T64	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T153	1		T156	18		T62	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T217	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T149	8		T219	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T146	16		T18	2		T189	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T153	8		T61	1		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	9		T153	2		T162	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T155	11		T61	4		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T152	10		T36	12		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T65	20		T157	11		T33	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T2	16		T9	28		T13	34
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T60	5		T17	1		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T103	11		T110	5		T195	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T155	17		T48	3		T231	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	6		T64	14		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	2		T181	15		T232	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T206	1		T44	2		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	1		T176	2		T227	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	4		T235	10		T103	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T103	17		T110	9		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T64	9		T65	8		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T153	13		T156	17		T62	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23465

1

T1

64

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3848

1

T5

5

T12

4

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21236

1

T1

61

T3

150

T4

20

auto[1]

6077

1

T1

3

T2

18

T5

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	316	1			T146	22		T150	1		T36	13
values[1]	573	1			T65	12		T161	1		T176	21
values[2]	787	1			T1	3		T65	16		T206	2
values[3]	714	1			T5	4		T64	16		T65	25
values[4]	659	1			T12	4		T57	1		T59	9
values[5]	3225	1			T2	18		T7	2		T9	30
values[6]	850	1			T148	6		T47	5		T149	20
values[7]	592	1			T14	10		T148	11		T153	3
values[8]	717	1			T57	7		T58	1		T147	1
values[9]	850	1			T5	1		T12	14		T58	1
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	532	1			T1	3		T65	12		T161	1
values[1]	720	1			T5	4		T65	16		T162	22
values[2]	755	1			T64	16		T65	25		T153	9
values[3]	3141	1			T2	18		T7	2		T9	30
values[4]	809	1			T147	1		T153	14		T149	16
values[5]	743	1			T148	17		T47	5		T69	29
values[6]	721	1			T14	10		T58	1		T153	3
values[7]	570	1			T57	7		T147	1		T154	1
values[8]	958	1			T5	1		T12	14		T58	1
values[9]	118	1			T192	1		T36	23		T38	1
minimum	18246	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	2		T65	8		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T176	3		T103	16		T111	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T206	2		T151	1		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	3		T65	9		T162	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T65	14		T220	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T64	10		T153	9		T155	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T2	18		T7	2		T9	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	2		T64	15		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T51	1		T62	6		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T147	1		T153	14		T149	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T148	2		T47	3		T157	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T69	16		T149	9		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T58	1		T153	3		T146	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	10		T157	1		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T57	1		T147	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T154	1		T49	6		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T12	10		T58	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	1		T148	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T182	1		T237	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T192	1		T36	23		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17960	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T16	4		T198	3		T239	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T1	1		T65	4		T155	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T176	18		T103	9		T111	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T151	3		T62	1		T240	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T65	7		T162	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T65	11		T241	4		T183	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T64	6		T155	15		T156	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T59	8		T174	9		T162	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	2		T64	10		T74	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T62	4		T43	15		T18	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T149	11		T32	16		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T148	15		T47	2		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T69	13		T149	11		T31	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T146	12		T155	13		T185	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T61	4		T16	1		T184	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T57	6		T177	9		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T49	3		T221	4		T242	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	4		T146	10		T33	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T148	2		T61	1		T242	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T237	13		T238	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T243	11		T244	11		T245	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T16	2		T198	3		T239	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T146	12		T246	1		T182	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T150	1		T36	13		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T65	8		T161	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T176	3		T103	16		T111	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	2		T206	2		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T65	9		T50	13		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T65	14		T220	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T5	3		T64	10		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T57	1		T59	1		T162	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	2		T64	15		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1730	1			T2	18		T7	2		T9	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T147	1		T153	14		T149	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T148	1		T47	3		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T149	9		T150	1		T26	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T148	1		T153	3		T146	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	10		T69	16		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T57	1		T58	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T154	1		T49	6		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	10		T58	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T148	1		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T146	10		T248	2		T249	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T243	6		T250	14		T251	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T65	4		T252	16		T253	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T176	18		T103	9		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T155	4		T240	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T65	7		T50	16		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T65	11		T151	3		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T64	6		T162	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T59	8		T162	2		T48	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	2		T64	10		T155	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T174	9		T254	12		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T149	11		T74	3		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T148	5		T47	2		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T149	11		T31	12		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T148	10		T146	12		T155	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T69	13		T16	1		T184	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T57	6		T151	2		T185	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T49	3		T61	4		T221	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	4		T177	9		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T148	2		T61	1		T242	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1