Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23674

1

T1

64

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3639

1

T5

5

T12

18

T57

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21383

1

T1

64

T3

150

T4

20

auto[1]

5930

1

T2

18

T5

4

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	340	1			T153	9		T150	1		T110	12
values[0]	45	1			T280	33		T201	11		T314	1
values[1]	779	1			T147	1		T64	16		T65	12
values[2]	660	1			T147	1		T148	6		T157	1
values[3]	464	1			T154	1		T220	1		T155	5
values[4]	841	1			T58	1		T49	9		T158	1
values[5]	2976	1			T2	18		T7	2		T9	30
values[6]	775	1			T14	10		T57	7		T162	33
values[7]	666	1			T12	4		T153	17		T146	22
values[8]	559	1			T5	4		T12	14		T59	9
values[9]	1178	1			T1	3		T5	1		T148	3
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	776	1			T147	1		T148	6		T64	16
values[1]	558	1			T147	1		T220	1		T155	5
values[2]	640	1			T154	1		T49	9		T61	9
values[3]	2973	1			T2	18		T7	2		T9	30
values[4]	721	1			T14	10		T57	1		T58	1
values[5]	679	1			T57	7		T162	11		T146	29
values[6]	726	1			T12	4		T59	9		T148	11
values[7]	594	1			T5	5		T12	14		T147	1
values[8]	1245	1			T1	3		T148	3		T65	16
values[9]	124	1			T206	2		T26	7		T315	1
minimum	18277	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T148	1		T64	10		T65	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T147	1		T157	1		T60	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T147	1		T155	1		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T220	1		T235	11		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	6		T167	6		T252	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T154	1		T61	5		T103	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T2	18		T7	2		T9	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T58	1		T158	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	10		T57	1		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	13		T62	2		T111	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T162	9		T146	17		T157	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T57	1		T149	5		T155	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T148	1		T162	17		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	2		T59	1		T153	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T69	16		T74	5		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	4		T12	10		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T1	2		T148	1		T65	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T153	9		T176	3		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T206	2		T26	7		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T182	1		T114	10		T278	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17992	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T288	1		T21	1		T302	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T148	5		T64	6		T65	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T60	2		T44	12		T104	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T155	4		T227	4		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T227	17		T31	7		T184	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T49	3		T167	9		T252	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T61	4		T103	15		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T174	9		T254	12		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T44	11		T19	1		T183	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T156	17		T103	9		T31	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T50	16		T62	1		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T162	2		T146	12		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T57	6		T149	11		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T148	10		T162	5		T43	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	2		T59	8		T146	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T69	13		T74	3		T185	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	1		T12	4		T64	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T1	1		T148	2		T65	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T176	18		T151	2		T185	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T223	11		T316	7		T317	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T114	3		T278	9		T309	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T288	10		T302	9		T280	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T150	1		T110	12		T26	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T153	9		T26	9		T32	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T280	17		T201	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T64	10		T65	8		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T147	1		T60	7		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	1		T148	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T157	1		T235	11		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T155	1		T33	10		T242	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T154	1		T220	1		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T49	6		T113	7		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T58	1		T158	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T2	18		T7	2		T9	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T50	13		T62	2		T111	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	10		T162	26		T146	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T57	1		T155	12		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T150	1		T61	2		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	2		T153	17		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T148	1		T69	16		T160	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	3		T12	10		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T1	2		T148	1		T65	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T5	1		T65	14		T47	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T169	9		T172	13		T223	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T32	16		T17	3		T18	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T280	16		T201	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T64	6		T65	4		T227	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T60	2		T167	5		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T148	5		T152	11		T62	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T227	17		T31	7		T44	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T155	4		T33	10		T242	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T61	4		T103	15		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T49	3		T113	2		T33	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T44	11		T19	1		T226	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T174	9		T156	17		T254	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	16		T62	1		T111	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T162	7		T146	12		T157	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T57	6		T155	13		T151	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T61	1		T43	6		T104	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	2		T146	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T148	10		T69	13		T185	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	1		T12	4		T59	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T148	2		T65	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T65	11		T47	2		T176	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T148	6		T64	7		T65	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T147	1		T157	1		T60	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T147	1		T155	5		T227	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T220	1		T235	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	5		T167	10		T252	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T154	1		T61	5		T103	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T2	2		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T58	1		T158	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T57	1		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	23		T62	2		T111	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T162	3		T146	13		T157	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T57	7		T149	12		T155	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T148	11		T162	6		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	4		T59	9		T153	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T69	14		T74	4		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	4		T12	8		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T1	3		T148	3		T65	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T153	1		T176	19		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T206	1		T26	1		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T182	1		T114	6		T278	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18100	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T288	11		T21	1		T302	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T64	9		T65	7		T62	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T60	5		T44	2		T104	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T152	10		T33	9		T242	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T235	10		T227	14		T36	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	4		T167	5		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T61	4		T103	17		T110	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T2	16		T9	28		T13	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T44	11		T184	10		T187	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	9		T156	17		T103	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T50	6		T62	1		T111	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T162	8		T146	16		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	4		T155	11		T33	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T162	16		T229	13		T233	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T153	15		T146	11		T111	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T69	15		T74	4		T160	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	1		T12	6		T64	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T65	8		T149	8		T110	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T153	8		T176	2		T185	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T206	1		T26	6		T223	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T114	7		T278	2		T275	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T103	11		T276	3		T273	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T302	11		T280	16		T189	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T150	1		T110	1		T26	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T153	1		T26	1		T32	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T280	17		T201	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T64	7		T65	5		T227	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T147	1		T60	4		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	1		T148	6		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T157	1		T235	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T155	5		T33	11		T242	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	1		T220	1		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T49	5		T113	3		T33	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T58	1		T158	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T2	2		T7	2		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T50	23		T62	2		T111	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	1		T162	9		T146	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T57	7		T155	14		T151	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T150	1		T61	2		T43	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	4		T153	2		T146	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T148	11		T69	14		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	3		T12	8		T59	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T1	3		T148	3		T65	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T5	1		T65	12		T47	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T110	11		T26	6		T169	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T153	8		T26	8		T32	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T280	16		T201	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T64	9		T65	7		T103	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T60	5		T226	9		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T152	10		T62	3		T171	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T235	10		T227	14		T36	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T33	9		T242	6		T23	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T61	4		T103	17		T111	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T49	4		T113	6		T33	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T110	9		T44	11		T305	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T2	16		T9	28		T13	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T50	6		T62	1		T111	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	9		T162	24		T146	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T155	11		T33	11		T36	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T61	1		T229	13		T233	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T153	15		T146	11		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T69	15		T160	12		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	1		T12	6		T64	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T65	8		T206	1		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T65	13		T47	2		T176	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28