Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23471

1

T1

64

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3842

1

T5

5

T12

18

T57

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21433

1

T1

64

T3

150

T4

20

auto[1]

5880

1

T2

18

T5

4

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	53	1			T169	18		T223	20		T317	6
values[0]	75	1			T167	6		T226	2		T224	23
values[1]	729	1			T147	1		T64	16		T65	12
values[2]	705	1			T147	1		T148	6		T157	1
values[3]	467	1			T154	1		T220	1		T155	5
values[4]	795	1			T58	1		T49	9		T158	1
values[5]	2938	1			T2	18		T7	2		T9	30
values[6]	779	1			T14	10		T57	7		T162	33
values[7]	711	1			T12	4		T153	17		T146	22
values[8]	595	1			T5	4		T12	14		T59	9
values[9]	1436	1			T1	3		T5	1		T148	3
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	993	1			T147	1		T148	6		T64	16
values[1]	583	1			T147	1		T220	1		T155	5
values[2]	635	1			T49	9		T61	9		T103	33
values[3]	2943	1			T2	18		T7	2		T9	30
values[4]	779	1			T14	10		T57	1		T58	1
values[5]	686	1			T57	7		T162	11		T146	29
values[6]	705	1			T12	4		T59	9		T148	11
values[7]	585	1			T5	5		T12	14		T147	1
values[8]	1215	1			T1	3		T148	3		T65	16
values[9]	148	1			T206	2		T51	1		T177	1
minimum	18041	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T148	1		T65	8		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T147	1		T64	10		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T147	1		T155	1		T152	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T220	1		T235	11		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T167	6		T252	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T49	6		T61	5		T103	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T2	18		T7	2		T9	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T58	1		T154	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	10		T57	1		T156	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T58	1		T50	13		T62	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T146	17		T155	12		T157	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T57	1		T162	9		T149	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T150	1		T43	1		T229	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	2		T59	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T69	16		T149	9		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	4		T12	10		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T1	2		T65	9		T176	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T148	1		T153	9		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T206	2		T51	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T17	3		T182	1		T279	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T288	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T148	5		T65	4		T227	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T64	6		T60	2		T62	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T155	4		T152	11		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T227	17		T31	7		T242	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T167	9		T252	16		T225	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T49	3		T61	4		T103	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T174	9		T254	12		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T44	11		T19	1		T183	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T156	17		T103	9		T31	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T50	16		T62	1		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	12		T155	13		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T57	6		T162	2		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T43	6		T318	4		T188	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	2		T59	8		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T69	13		T149	11		T185	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	1		T12	4		T64	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T65	7		T176	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T148	2		T52	1		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T172	13		T316	7		T294	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T17	3		T279	12		T114	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T288	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T169	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T223	9		T317	5		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T224	11		T280	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T167	1		T226	1		T201	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T65	8		T150	1		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T147	1		T64	10		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T147	1		T148	1		T152	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T157	1		T235	11		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T155	1		T225	1		T319	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T154	1		T220	1		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T152	1		T113	7		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T58	1		T49	6		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T2	18		T7	2		T9	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T58	1		T50	13		T62	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	10		T146	17		T155	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T57	1		T162	26		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T150	1		T43	1		T104	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	2		T153	17		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T69	16		T160	13		T185	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	3		T12	10		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T1	2		T65	9		T176	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	443	1			T5	1		T148	1		T65	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T169	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T223	11		T317	1		T291	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T224	12		T280	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T167	5		T226	1		T201	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T65	4		T227	4		T103	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T64	6		T168	10		T270	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T148	5		T152	11		T33	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T227	17		T60	2		T62	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T155	4		T225	4		T265	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T61	4		T103	15		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T113	2		T33	8		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T49	3		T19	1		T226	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T174	9		T156	17		T254	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	16		T62	1		T111	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	12		T155	13		T157	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T57	6		T162	7		T151	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T43	6		T104	2		T318	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	2		T146	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T69	13		T185	1		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T12	4		T59	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T65	7		T176	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T148	2		T65	11		T47	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T148	6		T65	5		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T147	1		T64	7		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T147	1		T155	5		T152	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T220	1		T235	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T167	10		T252	17		T225	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	5		T61	5		T103	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T2	2		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T58	1		T154	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	1		T57	1		T156	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T58	1		T50	23		T62	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T146	13		T155	14		T157	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T57	7		T162	3		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T150	1		T43	7		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	4		T59	9		T148	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T69	14		T149	12		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	4		T12	8		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	3		T65	8		T176	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T148	3		T153	1		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T206	1		T51	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T17	6		T182	1		T279	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T288	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T65	7		T103	11		T224	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T64	9		T60	5		T62	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T152	10		T33	9		T259	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T235	10		T227	14		T242	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T167	5		T117	12		T265	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	4		T61	4		T103	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	16		T9	28		T13	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T44	11		T230	13		T187	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	9		T156	17		T103	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	6		T62	1		T111	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T146	16		T155	11		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T162	8		T149	4		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T229	13		T233	16		T318	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T153	15		T162	16		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T69	15		T149	8		T160	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T12	6		T64	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T65	8		T176	2		T110	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T153	8		T52	1		T185	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T206	1		T172	14		T294	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T114	7		T317	1		T275	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T169	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T223	12		T317	5		T291	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T224	13		T280	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T167	6		T226	2		T201	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T65	5		T150	1		T227	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T147	1		T64	7		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T147	1		T148	6		T152	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T157	1		T235	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T155	5		T225	5		T319	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T154	1		T220	1		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T152	1		T113	3		T33	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T58	1		T49	5		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T2	2		T7	2		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T58	1		T50	23		T62	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	1		T146	13		T155	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T57	7		T162	9		T151	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T150	1		T43	7		T104	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	4		T153	2		T146	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T69	14		T160	1		T185	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	3		T12	8		T59	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T1	3		T65	8		T176	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T5	1		T148	3		T65	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T169	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T223	8		T317	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T224	10		T280	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T201	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T65	7		T103	11		T261	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T64	9		T230	10		T211	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T152	10		T33	9		T259	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T235	10		T227	14		T60	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T265	8		T23	1		T285	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T61	4		T103	17		T111	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T113	6		T33	6		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T49	4		T110	9		T230	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T2	16		T9	28		T13	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T50	6		T62	1		T111	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	9		T146	16		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T162	24		T33	11		T36	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T229	13		T233	3		T318	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T153	15		T146	11		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T69	15		T160	12		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	1		T12	6		T64	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T65	8		T176	2		T206	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T65	13		T153	8		T47	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28