Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23603

1

T1

64

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3710

1

T5

4

T12

14

T57

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21293

1

T1

61

T3

150

T4

20

auto[1]

6020

1

T1

3

T2

18

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	276	1			T5	4		T65	12		T50	29
values[0]	55	1			T290	1		T320	5		T321	14
values[1]	829	1			T57	7		T65	16		T153	14
values[2]	3025	1			T2	18		T7	2		T9	30
values[3]	423	1			T161	1		T162	11		T146	22
values[4]	703	1			T12	14		T58	1		T147	1
values[5]	955	1			T148	3		T64	25		T65	25
values[6]	688	1			T12	4		T235	11		T150	1
values[7]	707	1			T5	1		T58	1		T59	9
values[8]	834	1			T57	1		T147	1		T69	29
values[9]	788	1			T1	3		T14	10		T153	3
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T57	7		T65	16		T153	14
values[1]	2890	1			T2	18		T7	2		T9	30
values[2]	578	1			T148	6		T161	1		T146	22
values[3]	730	1			T12	14		T58	1		T147	1
values[4]	903	1			T12	4		T148	3		T64	25
values[5]	634	1			T5	1		T59	9		T47	5
values[6]	757	1			T58	1		T147	2		T148	11
values[7]	682	1			T1	3		T57	1		T69	29
values[8]	863	1			T5	4		T14	10		T65	12
values[9]	160	1			T50	29		T160	13		T110	10
minimum	18341	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T65	9		T153	14		T176	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T57	1		T151	1		T44	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T2	18		T7	2		T9	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T162	9		T157	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T148	1		T151	1		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T161	1		T146	12		T48	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T147	1		T155	18		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	10		T58	1		T64	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	2		T64	15		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T148	1		T65	14		T206	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T59	1		T47	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T150	1		T26	7		T36	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T58	1		T147	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T147	1		T148	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	2		T156	18		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T57	1		T69	16		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	10		T65	8		T153	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T5	3		T162	17		T103	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T231	5		T322	1		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T50	13		T160	13		T110	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17947	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T18	7		T286	13		T224	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T65	7		T176	18		T74	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T57	6		T151	3		T44	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T174	9		T254	12		T255	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T162	2		T227	4		T104	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T148	5		T151	5		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	10		T48	3		T157	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T155	15		T103	6		T62	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	4		T64	6		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	2		T64	10		T185	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T148	2		T65	11		T103	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T59	8		T47	2		T111	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T241	4		T198	4		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T146	12		T149	11		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	10		T184	10		T288	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T1	1		T156	17		T185	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T69	13		T155	4		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T65	4		T177	9		T113	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T162	5		T103	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T231	4		T277	9		T323	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T50	16		T31	5		T242	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T18	2		T286	15		T224	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T65	8		T262	1		T231	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	3		T50	13		T110	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T320	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T290	1		T321	14		T200	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T65	9		T153	14		T149	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T57	1		T151	1		T44	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1650	1			T2	18		T7	2		T9	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T157	1		T177	1		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	4		T104	6		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T161	1		T162	9		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T147	1		T148	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	10		T58	1		T64	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T64	15		T153	9		T155	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T148	1		T65	14		T206	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	2		T235	11		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T150	1		T26	7		T36	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T58	1		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T147	1		T148	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T147	1		T156	18		T185	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T57	1		T69	16		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	2		T14	10		T153	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T162	17		T52	2		T160	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T65	4		T231	2		T277	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	1		T50	16		T31	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T200	13		T324	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T65	7		T149	11		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T57	6		T151	3		T44	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T174	9		T176	18		T254	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T227	4		T104	2		T167	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T16	2		T104	4		T183	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T162	2		T146	10		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T148	5		T151	5		T103	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	4		T64	6		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T64	10		T155	15		T185	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T148	2		T65	11		T103	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	2		T325	2		T302	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T241	4		T183	2		T198	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T59	8		T47	2		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T148	10		T326	10		T195	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T156	17		T185	1		T43	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T69	13		T155	4		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T177	9		T113	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T162	5		T52	1		T103	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T65	8		T153	1		T176	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T57	7		T151	4		T44	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T2	2		T7	2		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T162	3		T157	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T148	6		T151	6		T16	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T161	1		T146	11		T48	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T147	1		T155	16		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	8		T58	1		T64	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	4		T64	11		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T148	3		T65	12		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T59	9		T47	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T150	1		T26	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T58	1		T147	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T147	1		T148	11		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	3		T156	18		T185	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T57	1		T69	14		T155	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	1		T65	5		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	3		T162	6		T103	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T231	9		T322	1		T277	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T50	23		T160	1		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18082	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	7		T286	16		T224	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T65	8		T153	13		T176	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T44	11		T184	2		T272	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T2	16		T9	28		T13	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T162	8		T167	10		T226	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T181	10		T169	10		T188	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T146	11		T48	3		T49	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T155	17		T103	11		T62	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	6		T64	9		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T64	14		T153	8		T185	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T65	13		T206	1		T101	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T47	2		T235	10		T111	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T26	6		T36	9		T198	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T146	16		T149	8		T36	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T179	6		T184	10		T170	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T156	17		T211	7		T273	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T69	15		T52	1		T111	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	9		T65	7		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	1		T162	16		T103	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T327	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T50	6		T160	12		T110	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T149	4		T155	11		T201	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T18	2		T286	12		T253	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T65	5		T262	1		T231	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	3		T50	23		T110	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T320	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T290	1		T321	1		T200	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T65	8		T153	1		T149	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T57	7		T151	4		T44	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T2	2		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T157	1		T177	1		T227	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T16	6		T104	9		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T161	1		T162	3		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T147	1		T148	6		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	8		T58	1		T64	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T64	11		T153	1		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T148	3		T65	12		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	4		T235	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	1		T26	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	1		T58	1		T59	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T147	1		T148	11		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T147	1		T156	18		T185	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T57	1		T69	14		T155	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	3		T14	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T162	6		T52	2		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T65	7		T231	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	1		T50	6		T110	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T320	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T321	13		T200	13		T328	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T65	8		T153	13		T149	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T44	11		T18	2		T286	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T2	16		T9	28		T13	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T167	10		T226	9		T120	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T104	1		T188	10		T276	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T162	8		T146	11		T49	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T103	11		T181	10		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	6		T64	9		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T64	14		T153	8		T155	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T65	13		T206	1		T101	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T235	10		T325	15		T234	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T26	6		T36	9		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T47	2		T146	16		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T179	6		T170	14		T276	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T156	17		T36	12		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T69	15		T111	8		T33	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	9		T153	2		T110	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T162	16		T52	1		T160	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28