Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21535

1

T1

61

T3

150

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5778

1

T1

3

T2

18

T5

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21213

1

T1

61

T3

150

T4

20

auto[1]

6100

1

T1

3

T2

18

T5

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	125	1			T57	1		T47	5		T159	1
values[0]	101	1			T227	32		T152	1		T279	13
values[1]	857	1			T12	14		T57	7		T65	25
values[2]	549	1			T65	12		T153	14		T146	29
values[3]	665	1			T147	1		T64	25		T153	3
values[4]	803	1			T5	1		T59	9		T147	1
values[5]	742	1			T148	3		T65	16		T162	33
values[6]	784	1			T5	4		T148	6		T153	9
values[7]	858	1			T58	1		T155	33		T51	1
values[8]	663	1			T1	3		T14	10		T147	1
values[9]	3136	1			T2	18		T7	2		T9	30
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T12	14		T57	7		T65	12
values[1]	2750	1			T2	18		T7	2		T9	30
values[2]	719	1			T147	1		T153	3		T176	21
values[3]	821	1			T5	1		T147	1		T148	3
values[4]	788	1			T59	9		T65	16		T162	33
values[5]	781	1			T5	4		T148	6		T153	9
values[6]	797	1			T1	3		T58	1		T147	1
values[7]	670	1			T14	10		T64	16		T154	1
values[8]	752	1			T12	4		T57	1		T58	1
values[9]	53	1			T47	5		T101	8		T111	17
minimum	18301	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T57	1		T65	8		T153	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	10		T154	1		T155	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T64	15		T146	17		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1567	1			T2	18		T7	2		T9	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T147	1		T176	3		T74	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T153	3		T157	13		T36	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T147	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T161	1		T220	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T59	1		T65	9		T162	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T162	9		T227	1		T111	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T148	1		T206	2		T156	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	3		T153	9		T155	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T58	1		T147	1		T61	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T1	2		T69	16		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T155	1		T49	6		T50	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	10		T64	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	2		T57	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T58	1		T26	7		T271	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T101	8		T20	1		T24	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T47	3		T111	9		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17978	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T227	15		T262	1		T187	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T57	6		T65	4		T62	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	4		T155	13		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T64	10		T146	12		T33	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	961	1			T174	9		T254	12		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T176	18		T74	3		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T157	12		T167	14		T181	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T148	2		T52	1		T113	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	11		T181	13		T198	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T59	8		T65	7		T162	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T162	2		T227	4		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T148	5		T156	17		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T155	15		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T61	4		T185	17		T104	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	1		T69	13		T103	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T155	4		T49	3		T50	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T64	6		T177	9		T33	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	2		T148	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T271	8		T252	16		T276	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T24	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T47	2		T111	8		T283	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T12	2		T65	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T227	17		T172	10		T329	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T57	1		T159	1		T232	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T47	3		T281	1		T330	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T152	1		T279	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T227	15		T187	11		T172	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T57	1		T65	14		T235	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	10		T154	1		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T65	8		T153	14		T146	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T151	1		T152	11		T103	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T147	1		T64	15		T176	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T153	3		T157	13		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	1		T59	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T161	1		T220	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T148	1		T65	9		T162	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T162	9		T111	9		T37	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T148	1		T206	2		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	3		T153	9		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T58	1		T61	5		T185	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T155	18		T51	1		T103	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T147	1		T155	1		T49	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	2		T14	10		T64	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	2		T148	1		T149	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1653	1			T2	18		T7	2		T9	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T232	2		T268	3		T331	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T47	2		T277	9		T332	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T227	17		T172	10		T284	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T57	6		T65	11		T61	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	4		T155	13		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T65	4		T146	12		T104	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T151	5		T152	11		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T64	10		T176	18		T74	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T157	12		T31	7		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T59	8		T52	1		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	11		T181	13		T198	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T148	2		T65	7		T162	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T162	2		T111	2		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T148	5		T146	10		T156	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T157	11		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T61	4		T185	17		T325	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T155	15		T103	15		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T155	4		T49	3		T104	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T64	6		T69	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	2		T148	10		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1003	1			T174	9		T254	12		T255	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T57	7		T65	5		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	8		T154	1		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T64	11		T146	13		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1287	1			T2	2		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T147	1		T176	19		T74	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T153	1		T157	14		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	1		T147	1		T148	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T161	1		T220	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T59	9		T65	8		T162	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T162	3		T227	5		T111	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T148	6		T206	1		T156	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	3		T153	1		T155	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T58	1		T147	1		T61	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T1	3		T69	14		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T155	5		T49	5		T50	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	1		T64	7		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	4		T57	1		T148	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T58	1		T26	1		T271	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T101	1		T20	1		T24	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T47	3		T111	9		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18090	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T227	18		T262	1		T187	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T65	7		T153	13		T235	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	6		T155	11		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T64	14		T146	16		T33	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1241	1			T2	16		T9	28		T13	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T176	2		T74	4		T60	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T153	2		T157	11		T36	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T52	1		T113	6		T26	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	11		T229	13		T181	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T65	8		T162	16		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T162	8		T111	8		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T206	1		T156	17		T110	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	1		T153	8		T155	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T61	4		T185	9		T110	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T69	15		T103	17		T33	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T49	4		T50	6		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	9		T64	9		T33	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	8		T48	3		T110	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	6		T271	8		T276	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T101	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T47	2		T111	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T65	13		T61	1		T18	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T227	14		T187	10		T172	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T57	1		T159	1		T232	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T47	3		T281	1		T330	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T152	1		T279	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T227	18		T187	1		T172	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T57	7		T65	12		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	8		T154	1		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T65	5		T153	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T151	6		T152	12		T103	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T147	1		T64	11		T176	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T153	1		T157	14		T31	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T59	9		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T161	1		T220	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T148	3		T65	8		T162	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T162	3		T111	3		T37	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T148	6		T206	1		T146	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	3		T153	1		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T58	1		T61	5		T185	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T155	16		T51	1		T103	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	1		T155	5		T49	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	3		T14	1		T64	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T12	4		T148	11		T149	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1357	1			T2	2		T7	2		T9	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T232	2		T273	13		T333	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T47	2		T332	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T227	14		T187	10		T172	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T65	13		T235	10		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	6		T155	11		T111	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T65	7		T153	13		T146	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	10		T103	15		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T64	14		T176	2		T74	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T153	2		T157	11		T36	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	1		T113	6		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T44	11		T229	13		T181	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T65	8		T162	16		T149	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T162	8		T111	8		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T206	1		T146	11		T156	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T5	1		T153	8		T167	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T61	4		T185	9		T110	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T155	17		T103	17		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	4		T104	1		T286	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	9		T64	9		T69	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T149	8		T48	3		T50	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1299	1			T2	16		T9	28		T13	34

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28