Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23569

1

T1

64

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3744

1

T5

4

T12

14

T57

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21302

1

T1

61

T3

150

T4

20

auto[1]

6011

1

T1

3

T2

18

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T110	10		T242	12		T231	7
values[0]	132	1			T227	32		T20	7		T290	1
values[1]	723	1			T57	7		T65	16		T153	14
values[2]	3016	1			T2	18		T7	2		T9	30
values[3]	468	1			T162	11		T146	22		T49	9
values[4]	717	1			T12	14		T58	1		T147	1
values[5]	879	1			T148	3		T64	25		T65	25
values[6]	784	1			T12	4		T149	20		T235	11
values[7]	571	1			T5	1		T57	1		T58	1
values[8]	879	1			T147	1		T69	29		T146	29
values[9]	1069	1			T1	3		T5	4		T14	10
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1058	1			T57	7		T65	16		T153	14
values[1]	2922	1			T2	18		T7	2		T9	30
values[2]	576	1			T148	6		T161	1		T146	22
values[3]	650	1			T12	14		T58	1		T147	1
values[4]	919	1			T12	4		T148	3		T64	25
values[5]	669	1			T5	1		T59	9		T150	2
values[6]	726	1			T58	1		T147	2		T148	11
values[7]	718	1			T57	1		T69	29		T155	5
values[8]	839	1			T1	3		T5	4		T14	10
values[9]	177	1			T50	29		T160	13		T62	3
minimum	18059	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T65	9		T153	14		T176	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T57	1		T151	1		T44	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1639	1			T2	18		T7	2		T9	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T162	9		T157	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T148	1		T151	1		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T161	1		T146	12		T48	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T147	1		T192	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	10		T58	1		T64	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	2		T153	9		T155	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T148	1		T64	15		T65	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T59	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T150	1		T26	7		T36	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T58	1		T147	1		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T147	1		T148	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T185	1		T43	1		T221	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T57	1		T69	16		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	2		T14	10		T65	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T5	3		T162	17		T103	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T231	5		T322	1		T323	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T50	13		T160	13		T62	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T183	1		T276	4		T334	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T65	7		T176	18		T149	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T57	6		T151	3		T44	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T174	9		T254	12		T255	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T162	2		T227	4		T104	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T148	5		T151	5		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	10		T48	3		T157	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T103	6		T185	17		T62	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	4		T64	6		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	2		T155	15		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T148	2		T64	10		T65	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T59	8		T111	9		T325	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T241	4		T198	4		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	2		T146	12		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	10		T288	10		T326	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T185	1		T43	6		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T69	13		T155	4		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T65	4		T177	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T162	5		T103	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T231	4		T323	7		T331	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T50	16		T62	1		T31	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T183	17		T334	6		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T231	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T110	10		T242	10		T335	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T227	15		T20	5		T320	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T290	1		T253	9		T321	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T65	9		T153	14		T149	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T57	1		T151	1		T44	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T2	18		T7	2		T9	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T161	1		T157	1		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T104	6		T186	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T162	9		T146	12		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T147	1		T148	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	10		T58	1		T64	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T153	9		T155	18		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T148	1		T64	15		T65	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	2		T149	9		T235	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T150	1		T26	7		T36	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	1		T58	1		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T57	1		T147	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T147	1		T146	17		T156	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T69	16		T155	1		T111	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	2		T14	10		T65	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T5	3		T162	17		T50	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T242	2		T335	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T227	17		T20	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T253	3		T200	13		T324	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T65	7		T149	11		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T57	6		T151	3		T44	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T174	9		T176	18		T74	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T227	4		T104	2		T167	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T104	4		T183	6		T188	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T162	2		T146	10		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T148	5		T151	5		T103	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	4		T64	6		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T155	15		T185	17		T62	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T148	2		T64	10		T65	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	2		T149	11		T325	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T241	4		T240	9		T183	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T59	8		T47	2		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T148	10		T326	10		T195	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	12		T156	17		T185	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T69	13		T155	4		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	1		T65	4		T177	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T162	5		T50	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T65	8		T153	1		T176	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T57	7		T151	4		T44	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	2		T7	2		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T162	3		T157	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T148	6		T151	6		T16	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T161	1		T146	11		T48	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T147	1		T192	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	8		T58	1		T64	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	4		T153	1		T155	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T148	3		T64	11		T65	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T59	9		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T150	1		T26	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T58	1		T147	1		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T147	1		T148	11		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T185	2		T43	7		T221	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T57	1		T69	14		T155	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	3		T14	1		T65	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	3		T162	6		T103	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T231	9		T322	1		T323	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T50	23		T160	1		T62	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T183	18		T276	1		T334	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T65	8		T153	13		T176	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	11		T18	2		T286	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T2	16		T9	28		T13	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T162	8		T167	10		T226	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T181	10		T169	10		T188	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T146	11		T48	3		T49	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T103	11		T185	9		T62	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	6		T64	9		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T153	8		T155	17		T235	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T64	14		T65	13		T206	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T111	10		T325	15		T234	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	6		T36	9		T198	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T47	2		T146	16		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T179	6		T170	14		T199	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T221	6		T273	18		T22	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T69	15		T52	1		T111	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	9		T65	7		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	1		T162	16		T103	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T336	2		T327	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T50	6		T160	12		T62	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T276	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T231	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T110	1		T242	3		T335	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T227	18		T20	6		T320	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T290	1		T253	9		T321	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T65	8		T153	1		T149	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T57	7		T151	4		T44	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T2	2		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T161	1		T157	1		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T104	9		T186	1		T183	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T162	3		T146	11		T49	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T147	1		T148	6		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	8		T58	1		T64	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	1		T155	16		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T148	3		T64	11		T65	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	4		T149	12		T235	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T150	1		T26	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T58	1		T59	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T57	1		T147	1		T148	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T147	1		T146	13		T156	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T69	14		T155	5		T111	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	3		T14	1		T65	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T5	3		T162	6		T50	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T231	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T110	9		T242	9		T335	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T227	14		T20	1		T320	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T253	3		T321	13		T200	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T65	8		T153	13		T149	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	11		T18	2		T286	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T2	16		T9	28		T13	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T226	9		T120	18		T265	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T104	1		T188	10		T276	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T162	8		T146	11		T49	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T103	11		T181	10		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	6		T64	9		T206	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T153	8		T155	17		T185	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T64	14		T65	13		T101	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T149	8		T235	10		T325	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	6		T36	9		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	2		T111	10		T318	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T170	14		T276	10		T199	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	16		T156	17		T36	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T69	15		T111	8		T33	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	9		T65	7		T153	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T5	1		T162	16		T50	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28