Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23425

1

T1

61

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3888

1

T1

3

T5

5

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20805

1

T1

57

T3

144

T4

20

auto[1]

6508

1

T1

7

T2

18

T3

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	865	1			T1	7		T3	6		T5	7
values[0]	44	1			T211	14		T200	18		T296	9
values[1]	595	1			T5	4		T148	6		T65	16
values[2]	2968	1			T2	18		T7	2		T9	30
values[3]	655	1			T153	3		T162	11		T156	35
values[4]	676	1			T148	11		T64	16		T65	12
values[5]	634	1			T57	8		T59	9		T147	1
values[6]	705	1			T157	13		T158	1		T16	6
values[7]	706	1			T14	10		T64	25		T176	21
values[8]	833	1			T5	1		T12	4		T65	25
values[9]	1089	1			T1	3		T58	1		T153	9
minimum	17543	1			T1	54		T3	144		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	650	1			T5	4		T148	6		T65	16
values[1]	2910	1			T2	18		T7	2		T9	30
values[2]	609	1			T153	3		T155	5		T50	29
values[3]	736	1			T57	1		T148	11		T64	16
values[4]	585	1			T57	7		T59	9		T147	1
values[5]	767	1			T157	12		T158	1		T61	3
values[6]	680	1			T14	10		T64	25		T176	21
values[7]	918	1			T5	1		T12	4		T65	25
values[8]	1043	1			T1	3		T12	14		T58	1
values[9]	161	1			T158	1		T160	13		T62	10
minimum	18254	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T153	14		T99	1		T101	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	3		T148	1		T65	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T2	18		T7	2		T9	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T148	1		T152	1		T185	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	3		T155	1		T235	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T50	13		T60	7		T61	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T57	1		T64	10		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T148	1		T65	8		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T59	1		T147	1		T26	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T57	1		T154	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T157	1		T104	4		T167	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T158	1		T61	2		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T64	15		T176	3		T110	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	10		T149	5		T103	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T12	2		T65	14		T49	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T206	2		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	10		T162	17		T69	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T1	2		T58	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T158	1		T186	1		T240	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T160	13		T62	6		T242	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17993	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T263	1		T226	10		T288	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T103	9		T185	1		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	1		T148	5		T65	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T174	9		T162	2		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T148	2		T185	17		T62	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T155	4		T103	6		T221	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	16		T60	2		T61	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T64	6		T52	1		T326	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T148	10		T65	4		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T59	8		T232	14		T305	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T57	6		T111	10		T31	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T157	11		T104	2		T167	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T61	1		T16	2		T181	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T64	10		T176	18		T167	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T149	11		T103	15		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	2		T65	11		T49	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T149	11		T227	4		T43	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	4		T162	5		T69	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T47	2		T146	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T240	9		T114	2		T323	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T62	4		T242	2		T265	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T226	10		T288	9		T307	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	607	1			T1	7		T3	6		T5	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T147	1		T157	12		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T211	8		T296	7		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T200	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T154	1		T99	1		T101	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	3		T148	1		T65	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1661	1			T2	18		T7	2		T9	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T148	1		T51	1		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	3		T162	9		T156	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T60	7		T61	5		T36	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T64	10		T155	1		T235	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T148	1		T65	8		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T57	1		T59	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T57	1		T154	1		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T157	1		T26	9		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T157	1		T158	1		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T64	15		T176	3		T26	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	10		T149	5		T61	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	2		T65	14		T74	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T206	2		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T69	16		T49	6		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T1	2		T58	1		T153	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17422	1			T1	54		T3	144		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	4		T162	5		T155	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T157	12		T62	4		T17	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T211	6		T296	2		T300	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T200	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T103	9		T185	1		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T5	1		T148	5		T65	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T174	9		T155	15		T254	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T148	2		T152	11		T185	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T162	2		T156	17		T103	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T60	2		T61	4		T230	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T64	6		T155	4		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T148	10		T65	4		T146	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T59	8		T232	14		T305	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T57	6		T48	3		T151	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T157	11		T104	2		T167	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	2		T181	12		T184	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T64	10		T176	18		T184	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T149	11		T61	1		T103	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	2		T65	11		T74	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T227	4		T17	3		T43	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T69	13		T49	3		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	1		T47	2		T146	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	1		T99	1		T101	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	3		T148	6		T65	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T2	2		T7	2		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T148	3		T152	1		T185	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T153	1		T155	5		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T50	23		T60	4		T61	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T57	1		T64	7		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T148	11		T65	5		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T59	9		T147	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T57	7		T154	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T157	12		T104	6		T167	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T158	1		T61	2		T16	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T64	11		T176	19		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	1		T149	12		T103	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T12	4		T65	12		T49	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	1		T206	1		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	8		T162	6		T69	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T1	3		T58	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T158	1		T186	1		T240	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T160	1		T62	7		T242	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18080	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T263	1		T226	11		T288	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T153	13		T101	7		T103	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T65	8		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T2	16		T9	28		T13	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T185	9		T62	1		T36	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T153	2		T235	10		T103	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T50	6		T60	5		T61	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T64	9		T52	1		T318	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T65	7		T146	11		T48	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T26	8		T36	2		T337	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T111	16		T179	8		T184	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T167	10		T229	13		T184	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T61	1		T181	15		T20	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T64	14		T176	2		T110	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	9		T149	4		T103	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T65	13		T49	4		T74	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T206	1		T149	8		T43	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	6		T162	16		T69	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T153	8		T47	2		T146	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T240	8		T303	11		T338	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T160	12		T62	3		T242	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T211	7		T257	15		T250	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T226	9		T233	3		T234	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	614	1			T1	7		T3	6		T5	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T147	1		T157	13		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T211	7		T296	3		T300	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T200	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T154	1		T99	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	3		T148	6		T65	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T2	2		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	3		T51	1		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T153	1		T162	3		T156	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T60	4		T61	5		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T64	7		T155	5		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T148	11		T65	5		T146	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T57	1		T59	9		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T57	7		T154	1		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T157	12		T26	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T157	1		T158	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T64	11		T176	19		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	1		T149	12		T61	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T12	4		T65	12		T74	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T206	1		T227	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T69	14		T49	5		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T1	3		T58	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17543	1			T1	54		T3	144		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	6		T162	16		T155	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T157	11		T160	12		T62	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T211	7		T296	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T200	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T101	7		T103	15		T110	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T65	8		T226	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T2	16		T9	28		T13	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T152	10		T185	9		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	2		T162	8		T156	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T60	5		T61	4		T36	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T64	9		T235	10		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T65	7		T146	11		T50	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T337	22		T339	10		T303	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	3		T111	8		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T26	8		T36	2		T167	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T179	8		T181	15		T184	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T64	14		T176	2		T26	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	9		T149	4		T61	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T65	13		T74	4		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T206	1		T43	14		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T69	15		T49	4		T37	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T153	8		T47	2		T146	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28