Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23403

1

T1

61

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3910

1

T1

3

T5

1

T57

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21319

1

T1

64

T3

150

T4

20

auto[1]

5994

1

T2

18

T5

5

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	339	1			T176	21		T227	5		T16	3
values[0]	84	1			T57	1		T304	16		T223	20
values[1]	628	1			T12	14		T47	5		T162	33
values[2]	537	1			T51	1		T151	3		T60	9
values[3]	589	1			T5	4		T154	1		T151	4
values[4]	702	1			T58	1		T64	25		T153	3
values[5]	872	1			T12	4		T14	10		T148	6
values[6]	737	1			T57	7		T65	41		T153	9
values[7]	804	1			T58	1		T59	9		T148	11
values[8]	694	1			T1	3		T5	1		T147	1
values[9]	3297	1			T2	18		T7	2		T9	30
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	593	1			T12	14		T57	1		T47	5
values[1]	496	1			T5	4		T154	1		T151	3
values[2]	707	1			T58	1		T64	25		T69	29
values[3]	664	1			T153	3		T156	35		T50	29
values[4]	811	1			T12	4		T14	10		T148	6
values[5]	826	1			T57	7		T59	9		T64	16
values[6]	2991	1			T2	18		T7	2		T9	30
values[7]	719	1			T1	3		T5	1		T65	12
values[8]	1080	1			T147	2		T176	21		T206	2
values[9]	129	1			T26	7		T38	1		T179	7
minimum	18297	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	10		T47	3		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T57	1		T162	26		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	3		T154	1		T110	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T151	1		T60	7		T111	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T58	1		T64	15		T227	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T69	16		T151	1		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T113	1		T167	6		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T153	3		T156	18		T50	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	2		T14	10		T153	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T148	1		T220	1		T146	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T57	1		T59	1		T65	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T64	10		T65	14		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T2	18		T7	2		T9	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T147	1		T148	2		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T52	2		T150	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	2		T5	1		T65	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T206	2		T149	9		T48	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T147	2		T176	3		T155	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T26	7		T264	1		T230	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T38	1		T179	7		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17982	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T157	1		T62	2		T110	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	4		T47	2		T33	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T162	7		T33	10		T226	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T230	10		T239	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T151	2		T60	2		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T64	10		T227	17		T185	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T69	13		T151	3		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T167	9		T183	8		T265	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T156	17		T50	16		T41	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	2		T74	3		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T148	5		T146	12		T61	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T57	6		T59	8		T65	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T64	6		T65	11		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T174	9		T254	12		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	12		T146	10		T155	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T52	1		T177	9		T32	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T65	4		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T149	11		T48	3		T227	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T176	18		T155	15		T103	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T230	16		T202	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T266	14		T340	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T157	11		T62	1		T221	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T227	1		T264	1		T230	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T176	3		T16	2		T38	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T304	1		T249	4		T228	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T57	1		T223	9		T341	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	10		T47	3		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T162	26		T157	1		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T51	1		T33	7		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T151	1		T60	7		T111	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	3		T154	1		T227	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T151	1		T17	3		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T58	1		T64	15		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T153	3		T69	16		T50	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	2		T14	10		T153	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T148	1		T220	1		T146	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T57	1		T65	9		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T65	14		T153	9		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T58	1		T59	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T148	1		T64	10		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T52	2		T150	1		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	2		T5	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T2	18		T7	2		T9	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T147	2		T161	1		T155	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T227	4		T230	16		T299	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T176	18		T16	1		T44	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T304	15		T249	3		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T223	11		T201	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	4		T47	2		T49	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T162	7		T157	11		T62	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T33	8		T230	10		T239	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T151	2		T60	2		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	1		T227	17		T185	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T151	3		T17	3		T326	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T64	10		T167	9		T168	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T69	13		T50	16		T41	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	2		T74	3		T61	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T148	5		T146	12		T156	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T57	6		T65	7		T230	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T65	11		T152	11		T185	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T59	8		T155	13		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T148	10		T64	6		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T52	1		T177	9		T32	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T148	2		T65	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T174	9		T149	11		T48	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T155	15		T103	6		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	8		T47	3		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T57	1		T162	9		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	3		T154	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T151	3		T60	4		T111	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T58	1		T64	11		T227	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T69	14		T151	4		T17	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T113	1		T167	10		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T153	1		T156	18		T50	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	4		T14	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T148	6		T220	1		T146	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	7		T59	9		T65	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T64	7		T65	12		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	2		T7	2		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T147	1		T148	14		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T52	2		T150	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	3		T5	1		T65	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T206	1		T149	12		T48	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T147	2		T176	19		T155	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T26	1		T264	1		T230	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T38	1		T179	1		T266	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18106	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T157	12		T62	2		T110	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	6		T47	2		T101	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T162	24		T33	9		T226	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	1		T110	5		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T60	5		T111	10		T181	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T64	14		T227	14		T185	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T69	15		T233	3		T272	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T167	5		T170	14		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T153	2		T156	17		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	9		T153	13		T74	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T146	16		T235	10		T61	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T65	8		T155	11		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T64	9		T65	13		T153	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T2	16		T9	28		T13	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T146	11		T160	12		T110	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T52	1		T32	12		T271	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T65	7		T157	11		T103	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T206	1		T149	8		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T176	2		T155	17		T103	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T26	6		T230	11		T273	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T179	6		T340	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T49	4		T169	10		T342	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T62	1		T110	9		T221	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T227	5		T264	1		T230	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T176	19		T16	2		T38	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T304	16		T249	4		T228	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T57	1		T223	12		T341	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	8		T47	3		T49	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T162	9		T157	12		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T51	1		T33	9		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T151	3		T60	4		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	3		T154	1		T227	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T151	4		T17	6		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T58	1		T64	11		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T153	1		T69	14		T50	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	4		T14	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T148	6		T220	1		T146	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T57	7		T65	8		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T65	12		T153	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T58	1		T59	9		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T148	11		T64	7		T146	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T52	2		T150	1		T177	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	3		T5	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T2	2		T7	2		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T147	2		T161	1		T155	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T230	11		T273	13		T259	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T176	2		T16	1		T44	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T249	3		T228	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T223	8		T201	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	6		T47	2		T49	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T162	24		T62	1		T110	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	6		T230	10		T239	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T60	5		T111	10		T33	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T227	14		T185	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T233	3		T272	14		T189	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T64	14		T167	5		T170	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T153	2		T69	15		T50	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	9		T153	13		T74	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T146	16		T156	17		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T65	8		T230	13		T188	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T65	13		T153	8		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T155	11		T242	6		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T64	9		T146	11		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T52	1		T32	12		T271	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T65	7		T157	11		T103	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T2	16		T9	28		T13	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T155	17		T103	11		T17	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28