Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T1	3		T65	5		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T176	19		T103	10		T111	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T206	1		T151	4		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	3		T65	8		T162	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T65	12		T220	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T64	7		T153	1		T155	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T2	2		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	4		T64	11		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T51	1		T62	7		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T147	1		T153	1		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T148	17		T47	3		T157	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T69	14		T149	12		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T58	1		T153	1		T146	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T157	1		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T57	7		T147	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T154	1		T49	5		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T12	8		T58	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	1		T148	3		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T182	1		T237	14		T238	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T192	1		T36	2		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18091	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T16	6		T198	4		T239	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T65	7		T184	2		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T176	2		T103	15		T111	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T206	1		T62	1		T26	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	1		T65	8		T162	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T65	13		T188	7		T170	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T64	9		T153	8		T155	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T2	16		T9	28		T13	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T64	14		T235	10		T74	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T62	3		T43	14		T18	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T153	13		T149	4		T32	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T47	2		T157	11		T111	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T69	15		T149	8		T26	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	2		T146	16		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	9		T61	4		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T110	14		T33	9		T181	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T49	4		T221	6		T242	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	6		T146	11		T33	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T61	1		T242	9		T230	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T36	21		T244	11		T245	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T253	3		T257	15		T258	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T198	2		T239	9		T257	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T146	11		T246	1		T182	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T150	1		T36	1		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T65	5		T161	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T176	19		T103	10		T111	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	3		T206	1		T155	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T65	8		T50	23		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T65	12		T220	1		T151	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	3		T64	7		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T57	1		T59	9		T162	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	4		T64	11		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T2	2		T7	2		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T147	1		T153	1		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T148	6		T47	3		T151	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T149	12		T150	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T148	11		T153	1		T146	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	1		T69	14		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T57	7		T58	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T154	1		T49	5		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	8		T58	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T148	3		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T146	11		T259	6		T248	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T36	12		T260	17		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T65	7		T253	3		T257	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T176	2		T103	15		T111	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T206	1		T26	6		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T65	8		T50	6		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T65	13		T62	1		T261	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T64	9		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T162	8		T48	3		T113	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T64	14		T155	17		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T2	16		T9	28		T13	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T153	13		T149	4		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	2		T62	3		T111	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T149	8		T26	8		T179	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T153	2		T146	16		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	9		T69	15		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T110	14		T33	9		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	4		T61	4		T221	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	6		T33	11		T226	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T61	1		T36	9		T242	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28