Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23419

1

T1

61

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3894

1

T1

3

T5

1

T57

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21295

1

T1

64

T3

150

T4

20

auto[1]

6018

1

T2

18

T5

5

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	117	1			T57	1		T262	1		T172	25
values[1]	644	1			T12	14		T47	5		T162	22
values[2]	456	1			T162	11		T51	1		T151	3
values[3]	627	1			T5	4		T154	1		T151	4
values[4]	686	1			T58	1		T64	25		T153	3
values[5]	830	1			T12	4		T14	10		T153	14
values[6]	833	1			T57	7		T148	6		T65	41
values[7]	767	1			T58	1		T59	9		T148	11
values[8]	697	1			T1	3		T5	1		T147	1
values[9]	3626	1			T2	18		T7	2		T9	30
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	768	1			T12	14		T57	1		T47	5
values[1]	546	1			T5	4		T154	1		T151	3
values[2]	696	1			T58	1		T64	25		T69	29
values[3]	752	1			T153	3		T156	35		T50	29
values[4]	747	1			T12	4		T14	10		T148	6
values[5]	832	1			T57	7		T59	9		T64	16
values[6]	3019	1			T2	18		T7	2		T9	30
values[7]	679	1			T1	3		T5	1		T65	12
values[8]	1015	1			T147	2		T176	21		T206	2
values[9]	188	1			T26	7		T38	1		T43	7
minimum	18071	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	10		T47	3		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T57	1		T162	26		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	3		T110	6		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T154	1		T151	1		T60	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T64	15		T69	16		T227	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T58	1		T151	1		T185	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T113	1		T167	6		T183	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T153	3		T156	18		T50	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	2		T14	10		T153	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T148	1		T146	17		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T57	1		T59	1		T65	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T64	10		T65	14		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T2	18		T7	2		T9	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T147	1		T148	2		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	2		T150	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	2		T5	1		T65	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T206	2		T149	9		T48	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T147	2		T176	3		T155	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T26	7		T43	1		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T38	1		T179	7		T21	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17922	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T221	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	4		T47	2		T151	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T162	7		T157	11		T62	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T230	10		T239	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T151	2		T60	2		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T64	10		T69	13		T227	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T151	3		T185	17		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T167	9		T183	8		T265	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T156	17		T50	16		T41	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	2		T74	3		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	5		T146	12		T61	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T57	6		T59	8		T65	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T64	6		T65	11		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T174	9		T254	12		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T148	12		T146	10		T155	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T52	1		T177	9		T31	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	1		T65	4		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T149	11		T48	3		T227	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T176	18		T155	15		T103	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T43	6		T230	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T266	14		T267	1		T268	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T221	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T262	1		T269	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T57	1		T172	15		T223	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	10		T47	3		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T162	17		T157	1		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T51	1		T110	6		T33	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T162	9		T151	1		T60	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	3		T227	15		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T154	1		T151	1		T185	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T64	15		T69	16		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T58	1		T153	3		T50	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	2		T14	10		T153	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T156	18		T192	1		T61	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T57	1		T65	9		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T148	1		T65	14		T153	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T58	1		T59	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T148	1		T64	10		T146	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T206	2		T52	2		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	2		T5	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1782	1			T2	18		T7	2		T9	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	437	1			T147	2		T161	1		T176	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T172	10		T223	11		T216	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	4		T47	2		T49	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T162	5		T157	11		T62	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T33	8		T230	10		T224	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T162	2		T151	2		T60	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T227	17		T270	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T151	3		T185	17		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T64	10		T69	13		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T50	16		T41	14		T270	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	2		T74	3		T61	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T156	17		T61	1		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T57	6		T65	7		T111	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T148	5		T65	11		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T59	8		T155	13		T242	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	10		T64	6		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T52	1		T32	16		T271	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	1		T148	2		T65	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T174	9		T149	11		T48	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T176	18		T155	15		T103	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	8		T47	3		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T57	1		T162	9		T157	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	3		T110	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T154	1		T151	3		T60	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T64	11		T69	14		T227	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T58	1		T151	4		T185	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T113	1		T167	10		T183	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T153	1		T156	18		T50	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	4		T14	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T148	6		T146	13		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T57	7		T59	9		T65	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T64	7		T65	12		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	2		T7	2		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T147	1		T148	14		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T52	2		T150	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	3		T5	1		T65	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T206	1		T149	12		T48	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T147	2		T176	19		T155	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T26	1		T43	7		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T38	1		T179	1		T21	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18036	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T221	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	6		T47	2		T101	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T162	24		T62	1		T110	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	1		T110	5		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T60	5		T111	10		T181	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T64	14		T69	15		T227	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T185	9		T233	3		T272	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T167	5		T265	11		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T153	2		T156	17		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	9		T153	13		T74	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T146	16		T235	10		T61	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T65	8		T155	11		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T64	9		T65	13		T153	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T2	16		T9	28		T13	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T146	11		T160	12		T110	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T52	1		T32	12		T271	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T65	7		T157	11		T103	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T206	1		T149	8		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T176	2		T155	17		T103	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T26	6		T230	11		T273	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T179	6		T257	11		T274	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T49	4		T275	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T221	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T262	1		T269	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T57	1		T172	11		T223	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	8		T47	3		T49	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T162	6		T157	12		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T51	1		T110	1		T33	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T162	3		T151	3		T60	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	3		T227	18		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T154	1		T151	4		T185	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T64	11		T69	14		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T58	1		T153	1		T50	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	4		T14	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T156	18		T192	1		T61	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T57	7		T65	8		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T148	6		T65	12		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T58	1		T59	9		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T148	11		T64	7		T146	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T206	1		T52	2		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	3		T5	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T2	2		T7	2		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T147	2		T161	1		T176	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T269	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T172	14		T223	8		T216	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	6		T47	2		T49	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T162	16		T62	1		T110	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T110	5		T33	6		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T162	8		T60	5		T181	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	1		T227	14		T198	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T185	9		T111	10		T272	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T64	14		T69	15		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T153	2		T50	6		T235	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	9		T153	13		T74	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T156	17		T61	1		T44	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T65	8		T111	8		T230	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T65	13		T153	8		T146	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T155	11		T242	6		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T64	9		T146	11		T157	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T206	1		T52	1		T32	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T65	7		T103	17		T113	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T2	16		T9	28		T13	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T176	2		T155	17		T103	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28