Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21484

1

T1

61

T3

150

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5829

1

T1

3

T2

18

T5

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21222

1

T1

61

T3

150

T4

20

auto[1]

6091

1

T1

3

T2

18

T5

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T276	21		T277	10		T278	1
values[0]	88	1			T227	32		T279	13		T187	11
values[1]	888	1			T12	14		T57	7		T65	25
values[2]	528	1			T65	12		T153	14		T146	29
values[3]	632	1			T147	1		T64	25		T220	1
values[4]	821	1			T5	1		T59	9		T147	1
values[5]	745	1			T148	3		T65	16		T162	33
values[6]	832	1			T5	4		T148	6		T153	9
values[7]	745	1			T155	33		T51	1		T61	9
values[8]	747	1			T1	3		T14	10		T58	1
values[9]	3225	1			T2	18		T7	2		T9	30
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1116	1			T12	14		T57	7		T65	37
values[1]	2807	1			T2	18		T7	2		T9	30
values[2]	665	1			T153	3		T176	21		T157	24
values[3]	889	1			T5	1		T147	1		T148	3
values[4]	737	1			T59	9		T162	33		T146	22
values[5]	737	1			T5	4		T148	6		T153	9
values[6]	883	1			T1	3		T58	1		T147	1
values[7]	668	1			T14	10		T64	16		T154	1
values[8]	654	1			T12	4		T58	1		T148	11
values[9]	112	1			T57	1		T47	5		T111	17
minimum	18045	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T57	1		T65	22		T153	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T12	10		T154	1		T155	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	1		T64	15		T146	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1583	1			T2	18		T7	2		T9	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T176	3		T151	1		T60	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T153	3		T157	12		T36	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	1		T147	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T161	1		T220	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T59	1		T162	17		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T162	9		T227	1		T111	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T148	1		T206	2		T155	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	3		T153	9		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T58	1		T147	1		T61	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T1	2		T69	16		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T49	6		T50	13		T36	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	10		T64	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	2		T148	1		T149	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T58	1		T26	7		T271	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T57	1		T280	17		T273	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T47	3		T111	9		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T237	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T57	6		T65	15		T61	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	4		T155	13		T227	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T64	10		T146	12		T74	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	970	1			T174	9		T254	12		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T176	18		T151	2		T60	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T157	12		T167	14		T181	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T148	2		T65	7		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T44	11		T240	9		T181	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T59	8		T162	5		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T162	2		T227	4		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T148	5		T155	15		T156	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T157	11		T221	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T61	4		T185	17		T104	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T69	13		T103	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T49	3		T50	16		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T64	6		T177	9		T33	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	2		T148	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T271	8		T252	16		T276	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T280	16		T24	2		T282	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T47	2		T111	8		T283	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T237	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T276	11		T277	1		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T227	15		T187	11		T284	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T57	1		T65	14		T235	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	10		T154	1		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T65	8		T153	14		T146	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T157	1		T151	1		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T147	1		T64	15		T176	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T220	1		T31	1		T36	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T59	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T153	3		T161	1		T157	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T148	1		T65	9		T162	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T162	9		T37	8		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T148	1		T206	2		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	3		T153	9		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T155	18		T61	5		T185	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T51	1		T103	18		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T58	1		T147	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	2		T14	10		T64	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T12	2		T57	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1678	1			T2	18		T7	2		T9	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T276	10		T277	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T227	17		T284	6		T285	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T57	6		T65	11		T61	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	4		T155	13		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T65	4		T146	12		T74	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T151	5		T152	11		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T64	10		T176	18		T60	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T31	7		T167	9		T181	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T59	8		T52	1		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T157	12		T111	2		T44	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T148	2		T65	7		T162	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T162	2		T37	3		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T148	5		T146	10		T156	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T157	11		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	15		T61	4		T185	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T103	15		T17	3		T43	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T155	4		T104	4		T286	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T64	6		T69	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	2		T148	10		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1031	1			T174	9		T47	2		T254	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T57	7		T65	17		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	8		T154	1		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T147	1		T64	11		T146	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1299	1			T2	2		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T176	19		T151	3		T60	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T153	1		T157	13		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T147	1		T148	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T161	1		T220	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T59	9		T162	6		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T162	3		T227	5		T111	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T148	6		T206	1		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	3		T153	1		T157	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T58	1		T147	1		T61	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	3		T69	14		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T49	5		T50	23		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	1		T64	7		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	4		T148	11		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T58	1		T26	1		T271	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T57	1		T280	17		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T47	3		T111	9		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18031	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T237	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T65	20		T153	13		T235	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	6		T155	11		T227	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T64	14		T146	16		T74	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1254	1			T2	16		T9	28		T13	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T176	2		T60	5		T211	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T153	2		T157	11		T36	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T65	8		T52	1		T113	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T44	11		T229	13		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T162	16		T146	11		T149	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T162	8		T111	8		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T206	1		T155	17		T156	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	1		T153	8		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T61	4		T185	9		T110	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T69	15		T103	17		T33	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	4		T50	6		T36	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T14	9		T64	9		T33	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T149	8		T48	3		T101	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	6		T271	8		T276	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T280	16		T273	13		T282	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T47	2		T111	8		T287	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T276	11		T277	10		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T279	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T227	18		T187	1		T284	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T57	7		T65	12		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	8		T154	1		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T65	5		T153	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T157	1		T151	6		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T147	1		T64	11		T176	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T220	1		T31	8		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	1		T59	9		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T153	1		T161	1		T157	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T148	3		T65	8		T162	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T162	3		T37	9		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T148	6		T206	1		T146	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	3		T153	1		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T155	16		T61	5		T185	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T51	1		T103	16		T17	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T58	1		T147	1		T155	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	3		T14	1		T64	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T12	4		T57	1		T148	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1393	1			T2	2		T7	2		T9	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T227	14		T187	10		T285	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T65	13		T235	10		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	6		T155	11		T111	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T65	7		T153	13		T146	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T152	10		T103	15		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T64	14		T176	2		T60	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T36	9		T167	5		T181	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T52	1		T113	6		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T153	2		T157	11		T111	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T65	8		T162	16		T149	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T162	8		T37	2		T240	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T206	1		T146	11		T156	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	1		T153	8		T167	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T155	17		T61	4		T185	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T103	17		T221	13		T181	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T110	11		T104	1		T286	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	9		T64	9		T69	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T149	8		T48	3		T49	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1316	1			T2	16		T9	28		T13	34

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28