Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23455

1

T1

61

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3858

1

T1

3

T5

5

T12

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21294

1

T1

64

T3

150

T4

20

auto[1]

6019

1

T2

18

T5

4

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	51	1			T148	3		T19	2		T288	10
values[0]	32	1			T289	32		-	-		-	-
values[1]	538	1			T65	12		T161	1		T176	21
values[2]	746	1			T1	3		T65	16		T206	2
values[3]	777	1			T5	4		T57	1		T64	16
values[4]	668	1			T12	4		T59	9		T64	25
values[5]	3152	1			T2	18		T7	2		T9	30
values[6]	883	1			T148	6		T153	14		T47	5
values[7]	587	1			T14	10		T148	11		T69	29
values[8]	773	1			T58	2		T147	1		T153	3
values[9]	1076	1			T5	1		T12	14		T57	7
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	734	1			T1	3		T65	12		T161	1
values[1]	724	1			T5	4		T65	16		T162	22
values[2]	776	1			T64	16		T65	25		T153	9
values[3]	3159	1			T2	18		T7	2		T9	30
values[4]	906	1			T147	1		T153	14		T47	5
values[5]	590	1			T148	17		T69	29		T149	20
values[6]	738	1			T14	10		T58	1		T153	3
values[7]	562	1			T57	7		T147	1		T154	1
values[8]	965	1			T5	1		T12	14		T58	1
values[9]	119	1			T192	1		T36	10		T38	1
minimum	18040	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T65	8		T161	1		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	2		T176	3		T52	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T206	2		T151	1		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	3		T65	9		T162	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T65	14		T162	9		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T64	10		T153	9		T155	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1669	1			T2	18		T7	2		T9	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	2		T64	15		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T47	3		T51	1		T62	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T147	1		T153	14		T149	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T148	2		T157	12		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T69	16		T149	9		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T58	1		T153	3		T146	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	10		T157	1		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T57	1		T147	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T154	1		T49	6		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T12	10		T58	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	1		T148	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T36	10		T182	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T192	1		T38	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T187	1		T291	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T65	4		T155	4		T270	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T176	18		T52	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T151	3		T62	1		T240	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T65	7		T162	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T65	11		T162	2		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T64	6		T155	15		T156	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T59	8		T174	9		T48	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	2		T64	10		T74	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T47	2		T62	4		T43	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T149	11		T32	16		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T148	15		T157	12		T151	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T69	13		T149	11		T31	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T146	12		T155	13		T185	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T61	4		T16	1		T184	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T57	6		T177	9		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T49	3		T221	4		T242	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	4		T146	10		T33	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T148	2		T61	1		T242	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T237	13		T238	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T243	11		T24	3		T244	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T288	1		T248	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T148	1		T19	1		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T289	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T65	8		T161	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T176	3		T103	16		T111	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T206	2		T155	1		T26	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	2		T65	9		T50	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T57	1		T65	14		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	3		T64	10		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T59	1		T162	9		T48	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	2		T64	15		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1674	1			T2	18		T7	2		T9	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T147	1		T149	5		T235	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T148	1		T47	3		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T153	14		T149	9		T26	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T148	1		T146	17		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	10		T69	16		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T58	2		T147	1		T153	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T154	1		T49	6		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T12	10		T57	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T5	1		T192	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T288	9		T248	2		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T148	2		T19	1		T243	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T289	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T65	4		T252	16		T253	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T176	18		T103	9		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T155	4		T240	9		T270	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T65	7		T50	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T65	11		T151	3		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	1		T64	6		T162	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T59	8		T162	2		T48	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	2		T64	10		T155	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T174	9		T254	12		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T149	11		T74	3		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T148	5		T47	2		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T149	11		T31	12		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T148	10		T146	12		T155	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T69	13		T16	1		T184	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T151	2		T185	1		T33	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T49	3		T61	4		T221	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	4		T57	6		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T61	1		T226	1		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T65	5		T161	1		T155	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	3		T176	19		T52	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T206	1		T151	4		T62	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	3		T65	8		T162	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T65	12		T162	3		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T64	7		T153	1		T155	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T2	2		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	4		T64	11		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T47	3		T51	1		T62	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T147	1		T153	1		T149	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T148	17		T157	13		T151	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T69	14		T149	12		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T58	1		T153	1		T146	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T157	1		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T57	7		T147	1		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T154	1		T49	5		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	8		T58	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	1		T148	3		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T36	1		T182	1		T237	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T192	1		T38	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T187	1		T291	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T65	7		T184	2		T253	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T176	2		T52	1		T103	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T206	1		T62	1		T26	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T65	8		T162	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T65	13		T162	8		T167	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T64	9		T153	8		T155	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T2	16		T9	28		T13	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T64	14		T235	10		T74	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T47	2		T62	3		T43	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T153	13		T149	4		T26	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T157	11		T111	8		T286	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T69	15		T149	8		T179	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T153	2		T146	16		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	9		T61	4		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T110	14		T33	9		T181	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	4		T221	6		T242	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	6		T146	11		T33	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T61	1		T36	12		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T36	9		T292	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T24	1		T244	11		T293	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T288	10		T248	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T148	3		T19	2		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T289	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T65	5		T161	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T176	19		T103	10		T111	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T206	1		T155	5		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	3		T65	8		T50	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T57	1		T65	12		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	3		T64	7		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T59	9		T162	3		T48	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	4		T64	11		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T2	2		T7	2		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T147	1		T149	12		T235	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T148	6		T47	3		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T153	1		T149	12		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T148	11		T146	13		T155	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	1		T69	14		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T58	2		T147	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T154	1		T49	5		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T12	8		T57	7		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T5	1		T192	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T248	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T251	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T289	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T65	7		T253	3		T257	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T176	2		T103	15		T111	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T206	1		T26	6		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T65	8		T50	6		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T65	13		T62	1		T261	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T64	9		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T162	8		T48	3		T113	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T64	14		T155	17		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T2	16		T9	28		T13	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T149	4		T235	10		T74	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	2		T62	3		T111	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T153	13		T149	8		T26	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	16		T155	11		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	9		T69	15		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T153	2		T110	14		T33	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T49	4		T61	4		T221	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	6		T146	11		T33	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T61	1		T36	12		T198	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28