Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23344

1

T1

64

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3969

1

T5

4

T58

2

T147

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20963

1

T1

64

T3

150

T4

20

auto[1]

6350

1

T2

18

T5

5

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	397	1			T153	14		T156	35		T62	10
values[0]	9	1			T153	9		-	-		-	-
values[1]	626	1			T1	3		T57	7		T154	1
values[2]	785	1			T14	10		T58	1		T148	3
values[3]	803	1			T65	37		T157	36		T51	1
values[4]	2994	1			T2	18		T7	2		T9	30
values[5]	632	1			T147	2		T155	38		T48	12
values[6]	729	1			T12	14		T64	25		T161	1
values[7]	653	1			T5	1		T57	1		T147	1
values[8]	688	1			T5	4		T58	1		T59	9
values[9]	967	1			T12	4		T148	11		T64	16
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	659	1			T1	3		T14	10		T57	7
values[1]	759	1			T153	3		T162	22		T69	29
values[2]	742	1			T65	37		T157	12		T51	1
values[3]	3044	1			T2	18		T7	2		T9	30
values[4]	615	1			T147	2		T161	1		T155	38
values[5]	696	1			T5	1		T12	14		T147	1
values[6]	713	1			T57	1		T58	1		T59	9
values[7]	616	1			T5	4		T64	16		T49	9
values[8]	1162	1			T12	4		T148	11		T65	16
values[9]	95	1			T62	10		T26	9		T253	12
minimum	18212	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	2		T14	10		T57	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T58	1		T148	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	3		T162	17		T69	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T155	12		T157	12		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	11		T185	1		T36	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T65	22		T157	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T2	18		T7	2		T9	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T60	7		T221	14		T181	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	1		T161	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T147	1		T155	18		T48	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T12	10		T64	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T147	1		T99	1		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T57	1		T59	1		T206	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	1		T176	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T64	10		T49	6		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	3		T177	1		T103	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T12	2		T148	1		T65	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T153	14		T156	18		T111	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T170	10		T223	9		T23	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T62	6		T26	9		T253	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17929	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T153	9		T187	1		T169	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T57	6		T162	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T148	2		T149	11		T61	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T162	5		T69	13		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T155	13		T157	12		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T152	11		T185	1		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T65	15		T157	11		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T148	5		T174	9		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T60	2		T221	11		T181	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T155	4		T52	1		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T155	15		T48	3		T104	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	4		T64	10		T32	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T181	12		T183	2		T184	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T59	8		T16	2		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T176	18		T227	17		T185	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T64	6		T49	3		T151	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T103	15		T111	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	2		T148	10		T65	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T156	17		T111	9		T104	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T223	11		T23	2		T219	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T62	4		T253	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T169	9		T117	11		T256	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T113	7		T38	1		T230	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T153	14		T156	18		T62	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T153	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	2		T57	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T149	9		T61	2		T229	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	10		T153	3		T162	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T58	1		T148	1		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T152	11		T185	1		T36	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T65	22		T157	13		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T2	18		T7	2		T9	30
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T151	1		T60	7		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T147	1		T155	1		T110	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T147	1		T155	18		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	10		T64	15		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T99	1		T186	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T57	1		T206	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T147	1		T176	3		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	1		T49	6		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	3		T58	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T12	2		T148	1		T64	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T26	9		T38	1		T104	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T113	2		T230	16		T172	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T156	17		T62	4		T111	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T57	6		T146	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	11		T61	1		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T162	7		T69	13		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T148	2		T155	13		T151	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T152	11		T185	1		T167	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T65	15		T157	23		T33	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T148	5		T174	9		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T151	2		T60	2		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T155	4		T31	7		T241	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T155	15		T48	3		T104	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	4		T64	10		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T181	12		T183	2		T232	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	2		T44	12		T232	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T176	18		T227	17		T185	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T59	8		T49	3		T151	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T103	15		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	2		T148	10		T64	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T104	4		T167	5		T184	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	3		T14	1		T57	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T58	1		T148	3		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	1		T162	6		T69	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T155	14		T157	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T152	12		T185	2		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T65	17		T157	12		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T2	2		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T60	4		T221	12		T181	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T147	1		T161	1		T155	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T147	1		T155	16		T48	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T12	8		T64	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T147	1		T99	1		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	1		T59	9		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T58	1		T176	19		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T64	7		T49	5		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	3		T177	1		T103	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T12	4		T148	11		T65	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T153	1		T156	18		T111	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T170	1		T223	12		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T62	7		T26	1		T253	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18066	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T153	1		T187	1		T169	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	9		T162	8		T146	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T149	8		T61	1		T229	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	2		T162	16		T69	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T155	11		T157	11		T61	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T152	10		T36	12		T198	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T65	20		T33	6		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T2	16		T9	28		T13	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T60	5		T221	13		T181	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T52	1		T110	5		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T155	17		T48	3		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	6		T64	14		T32	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T181	15		T184	2		T233	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T206	1		T26	6		T44	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T176	2		T227	14		T185	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T64	9		T49	4		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T103	17		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T65	8		T47	2		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T153	13		T156	17		T111	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T170	9		T223	8		T23	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T62	3		T26	8		T253	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T268	3		T294	10		T295	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T153	8		T169	8		T117	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T113	3		T38	1		T230	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T153	1		T156	18		T62	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T153	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	3		T57	7		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T149	12		T61	2		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	1		T153	1		T162	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T58	1		T148	3		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	12		T185	2		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T65	17		T157	25		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T2	2		T7	2		T9	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T151	3		T60	4		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T147	1		T155	5		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T147	1		T155	16		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	8		T64	11		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T99	1		T186	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T57	1		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T147	1		T176	19		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T59	9		T49	5		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	3		T58	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	4		T148	11		T64	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T26	1		T38	1		T104	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T113	6		T230	11		T172	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T153	13		T156	17		T62	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T153	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T146	16		T18	2		T189	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T149	8		T61	1		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	9		T153	2		T162	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T155	11		T61	4		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T152	10		T36	12		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T65	20		T157	11		T33	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T2	16		T9	28		T13	34
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T60	5		T17	1		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T110	5		T195	10		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T155	17		T48	3		T231	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	6		T64	14		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T181	15		T232	2		T184	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T206	1		T44	2		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T176	2		T227	14		T185	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	4		T235	10		T103	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	1		T103	17		T110	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T64	9		T65	8		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T26	8		T104	1		T167	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28