Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23736

1

T1

61

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3577

1

T1

3

T5

5

T12

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20903

1

T1

57

T3

144

T4

20

auto[1]

6410

1

T1

7

T2

18

T3

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	490	1			T1	7		T3	6		T5	7
values[0]	52	1			T234	19		T200	18		T296	9
values[1]	604	1			T5	4		T65	16		T154	1
values[2]	2990	1			T2	18		T7	2		T9	30
values[3]	649	1			T153	3		T162	11		T156	35
values[4]	691	1			T59	9		T148	11		T64	16
values[5]	588	1			T57	8		T147	1		T154	1
values[6]	740	1			T157	13		T16	6		T26	9
values[7]	695	1			T64	25		T176	21		T149	16
values[8]	821	1			T5	1		T12	4		T14	10
values[9]	1450	1			T1	3		T12	14		T58	1
minimum	17543	1			T1	54		T3	144		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	854	1			T5	4		T148	6		T65	16
values[1]	2948	1			T2	18		T7	2		T9	30
values[2]	610	1			T153	3		T155	5		T50	29
values[3]	688	1			T57	1		T148	11		T64	16
values[4]	623	1			T57	7		T59	9		T147	1
values[5]	764	1			T157	12		T158	1		T61	3
values[6]	687	1			T14	10		T64	25		T176	21
values[7]	885	1			T5	1		T12	4		T65	25
values[8]	1019	1			T1	3		T12	14		T58	1
values[9]	202	1			T147	1		T62	10		T110	6
minimum	18033	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T148	1		T153	14		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	3		T65	9		T152	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T2	18		T7	2		T9	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T148	1		T151	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T153	3		T155	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T50	13		T235	11		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T57	1		T64	10		T65	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T148	1		T52	2		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T59	1		T48	9		T111	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T57	1		T147	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T157	1		T158	1		T26	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T61	2		T16	4		T297	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T64	15		T176	3		T149	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	10		T103	18		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	2		T65	14		T149	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T206	2		T146	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T162	17		T69	16		T155	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	2		T12	10		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T110	6		T240	10		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T147	1		T62	6		T179	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T148	5		T103	9		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T65	7		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T174	9		T162	2		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T148	2		T151	5		T185	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T155	4		T103	6		T221	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T50	16		T177	9		T60	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T64	6		T65	4		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T148	10		T52	1		T31	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T59	8		T48	3		T111	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T57	6		T111	8		T31	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T157	11		T104	2		T167	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T61	1		T16	2		T181	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T64	10		T176	18		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T103	15		T111	9		T32	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	2		T65	11		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	12		T43	15		T44	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T162	5		T69	13		T155	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	1		T12	4		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T240	9		T114	2		T124	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T62	4		T279	11		T299	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	1		T12	2		T146	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	487	1			T1	7		T3	6		T5	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T17	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T200	9		T296	7		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T234	19		T301	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T154	1		T101	8		T103	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	3		T65	9		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T2	18		T7	2		T9	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T148	1		T151	1		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T153	3		T162	9		T156	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T235	11		T60	7		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T59	1		T64	10		T65	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T148	1		T50	13		T52	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T57	1		T48	9		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T57	1		T147	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T157	1		T26	9		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T157	1		T16	4		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T64	15		T176	3		T149	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	2		T103	18		T111	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	2		T65	14		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T14	10		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T162	17		T69	16		T149	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	475	1			T1	2		T12	10		T58	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17422	1			T1	54		T3	144		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T17	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T200	9		T296	2		T300	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T301	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T103	9		T185	1		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	1		T65	7		T286	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T148	5		T174	9		T155	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T148	2		T151	5		T152	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T162	2		T156	17		T103	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T60	2		T61	4		T230	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T59	8		T64	6		T65	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T148	10		T50	16		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T48	3		T151	3		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T57	6		T31	5		T183	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T157	11		T104	2		T167	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	2		T181	12		T184	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T64	10		T176	18		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T61	1		T103	15		T111	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	2		T65	11		T227	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	15		T44	12		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T162	5		T69	13		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T1	1		T12	4		T47	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T148	6		T153	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	3		T65	8		T152	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T2	2		T7	2		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T148	3		T151	6		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T153	1		T155	5		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T50	23		T235	1		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T57	1		T64	7		T65	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T148	11		T52	2		T31	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T59	9		T48	9		T111	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T57	7		T147	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T157	12		T158	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	2		T16	6		T297	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T64	11		T176	19		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T103	16		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T12	4		T65	12		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	1		T206	1		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T162	6		T69	14		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T1	3		T12	8		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T110	1		T240	11		T114	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T147	1		T62	7		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18032	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T153	13		T101	7		T103	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	1		T65	8		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T2	16		T9	28		T13	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T185	9		T62	1		T36	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	2		T103	11		T221	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T50	6		T235	10		T60	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T64	9		T65	7		T146	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T52	1		T276	3		T302	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T48	3		T111	8		T26	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T111	8		T179	8		T184	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T26	6		T167	10		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T61	1		T181	15		T233	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T64	14		T176	2		T149	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	9		T103	17		T110	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T65	13		T149	8		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T206	1		T146	16		T43	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T162	16		T69	15		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	6		T153	8		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T110	5		T240	8		T303	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T62	3		T179	6		T273	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	487	1			T1	7		T3	6		T5	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T17	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T200	10		T296	3		T300	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T234	1		T301	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T154	1		T101	1		T103	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	3		T65	8		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T2	2		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T148	3		T151	6		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T153	1		T162	3		T156	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T235	1		T60	4		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T59	9		T64	7		T65	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T148	11		T50	23		T52	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T57	1		T48	9		T151	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T57	7		T147	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T157	12		T26	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T157	1		T16	6		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T64	11		T176	19		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	2		T103	16		T111	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	4		T65	12		T227	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	1		T14	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T162	6		T69	14		T149	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	456	1			T1	3		T12	8		T58	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17543	1			T1	54		T3	144		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T17	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T200	8		T296	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T234	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T101	7		T103	15		T110	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T65	8		T286	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T2	16		T9	28		T13	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T152	10		T185	9		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T153	2		T162	8		T156	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T235	10		T60	5		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T64	9		T65	7		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T50	6		T52	1		T111	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T48	3		T111	8		T230	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T233	16		T170	18		T171	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T26	8		T36	2		T167	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T179	8		T181	15		T184	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T64	14		T176	2		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T61	1		T103	17		T111	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T65	13		T167	5		T199	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	9		T206	1		T110	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T162	16		T69	15		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T12	6		T153	8		T47	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28