Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23609

1

T1

61

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3704

1

T1

3

T5

1

T12

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21358

1

T1

64

T3

150

T4

20

auto[1]

5955

1

T2

18

T5

5

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T104	10		T21	1		-	-
values[0]	40	1			T169	18		T299	6		T284	7
values[1]	781	1			T58	1		T64	25		T65	25
values[2]	844	1			T14	10		T59	9		T153	3
values[3]	859	1			T12	14		T57	8		T162	11
values[4]	682	1			T5	1		T148	3		T64	16
values[5]	660	1			T65	12		T153	14		T176	21
values[6]	646	1			T5	4		T157	25		T152	23
values[7]	720	1			T148	6		T65	16		T146	22
values[8]	2830	1			T2	18		T7	2		T9	30
values[9]	1210	1			T1	3		T58	1		T147	2
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1021	1			T58	1		T59	9		T64	25
values[1]	791	1			T12	14		T14	10		T162	11
values[2]	951	1			T57	8		T153	3		T146	29
values[3]	555	1			T148	3		T64	16		T176	21
values[4]	660	1			T5	5		T65	12		T153	14
values[5]	750	1			T149	16		T156	35		T157	25
values[6]	2933	1			T2	18		T7	2		T9	30
values[7]	554	1			T12	4		T147	1		T148	11
values[8]	862	1			T147	2		T154	2		T220	1
values[9]	174	1			T1	3		T58	1		T151	4
minimum	18062	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T58	1		T59	1		T64	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T162	17		T49	6		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	10		T162	9		T160	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T12	10		T69	16		T103	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T57	2		T153	3		T146	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T111	9		T33	12		T104	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T148	1		T155	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T64	10		T176	3		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	3		T153	14		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	1		T65	8		T48	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T156	18		T235	11		T60	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T149	5		T157	13		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T2	18		T7	2		T9	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	9		T146	12		T158	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T147	1		T149	9		T74	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	2		T148	1		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T147	1		T154	2		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T147	1		T151	1		T227	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T151	1		T43	1		T182	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T1	2		T58	1		T33	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17920	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T276	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T59	8		T64	10		T65	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T162	5		T49	3		T61	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T162	2		T62	1		T224	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	4		T69	13		T103	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T57	6		T146	12		T155	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T111	2		T33	2		T104	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T148	2		T155	4		T240	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T64	6		T176	18		T151	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	1		T177	9		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T65	4		T48	3		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	17		T60	2		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T149	11		T157	12		T32	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T148	5		T174	9		T50	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T65	7		T146	10		T31	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T149	11		T74	3		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	2		T148	10		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T227	4		T304	4		T46	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T151	2		T227	17		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T151	3		T43	6		T305	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T1	1		T33	10		T221	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T104	6		T21	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T169	9		T218	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T299	1		T284	1		T300	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T58	1		T64	15		T65	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T162	17		T49	6		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T14	10		T59	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T61	2		T103	12		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T57	2		T162	9		T146	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T12	10		T69	16		T103	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T148	1		T155	19		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T64	10		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T153	14		T156	18		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T65	8		T176	3		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	3		T152	1		T60	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T157	13		T152	11		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T148	1		T235	11		T111	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T65	9		T146	12		T149	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T2	18		T7	2		T9	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	2		T157	1		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T147	1		T154	2		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T1	2		T58	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T104	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T169	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T299	5		T284	6		T300	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T64	10		T65	11		T41	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T162	5		T49	3		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T59	8		T155	13		T62	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T61	1		T103	6		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T57	6		T162	2		T146	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	4		T69	13		T103	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T148	2		T155	19		T37	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T64	6		T151	5		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T156	17		T177	9		T61	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T65	4		T176	18		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	1		T60	2		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T157	12		T152	11		T286	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T148	5		T111	9		T183	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T65	7		T146	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T174	9		T149	11		T50	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	2		T157	11		T52	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T151	3		T227	4		T43	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	1		T148	10		T47	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T58	1		T59	9		T64	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T162	6		T49	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T162	3		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	8		T69	14		T103	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T57	8		T153	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T111	3		T33	3		T104	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T148	3		T155	5		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T64	7		T176	19		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	3		T153	1		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	1		T65	5		T48	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T156	18		T235	1		T60	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T149	12		T157	14		T32	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T2	2		T7	2		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T65	8		T146	11		T158	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	1		T149	12		T74	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	4		T148	11		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T147	1		T154	2		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T147	1		T151	3		T227	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T151	4		T43	7		T182	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T1	3		T58	1		T33	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18031	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T276	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T64	14		T65	13		T153	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T162	16		T49	4		T61	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	9		T162	8		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	6		T69	15		T103	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T153	2		T146	16		T155	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T111	8		T33	11		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T26	8		T240	8		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T64	9		T176	2		T185	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T5	1		T153	13		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T65	7		T48	3		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T156	17		T235	10		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T149	4		T157	11		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T2	16		T9	28		T13	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T65	8		T146	11		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T149	8		T74	4		T111	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	2		T52	1		T101	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T257	15		T306	11		T189	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T227	14		T110	9		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T307	12		T308	1		T309	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T33	9		T221	6		T242	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T310	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T104	9		T21	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T169	10		T218	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T299	6		T284	7		T300	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T58	1		T64	11		T65	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T162	6		T49	5		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T14	1		T59	9		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T61	2		T103	7		T241	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T57	8		T162	3		T146	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T12	8		T69	14		T103	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T148	3		T155	21		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T64	7		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T153	1		T156	18		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T65	5		T176	19		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	3		T152	1		T60	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T157	14		T152	12		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T148	6		T235	1		T111	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T65	8		T146	11		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	2		T7	2		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	4		T157	12		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T147	1		T154	2		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T1	3		T58	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T104	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T169	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T64	14		T65	13		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T162	16		T49	4		T110	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	9		T153	2		T206	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T61	1		T103	11		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T162	8		T146	16		T278	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	6		T69	15		T103	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T155	17		T26	8		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T64	9		T181	25		T198	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T153	13		T156	17		T61	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T65	7		T176	2		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	1		T60	5		T36	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T157	11		T152	10		T286	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T235	10		T111	10		T26	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T65	8		T146	11		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T2	16		T9	28		T13	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T52	1		T110	11		T33	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T167	10		T305	15		T253	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T47	2		T227	14		T101	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28