Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27313

1

T1

64

T2

18

T3

150

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23686

1

T1

61

T2

18

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3627

1

T1

3

T5

1

T12

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21329

1

T1

64

T3

150

T4

20

auto[1]

5984

1

T2

18

T5

5

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23344

1

T1

63

T2

18

T3

150

auto[1]

3969

1

T1

1

T5

2

T12

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	270	1			T1	3		T154	1		T150	1
values[0]	14	1			T299	6		T284	7		T218	1
values[1]	797	1			T58	1		T64	25		T65	25
values[2]	818	1			T12	14		T14	10		T59	9
values[3]	861	1			T57	8		T153	3		T162	11
values[4]	725	1			T5	1		T148	3		T64	16
values[5]	642	1			T65	12		T153	14		T176	21
values[6]	672	1			T5	4		T157	25		T152	1
values[7]	706	1			T148	6		T65	16		T146	22
values[8]	2830	1			T2	18		T7	2		T9	30
values[9]	948	1			T12	4		T58	1		T147	2
minimum	18030	1			T1	61		T3	150		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	832	1			T64	25		T65	25		T153	9
values[1]	819	1			T12	14		T14	10		T59	9
values[2]	837	1			T57	8		T153	3		T146	29
values[3]	659	1			T148	3		T64	16		T155	38
values[4]	651	1			T5	1		T65	12		T153	14
values[5]	738	1			T5	4		T149	16		T157	25
values[6]	2936	1			T2	18		T7	2		T9	30
values[7]	605	1			T12	4		T147	1		T148	11
values[8]	843	1			T58	1		T147	2		T154	2
values[9]	132	1			T1	3		T33	20		T43	7
minimum	18261	1			T1	61		T3	150		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

4358

1

T2

16

T5

1

T9

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T64	15		T65	14		T153	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	6		T150	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	10		T59	1		T162	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T12	10		T69	16		T62	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T57	2		T153	3		T146	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T103	16		T111	9		T33	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T148	1		T155	19		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T64	10		T192	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T153	14		T156	18		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	1		T65	8		T176	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	3		T157	1		T235	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T149	5		T157	12		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T2	18		T7	2		T9	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	9		T146	12		T158	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T147	1		T149	9		T74	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	2		T148	1		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T147	1		T154	2		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T58	1		T147	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T43	1		T182	2		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T1	2		T33	10		T221	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17971	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T162	17		T110	6		T226	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T64	10		T65	11		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T49	3		T61	1		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T59	8		T162	2		T103	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	4		T69	13		T62	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T57	6		T146	12		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T103	9		T111	2		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T148	2		T155	19		T240	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T64	6		T151	5		T185	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T156	17		T177	9		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T65	4		T176	18		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T5	1		T60	2		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T149	11		T157	12		T32	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T148	5		T174	9		T50	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T65	7		T146	10		T171	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T149	11		T74	3		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T12	2		T148	10		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T151	3		T227	4		T253	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T151	2		T227	17		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T43	6		T305	2		T311	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T1	1		T33	10		T221	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T12	2		T146	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T162	5		T226	10		T114	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T154	1		T150	1		T182	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T1	2		T151	1		T33	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T299	1		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T58	1		T64	15		T65	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T162	17		T49	6		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T14	10		T59	1		T206	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	10		T61	2		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T57	2		T153	3		T162	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T69	16		T151	1		T103	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T148	1		T155	19		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T64	10		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	14		T156	18		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T65	8		T176	3		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	3		T157	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T157	12		T38	1		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T148	1		T50	13		T235	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T65	9		T146	12		T149	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T2	18		T7	2		T9	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T157	1		T158	1		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T147	1		T154	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	2		T58	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T312	9		T311	7		T313	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T1	1		T151	2		T33	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T299	5		T284	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T64	10		T65	11		T41	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T162	5		T49	3		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T59	8		T103	6		T62	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	4		T61	1		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T57	6		T162	2		T146	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T69	13		T151	5		T103	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T148	2		T155	19		T37	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T64	6		T17	3		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T156	17		T177	9		T61	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T65	4		T176	18		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	1		T60	2		T103	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T157	12		T286	15		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T148	5		T50	16		T183	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T65	7		T146	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T174	9		T149	11		T74	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T157	11		T52	1		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T151	3		T227	4		T43	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	2		T148	10		T47	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T12	2		T146	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T64	11		T65	12		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T49	5		T150	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	1		T59	9		T162	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	8		T69	14		T62	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T57	8		T153	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T103	10		T111	3		T33	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T148	3		T155	21		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T64	7		T192	1		T151	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T153	1		T156	18		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T65	5		T176	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	3		T157	1		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T149	12		T157	13		T32	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T2	2		T7	2		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T65	8		T146	11		T158	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T147	1		T149	12		T74	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	4		T148	11		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T147	1		T154	2		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T58	1		T147	1		T151	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T43	7		T182	2		T305	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T1	3		T33	11		T221	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18083	1			T1	61		T3	150		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T162	6		T110	1		T226	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T64	14		T65	13		T153	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	4		T61	1		T36	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	9		T162	8		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	6		T69	15		T62	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T153	2		T146	16		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T103	15		T111	8		T33	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T155	17		T26	8		T240	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T64	9		T185	9		T181	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T153	13		T156	17		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T65	7		T176	2		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T235	10		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T149	4		T157	11		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T2	16		T9	28		T13	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T65	8		T146	11		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T149	8		T74	4		T111	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T47	2		T52	1		T101	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T253	3		T306	11		T307	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T227	14		T110	9		T111	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T309	14		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T33	9		T221	6		T172	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T44	11		T169	8		T310	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T162	16		T110	5		T226	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T154	1		T150	1		T182	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T1	3		T151	3		T33	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	6		T284	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T58	1		T64	11		T65	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T162	6		T49	5		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	1		T59	9		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	8		T61	2		T241	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T57	8		T153	1		T162	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T69	14		T151	6		T103	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T148	3		T155	21		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	1		T64	7		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T153	1		T156	18		T177	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T65	5		T176	19		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	3		T157	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T157	13		T38	1		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T148	6		T50	23		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T65	8		T146	11		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T2	2		T7	2		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T157	12		T158	1		T52	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T147	1		T154	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	4		T58	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	61		T3	150		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T312	11		T313	13		T309	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T33	9		T104	1		T221	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T64	14		T65	13		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T162	16		T49	4		T110	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	9		T206	1		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	6		T61	1		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T153	2		T162	8		T146	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T69	15		T103	15		T62	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T155	17		T26	8		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T64	9		T167	5		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T153	13		T156	17		T61	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T65	7		T176	2		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	1		T60	5		T103	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T157	11		T286	12		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T50	6		T235	10		T26	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T65	8		T146	11		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T2	16		T9	28		T13	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T52	1		T110	11		T33	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T167	10		T305	15		T253	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T47	2		T227	14		T101	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22955

1

T1

64

T2

2

T3

150

auto[1]

auto[0]

4358

1

T2

16

T5

1

T9

28