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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.27


Total test records in report: 918
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T794 /workspace/coverage/default/16.adc_ctrl_clock_gating.4084570980 Aug 01 06:52:24 PM PDT 24 Aug 01 07:05:36 PM PDT 24 330665456525 ps
T795 /workspace/coverage/default/0.adc_ctrl_filters_wakeup.271041893 Aug 01 06:51:56 PM PDT 24 Aug 01 06:57:12 PM PDT 24 168339993704 ps
T796 /workspace/coverage/default/10.adc_ctrl_clock_gating.54212005 Aug 01 06:52:04 PM PDT 24 Aug 01 06:58:44 PM PDT 24 361673455111 ps
T70 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4142045090 Aug 01 06:23:51 PM PDT 24 Aug 01 06:23:54 PM PDT 24 4879567107 ps
T78 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3101987579 Aug 01 06:23:40 PM PDT 24 Aug 01 06:23:43 PM PDT 24 323732470 ps
T79 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3465703872 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 379516430 ps
T75 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2397670014 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:11 PM PDT 24 8482846827 ps
T76 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1185807658 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:53 PM PDT 24 3800678416 ps
T71 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2981377495 Aug 01 06:23:34 PM PDT 24 Aug 01 06:23:50 PM PDT 24 4450065816 ps
T83 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3516708500 Aug 01 06:23:52 PM PDT 24 Aug 01 06:23:53 PM PDT 24 459703070 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3681583819 Aug 01 06:23:43 PM PDT 24 Aug 01 06:23:45 PM PDT 24 595558286 ps
T73 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2483773482 Aug 01 06:23:49 PM PDT 24 Aug 01 06:23:51 PM PDT 24 540675063 ps
T797 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4137863490 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 512594662 ps
T84 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1534889864 Aug 01 06:23:48 PM PDT 24 Aug 01 06:23:50 PM PDT 24 388003771 ps
T798 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.716763274 Aug 01 06:24:09 PM PDT 24 Aug 01 06:24:11 PM PDT 24 396730920 ps
T85 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3151469310 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:05 PM PDT 24 601409206 ps
T72 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1149728087 Aug 01 06:23:44 PM PDT 24 Aug 01 06:23:47 PM PDT 24 2474411199 ps
T105 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1550494139 Aug 01 06:23:52 PM PDT 24 Aug 01 06:23:54 PM PDT 24 363867351 ps
T145 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3186814591 Aug 01 06:23:41 PM PDT 24 Aug 01 06:24:03 PM PDT 24 25925016103 ps
T140 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1184362387 Aug 01 06:23:50 PM PDT 24 Aug 01 06:23:52 PM PDT 24 2504263696 ps
T141 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3722280007 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:51 PM PDT 24 2358590327 ps
T106 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1409362904 Aug 01 06:23:47 PM PDT 24 Aug 01 06:23:50 PM PDT 24 547276233 ps
T142 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2353776703 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:04 PM PDT 24 485524915 ps
T77 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1665992614 Aug 01 06:23:55 PM PDT 24 Aug 01 06:23:59 PM PDT 24 4822806671 ps
T799 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.678283280 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:05 PM PDT 24 333582781 ps
T126 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.221117720 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:06 PM PDT 24 545596498 ps
T80 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2493292672 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:49 PM PDT 24 8983124427 ps
T800 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.705464434 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:42 PM PDT 24 468923952 ps
T801 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3129511824 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:03 PM PDT 24 291249470 ps
T143 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3359513967 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:44 PM PDT 24 2305108993 ps
T802 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3734522216 Aug 01 06:23:49 PM PDT 24 Aug 01 06:23:50 PM PDT 24 313151840 ps
T803 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2808903778 Aug 01 06:23:37 PM PDT 24 Aug 01 06:23:38 PM PDT 24 373568729 ps
T804 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2295373770 Aug 01 06:24:07 PM PDT 24 Aug 01 06:24:09 PM PDT 24 436508820 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3403811686 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:45 PM PDT 24 1422263071 ps
T805 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1530412034 Aug 01 06:23:58 PM PDT 24 Aug 01 06:23:59 PM PDT 24 647945344 ps
T806 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.669772638 Aug 01 06:24:06 PM PDT 24 Aug 01 06:24:18 PM PDT 24 487121333 ps
T144 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1577235964 Aug 01 06:23:52 PM PDT 24 Aug 01 06:23:56 PM PDT 24 4517905111 ps
T807 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.904004280 Aug 01 06:23:44 PM PDT 24 Aug 01 06:23:45 PM PDT 24 445976604 ps
T808 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.625026673 Aug 01 06:24:06 PM PDT 24 Aug 01 06:24:22 PM PDT 24 4796136623 ps
T809 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3734633584 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:04 PM PDT 24 513826536 ps
T810 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1673970472 Aug 01 06:23:45 PM PDT 24 Aug 01 06:23:46 PM PDT 24 576635137 ps
T811 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.707674874 Aug 01 06:23:52 PM PDT 24 Aug 01 06:23:53 PM PDT 24 342618243 ps
T812 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1520835803 Aug 01 06:24:00 PM PDT 24 Aug 01 06:24:02 PM PDT 24 287082176 ps
T813 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2406862932 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:46 PM PDT 24 1186454988 ps
T814 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2504719335 Aug 01 06:23:49 PM PDT 24 Aug 01 06:23:53 PM PDT 24 4922311643 ps
T815 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1376386915 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 352218215 ps
T91 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2822589289 Aug 01 06:23:51 PM PDT 24 Aug 01 06:23:55 PM PDT 24 522498113 ps
T816 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2052994948 Aug 01 06:24:05 PM PDT 24 Aug 01 06:24:06 PM PDT 24 287622782 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2036715180 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:44 PM PDT 24 346646085 ps
T817 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.746985398 Aug 01 06:23:59 PM PDT 24 Aug 01 06:24:02 PM PDT 24 422092823 ps
T818 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3890055320 Aug 01 06:23:43 PM PDT 24 Aug 01 06:23:56 PM PDT 24 26791965811 ps
T819 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2250831986 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:45 PM PDT 24 877422038 ps
T820 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2539725939 Aug 01 06:23:58 PM PDT 24 Aug 01 06:23:59 PM PDT 24 362977623 ps
T821 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.855415771 Aug 01 06:23:57 PM PDT 24 Aug 01 06:24:01 PM PDT 24 4798993103 ps
T822 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3387206620 Aug 01 06:23:29 PM PDT 24 Aug 01 06:23:30 PM PDT 24 518608839 ps
T92 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1154398097 Aug 01 06:24:01 PM PDT 24 Aug 01 06:24:15 PM PDT 24 8920799039 ps
T823 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3343214653 Aug 01 06:23:36 PM PDT 24 Aug 01 06:23:39 PM PDT 24 4894838143 ps
T129 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2623137840 Aug 01 06:23:30 PM PDT 24 Aug 01 06:23:32 PM PDT 24 859597605 ps
T824 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3892601601 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:44 PM PDT 24 366483699 ps
T89 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1263868360 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:43 PM PDT 24 885887017 ps
T825 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2810131787 Aug 01 06:24:08 PM PDT 24 Aug 01 06:24:13 PM PDT 24 474988398 ps
T826 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.666778911 Aug 01 06:24:01 PM PDT 24 Aug 01 06:24:02 PM PDT 24 322807338 ps
T827 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2455498874 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:06 PM PDT 24 500614633 ps
T828 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3785264776 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:04 PM PDT 24 292291306 ps
T829 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2445959434 Aug 01 06:24:06 PM PDT 24 Aug 01 06:24:08 PM PDT 24 503597916 ps
T830 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.505627969 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 390942529 ps
T130 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.923129087 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:03 PM PDT 24 570176969 ps
T831 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4058064701 Aug 01 06:24:05 PM PDT 24 Aug 01 06:24:06 PM PDT 24 496315850 ps
T832 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.215976840 Aug 01 06:23:43 PM PDT 24 Aug 01 06:23:54 PM PDT 24 4507575831 ps
T833 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3296316914 Aug 01 06:23:55 PM PDT 24 Aug 01 06:23:56 PM PDT 24 782647829 ps
T834 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3459431614 Aug 01 06:24:09 PM PDT 24 Aug 01 06:24:10 PM PDT 24 462364140 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.535414576 Aug 01 06:23:50 PM PDT 24 Aug 01 06:23:51 PM PDT 24 393639850 ps
T836 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.892641742 Aug 01 06:23:55 PM PDT 24 Aug 01 06:23:57 PM PDT 24 427074453 ps
T837 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1948300486 Aug 01 06:23:54 PM PDT 24 Aug 01 06:23:56 PM PDT 24 489959334 ps
T838 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1652700394 Aug 01 06:23:53 PM PDT 24 Aug 01 06:23:55 PM PDT 24 591958134 ps
T131 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2330355575 Aug 01 06:23:48 PM PDT 24 Aug 01 06:23:52 PM PDT 24 1184921648 ps
T839 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2635535165 Aug 01 06:23:35 PM PDT 24 Aug 01 06:23:38 PM PDT 24 471383572 ps
T840 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3363011618 Aug 01 06:24:07 PM PDT 24 Aug 01 06:24:08 PM PDT 24 498521667 ps
T841 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1058995369 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:45 PM PDT 24 911623332 ps
T842 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.977318118 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 288462261 ps
T843 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1615136138 Aug 01 06:24:06 PM PDT 24 Aug 01 06:24:14 PM PDT 24 2059176488 ps
T90 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.213464959 Aug 01 06:23:44 PM PDT 24 Aug 01 06:23:46 PM PDT 24 423190808 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2587065643 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:45 PM PDT 24 454787035 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3571129475 Aug 01 06:23:40 PM PDT 24 Aug 01 06:23:51 PM PDT 24 4550283131 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2359448727 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:46 PM PDT 24 2478373651 ps
T847 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2032511144 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:05 PM PDT 24 380848585 ps
T848 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.607006069 Aug 01 06:23:51 PM PDT 24 Aug 01 06:23:55 PM PDT 24 4846287862 ps
T849 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.429381430 Aug 01 06:23:30 PM PDT 24 Aug 01 06:23:32 PM PDT 24 398175882 ps
T132 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3362891270 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:42 PM PDT 24 527327612 ps
T850 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3885795240 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:43 PM PDT 24 363768242 ps
T851 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1569229130 Aug 01 06:24:10 PM PDT 24 Aug 01 06:24:12 PM PDT 24 490277310 ps
T852 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1072528652 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:42 PM PDT 24 700223848 ps
T853 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1745062702 Aug 01 06:24:08 PM PDT 24 Aug 01 06:24:09 PM PDT 24 445214871 ps
T854 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3471042647 Aug 01 06:23:40 PM PDT 24 Aug 01 06:23:52 PM PDT 24 26930956331 ps
T855 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.438050876 Aug 01 06:24:05 PM PDT 24 Aug 01 06:24:12 PM PDT 24 515241040 ps
T856 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.172093063 Aug 01 06:24:05 PM PDT 24 Aug 01 06:24:07 PM PDT 24 352192879 ps
T857 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.89635063 Aug 01 06:23:43 PM PDT 24 Aug 01 06:23:44 PM PDT 24 542043665 ps
T133 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2947070961 Aug 01 06:23:37 PM PDT 24 Aug 01 06:23:39 PM PDT 24 563105122 ps
T344 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1121354662 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:06 PM PDT 24 4069821065 ps
T858 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3736047743 Aug 01 06:24:05 PM PDT 24 Aug 01 06:24:06 PM PDT 24 420686492 ps
T859 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.518988390 Aug 01 06:23:39 PM PDT 24 Aug 01 06:23:42 PM PDT 24 4491700586 ps
T860 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2779668514 Aug 01 06:24:06 PM PDT 24 Aug 01 06:24:08 PM PDT 24 481473937 ps
T134 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4038402061 Aug 01 06:23:42 PM PDT 24 Aug 01 06:24:06 PM PDT 24 43484377212 ps
T861 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2627636191 Aug 01 06:23:33 PM PDT 24 Aug 01 06:23:35 PM PDT 24 454152237 ps
T862 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3561848375 Aug 01 06:23:54 PM PDT 24 Aug 01 06:23:55 PM PDT 24 376579877 ps
T863 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3545369839 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:05 PM PDT 24 296596124 ps
T864 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.710794074 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:02 PM PDT 24 575139602 ps
T865 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3242458963 Aug 01 06:23:38 PM PDT 24 Aug 01 06:23:39 PM PDT 24 368054563 ps
T866 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2618507125 Aug 01 06:24:01 PM PDT 24 Aug 01 06:24:02 PM PDT 24 389283639 ps
T93 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4102147590 Aug 01 06:23:50 PM PDT 24 Aug 01 06:24:10 PM PDT 24 8326623435 ps
T135 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2306900240 Aug 01 06:23:34 PM PDT 24 Aug 01 06:23:37 PM PDT 24 813588923 ps
T343 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2802439196 Aug 01 06:23:52 PM PDT 24 Aug 01 06:24:04 PM PDT 24 8218381538 ps
T867 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2484673837 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:16 PM PDT 24 4410371120 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2459501799 Aug 01 06:23:49 PM PDT 24 Aug 01 06:23:50 PM PDT 24 534096150 ps
T869 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2928920223 Aug 01 06:23:54 PM PDT 24 Aug 01 06:23:56 PM PDT 24 452934410 ps
T870 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.144540572 Aug 01 06:23:55 PM PDT 24 Aug 01 06:23:57 PM PDT 24 496694565 ps
T871 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1066571354 Aug 01 06:24:00 PM PDT 24 Aug 01 06:24:03 PM PDT 24 543125129 ps
T872 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4263783190 Aug 01 06:23:50 PM PDT 24 Aug 01 06:23:55 PM PDT 24 2244946251 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.613769084 Aug 01 06:23:40 PM PDT 24 Aug 01 06:23:42 PM PDT 24 529549243 ps
T136 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3191510635 Aug 01 06:24:05 PM PDT 24 Aug 01 06:24:06 PM PDT 24 316398408 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3464644528 Aug 01 06:24:01 PM PDT 24 Aug 01 06:24:20 PM PDT 24 7853867302 ps
T875 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.591289735 Aug 01 06:23:44 PM PDT 24 Aug 01 06:23:45 PM PDT 24 405491329 ps
T876 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3317366920 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:04 PM PDT 24 464963522 ps
T877 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2943598880 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:08 PM PDT 24 688151520 ps
T878 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1094373191 Aug 01 06:23:47 PM PDT 24 Aug 01 06:23:55 PM PDT 24 8575583836 ps
T137 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.737409827 Aug 01 06:23:42 PM PDT 24 Aug 01 06:23:45 PM PDT 24 1031769264 ps
T879 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1546729684 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:43 PM PDT 24 386598840 ps
T138 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2090424485 Aug 01 06:23:34 PM PDT 24 Aug 01 06:24:36 PM PDT 24 53244391908 ps
T880 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2636903671 Aug 01 06:23:37 PM PDT 24 Aug 01 06:23:39 PM PDT 24 545733045 ps
T881 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2409788463 Aug 01 06:24:00 PM PDT 24 Aug 01 06:24:02 PM PDT 24 469092924 ps
T882 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2511011131 Aug 01 06:23:59 PM PDT 24 Aug 01 06:24:00 PM PDT 24 494019372 ps
T883 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2696847331 Aug 01 06:24:10 PM PDT 24 Aug 01 06:24:12 PM PDT 24 481952110 ps
T884 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3638325805 Aug 01 06:23:40 PM PDT 24 Aug 01 06:23:44 PM PDT 24 4532465924 ps
T885 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3242118612 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 663695278 ps
T886 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1572795575 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:05 PM PDT 24 795124932 ps
T887 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.469501605 Aug 01 06:24:10 PM PDT 24 Aug 01 06:24:12 PM PDT 24 508033491 ps
T888 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1087126499 Aug 01 06:23:49 PM PDT 24 Aug 01 06:23:50 PM PDT 24 482909232 ps
T889 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2841029595 Aug 01 06:23:49 PM PDT 24 Aug 01 06:23:51 PM PDT 24 336232249 ps
T890 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2411881004 Aug 01 06:23:50 PM PDT 24 Aug 01 06:23:57 PM PDT 24 4311513061 ps
T891 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1809411356 Aug 01 06:23:42 PM PDT 24 Aug 01 06:24:03 PM PDT 24 7272734631 ps
T139 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3009892119 Aug 01 06:23:36 PM PDT 24 Aug 01 06:23:38 PM PDT 24 881302383 ps
T892 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.644163015 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:43 PM PDT 24 574542374 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2770931090 Aug 01 06:23:43 PM PDT 24 Aug 01 06:23:45 PM PDT 24 417185718 ps
T894 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2117786917 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:04 PM PDT 24 366867603 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2246067187 Aug 01 06:23:44 PM PDT 24 Aug 01 06:23:49 PM PDT 24 9262278135 ps
T896 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4100050029 Aug 01 06:24:07 PM PDT 24 Aug 01 06:24:09 PM PDT 24 1846790766 ps
T897 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1397072620 Aug 01 06:24:09 PM PDT 24 Aug 01 06:24:10 PM PDT 24 543148699 ps
T898 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3009305239 Aug 01 06:24:05 PM PDT 24 Aug 01 06:24:08 PM PDT 24 529481978 ps
T899 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.572670075 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 630579119 ps
T900 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3370060436 Aug 01 06:24:02 PM PDT 24 Aug 01 06:24:04 PM PDT 24 522228010 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4093024610 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:05 PM PDT 24 474448261 ps
T902 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3422134855 Aug 01 06:23:41 PM PDT 24 Aug 01 06:23:43 PM PDT 24 468062084 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.289206845 Aug 01 06:23:59 PM PDT 24 Aug 01 06:24:02 PM PDT 24 1226622100 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3355189053 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:17 PM PDT 24 5428513125 ps
T905 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3658981032 Aug 01 06:23:56 PM PDT 24 Aug 01 06:24:16 PM PDT 24 8159552197 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.976838488 Aug 01 06:23:43 PM PDT 24 Aug 01 06:23:44 PM PDT 24 550429112 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2493978556 Aug 01 06:23:52 PM PDT 24 Aug 01 06:23:54 PM PDT 24 377722626 ps
T908 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.941189351 Aug 01 06:23:43 PM PDT 24 Aug 01 06:24:02 PM PDT 24 4935688174 ps
T909 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1349895061 Aug 01 06:23:40 PM PDT 24 Aug 01 06:23:42 PM PDT 24 520031103 ps
T910 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3055720344 Aug 01 06:23:54 PM PDT 24 Aug 01 06:23:55 PM PDT 24 566481397 ps
T911 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3326555181 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:16 PM PDT 24 4816381459 ps
T912 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2421721741 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:06 PM PDT 24 399669221 ps
T913 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1156079047 Aug 01 06:24:03 PM PDT 24 Aug 01 06:24:04 PM PDT 24 482902068 ps
T914 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.20554725 Aug 01 06:24:04 PM PDT 24 Aug 01 06:24:07 PM PDT 24 2151935214 ps
T915 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2702224946 Aug 01 06:23:49 PM PDT 24 Aug 01 06:23:53 PM PDT 24 2989206799 ps
T916 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1594117218 Aug 01 06:24:09 PM PDT 24 Aug 01 06:24:13 PM PDT 24 4527036600 ps
T917 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1306726862 Aug 01 06:24:10 PM PDT 24 Aug 01 06:24:12 PM PDT 24 501009572 ps
T918 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.563189913 Aug 01 06:23:47 PM PDT 24 Aug 01 06:23:49 PM PDT 24 872887982 ps

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3972914839
Short name T5
Test name
Test status
Simulation time 324256302732 ps
CPU time 686.97 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 07:04:42 PM PDT 24
Peak memory 218168 kb
Host smart-18c68de4-4aec-4669-a5be-f7fbbe652668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972914839 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3972914839
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.562460368
Short name T65
Test name
Test status
Simulation time 564300260667 ps
CPU time 318.59 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:57:46 PM PDT 24
Peak memory 201440 kb
Host smart-d5f1f0b6-d7b3-4fed-8e2e-e5b8ba86d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562460368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.562460368
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2258636374
Short name T1
Test name
Test status
Simulation time 58651292433 ps
CPU time 258.02 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:56:05 PM PDT 24
Peak memory 217440 kb
Host smart-a0f12092-2325-49a0-b993-8fc31d4b5f3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258636374 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2258636374
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2688725407
Short name T16
Test name
Test status
Simulation time 183701249326 ps
CPU time 111.58 seconds
Started Aug 01 06:55:55 PM PDT 24
Finished Aug 01 06:57:47 PM PDT 24
Peak memory 210820 kb
Host smart-f7feb6bf-b01a-4ecf-8d31-850505b83ae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688725407 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2688725407
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1959476023
Short name T2
Test name
Test status
Simulation time 405202463527 ps
CPU time 234.24 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 201480 kb
Host smart-a42d044f-fa7c-47f1-861f-54d60371906b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959476023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1959476023
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2475390669
Short name T62
Test name
Test status
Simulation time 104978146924 ps
CPU time 147.12 seconds
Started Aug 01 06:54:26 PM PDT 24
Finished Aug 01 06:56:53 PM PDT 24
Peak memory 217872 kb
Host smart-4b2b3927-c8dd-459c-a4ee-a3ac7879f407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475390669 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2475390669
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1737059932
Short name T155
Test name
Test status
Simulation time 563213340211 ps
CPU time 115.32 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 06:56:51 PM PDT 24
Peak memory 201460 kb
Host smart-01a1dbe2-b122-487a-b36d-fedb89a0570f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737059932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1737059932
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2644539709
Short name T111
Test name
Test status
Simulation time 498273778494 ps
CPU time 283.88 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 06:57:39 PM PDT 24
Peak memory 201472 kb
Host smart-18a3120a-d4c2-4b5f-9dbd-2a850a949aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644539709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2644539709
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2913571130
Short name T198
Test name
Test status
Simulation time 620491577836 ps
CPU time 338.88 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 07:00:07 PM PDT 24
Peak memory 201484 kb
Host smart-eb09c2ef-6272-445d-86de-c1448e9cc098
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913571130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2913571130
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.279222595
Short name T167
Test name
Test status
Simulation time 511604796357 ps
CPU time 1163.26 seconds
Started Aug 01 06:55:56 PM PDT 24
Finished Aug 01 07:15:19 PM PDT 24
Peak memory 201452 kb
Host smart-93d6d35f-2088-4792-b5a5-f3d275f832ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279222595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.279222595
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3247347282
Short name T149
Test name
Test status
Simulation time 350805284554 ps
CPU time 156.35 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 06:54:51 PM PDT 24
Peak memory 201456 kb
Host smart-4670e9be-6ad1-4ca8-a9f8-e5729fcf8f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247347282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3247347282
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3531550106
Short name T81
Test name
Test status
Simulation time 8063459213 ps
CPU time 8.69 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 06:52:05 PM PDT 24
Peak memory 218232 kb
Host smart-68891a7e-1400-4d37-aded-415943b5a37f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531550106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3531550106
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1715120462
Short name T151
Test name
Test status
Simulation time 498083428767 ps
CPU time 743.6 seconds
Started Aug 01 06:53:35 PM PDT 24
Finished Aug 01 07:05:59 PM PDT 24
Peak memory 201508 kb
Host smart-b2ea51da-2d8b-4b47-83e1-2dd996bb2d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715120462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1715120462
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3101987579
Short name T78
Test name
Test status
Simulation time 323732470 ps
CPU time 2.63 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 201588 kb
Host smart-f923fc61-8433-4f84-8bf4-9eb12bd8d47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101987579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3101987579
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3712195864
Short name T61
Test name
Test status
Simulation time 87091712635 ps
CPU time 103.34 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:53:56 PM PDT 24
Peak memory 210148 kb
Host smart-92a627eb-c559-4d6b-9c1e-c63f965a75a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712195864 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3712195864
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2463767744
Short name T33
Test name
Test status
Simulation time 510439486412 ps
CPU time 1182.07 seconds
Started Aug 01 06:52:53 PM PDT 24
Finished Aug 01 07:12:36 PM PDT 24
Peak memory 201448 kb
Host smart-bd0f3b49-dbef-441b-93ad-714d71388d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463767744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2463767744
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3645177566
Short name T276
Test name
Test status
Simulation time 493291966960 ps
CPU time 1200.65 seconds
Started Aug 01 06:53:48 PM PDT 24
Finished Aug 01 07:13:49 PM PDT 24
Peak memory 201540 kb
Host smart-ef098f87-e206-4b5e-a6f4-c10dc4adf1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645177566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3645177566
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2483773482
Short name T73
Test name
Test status
Simulation time 540675063 ps
CPU time 1.96 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:51 PM PDT 24
Peak memory 201304 kb
Host smart-ff815224-adef-4e05-a2bf-4e6d26ad781b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483773482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2483773482
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1463951522
Short name T169
Test name
Test status
Simulation time 536987178709 ps
CPU time 1295.21 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 07:17:53 PM PDT 24
Peak memory 201472 kb
Host smart-896f72a5-5a1b-409d-abd6-3f08a8d93488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463951522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1463951522
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.4206738620
Short name T223
Test name
Test status
Simulation time 525512168454 ps
CPU time 583.99 seconds
Started Aug 01 06:54:57 PM PDT 24
Finished Aug 01 07:04:41 PM PDT 24
Peak memory 201504 kb
Host smart-5d3bb62b-34b8-48e5-b693-67d6b948f674
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206738620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.4206738620
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3282582516
Short name T36
Test name
Test status
Simulation time 533219519812 ps
CPU time 1239.08 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 07:14:04 PM PDT 24
Peak memory 201492 kb
Host smart-6b272d92-6c45-45ae-ad59-a6cf341a5971
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282582516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3282582516
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.42622028
Short name T232
Test name
Test status
Simulation time 467699364756 ps
CPU time 1313.94 seconds
Started Aug 01 06:54:35 PM PDT 24
Finished Aug 01 07:16:30 PM PDT 24
Peak memory 209992 kb
Host smart-1714fcf4-27b4-4eac-94a2-26c606f40492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42622028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.42622028
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3813488828
Short name T17
Test name
Test status
Simulation time 191227483651 ps
CPU time 628.72 seconds
Started Aug 01 06:55:42 PM PDT 24
Finished Aug 01 07:06:11 PM PDT 24
Peak memory 210212 kb
Host smart-caa2ba34-dfc0-4dbb-9c70-394bbbd5306c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813488828 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3813488828
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1608738968
Short name T227
Test name
Test status
Simulation time 447598935619 ps
CPU time 261.98 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:56:49 PM PDT 24
Peak memory 201444 kb
Host smart-53150742-c90f-42a5-8946-10ae8cf3bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608738968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1608738968
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.797555156
Short name T288
Test name
Test status
Simulation time 325544568587 ps
CPU time 179.5 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 06:55:09 PM PDT 24
Peak memory 201356 kb
Host smart-3c45f3fc-b704-4a50-abfc-bbd1f2df65a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797555156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.797555156
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1675978690
Short name T146
Test name
Test status
Simulation time 428011707474 ps
CPU time 670.43 seconds
Started Aug 01 06:55:11 PM PDT 24
Finished Aug 01 07:06:21 PM PDT 24
Peak memory 209952 kb
Host smart-f0b58230-7f04-4ae0-bdb6-2c190b15a520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675978690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1675978690
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3140691055
Short name T200
Test name
Test status
Simulation time 507726946159 ps
CPU time 254.71 seconds
Started Aug 01 06:53:49 PM PDT 24
Finished Aug 01 06:58:03 PM PDT 24
Peak memory 201388 kb
Host smart-898fb5b2-1b22-4f36-8681-429421b6775f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140691055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3140691055
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3360369533
Short name T233
Test name
Test status
Simulation time 506196411744 ps
CPU time 265.12 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:56:25 PM PDT 24
Peak memory 201436 kb
Host smart-86b45b3f-cb87-4da2-b889-6c75c3ea18c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360369533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3360369533
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2468394236
Short name T230
Test name
Test status
Simulation time 531444353204 ps
CPU time 1121.79 seconds
Started Aug 01 06:55:55 PM PDT 24
Finished Aug 01 07:14:37 PM PDT 24
Peak memory 201444 kb
Host smart-97bc6b35-46f1-41c3-9684-5a7aac8532b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468394236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2468394236
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4102147590
Short name T93
Test name
Test status
Simulation time 8326623435 ps
CPU time 20.07 seconds
Started Aug 01 06:23:50 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 201628 kb
Host smart-bfc5e3c5-89e6-4cd5-aab7-a4f64a17b470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102147590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.4102147590
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2748346582
Short name T31
Test name
Test status
Simulation time 320390558459 ps
CPU time 189.84 seconds
Started Aug 01 06:54:46 PM PDT 24
Finished Aug 01 06:57:56 PM PDT 24
Peak memory 201644 kb
Host smart-c08caac0-927d-4704-bbf0-50bc6df9c69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748346582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2748346582
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.4123365337
Short name T88
Test name
Test status
Simulation time 407660201 ps
CPU time 1.52 seconds
Started Aug 01 06:52:42 PM PDT 24
Finished Aug 01 06:52:44 PM PDT 24
Peak memory 201156 kb
Host smart-4755c3c1-189b-42b1-a25f-dbec25d41161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123365337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.4123365337
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2062684738
Short name T221
Test name
Test status
Simulation time 343484205754 ps
CPU time 735.3 seconds
Started Aug 01 06:52:07 PM PDT 24
Finished Aug 01 07:04:22 PM PDT 24
Peak memory 201492 kb
Host smart-95f9fb21-6d58-4eba-8c4b-8d6384d0b120
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062684738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2062684738
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1111586721
Short name T114
Test name
Test status
Simulation time 350774994396 ps
CPU time 289.02 seconds
Started Aug 01 06:53:15 PM PDT 24
Finished Aug 01 06:58:04 PM PDT 24
Peak memory 217644 kb
Host smart-7beda2f3-d337-4bcf-8ccc-80dc52af10a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111586721 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1111586721
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2352977458
Short name T280
Test name
Test status
Simulation time 181328526645 ps
CPU time 115.2 seconds
Started Aug 01 06:55:29 PM PDT 24
Finished Aug 01 06:57:25 PM PDT 24
Peak memory 201420 kb
Host smart-b4850577-c956-477c-be1a-bc7de4a1bfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352977458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2352977458
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1854885668
Short name T231
Test name
Test status
Simulation time 150301168552 ps
CPU time 263.17 seconds
Started Aug 01 06:53:34 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 218092 kb
Host smart-a1c44966-9e67-4302-935b-5bfe96e80d8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854885668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1854885668
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.74572885
Short name T174
Test name
Test status
Simulation time 161311936332 ps
CPU time 354.76 seconds
Started Aug 01 06:54:29 PM PDT 24
Finished Aug 01 07:00:24 PM PDT 24
Peak memory 201440 kb
Host smart-4241d41f-274d-47b5-89ac-c2946770cd9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74572885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt
_fixed.74572885
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3273182375
Short name T38
Test name
Test status
Simulation time 489809377539 ps
CPU time 202.14 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 06:55:18 PM PDT 24
Peak memory 201440 kb
Host smart-5e442a57-e531-4a37-a6e1-ddc28025b207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273182375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3273182375
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1687269928
Short name T217
Test name
Test status
Simulation time 639180036895 ps
CPU time 375.6 seconds
Started Aug 01 06:53:15 PM PDT 24
Finished Aug 01 06:59:30 PM PDT 24
Peak memory 201408 kb
Host smart-f659d989-9f06-40dd-9a4e-46ea843c554f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687269928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1687269928
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2512206277
Short name T211
Test name
Test status
Simulation time 431509669714 ps
CPU time 980.04 seconds
Started Aug 01 06:53:25 PM PDT 24
Finished Aug 01 07:09:45 PM PDT 24
Peak memory 212420 kb
Host smart-cdb8e3be-a0e0-4334-beb2-b23dccaea9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512206277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2512206277
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.821822560
Short name T299
Test name
Test status
Simulation time 328079163873 ps
CPU time 350.8 seconds
Started Aug 01 06:53:27 PM PDT 24
Finished Aug 01 06:59:17 PM PDT 24
Peak memory 201296 kb
Host smart-09de37e1-c789-4e74-9ad1-22eace1ebdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821822560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.821822560
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3872627965
Short name T104
Test name
Test status
Simulation time 227138299630 ps
CPU time 151.83 seconds
Started Aug 01 06:56:37 PM PDT 24
Finished Aug 01 06:59:09 PM PDT 24
Peak memory 209744 kb
Host smart-05dfd65a-2c82-4af3-abc3-a8db9c31d172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872627965 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3872627965
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1316040001
Short name T153
Test name
Test status
Simulation time 544991250783 ps
CPU time 1195.04 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 07:12:04 PM PDT 24
Peak memory 200212 kb
Host smart-a5578bfe-c912-45de-a605-4e7a0663eda5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316040001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1316040001
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1854319642
Short name T228
Test name
Test status
Simulation time 486159108986 ps
CPU time 1008.06 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 07:08:57 PM PDT 24
Peak memory 200236 kb
Host smart-ddca76f8-67ae-4103-b3c8-99413b50a31d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854319642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1854319642
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3771690433
Short name T289
Test name
Test status
Simulation time 357297535654 ps
CPU time 814.24 seconds
Started Aug 01 06:53:57 PM PDT 24
Finished Aug 01 07:07:31 PM PDT 24
Peak memory 201432 kb
Host smart-f15ab18a-07a2-4997-970e-378077214579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771690433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3771690433
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3547447615
Short name T237
Test name
Test status
Simulation time 329060071277 ps
CPU time 752.47 seconds
Started Aug 01 06:55:42 PM PDT 24
Finished Aug 01 07:08:15 PM PDT 24
Peak memory 201448 kb
Host smart-ed693f48-48b0-4581-96b4-0340464fc466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547447615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3547447615
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2575620724
Short name T251
Test name
Test status
Simulation time 372913716698 ps
CPU time 435.29 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 06:59:25 PM PDT 24
Peak memory 201396 kb
Host smart-77f9b05b-31a1-4077-b3e6-60a4ea4cbcff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575620724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2575620724
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.737409827
Short name T137
Test name
Test status
Simulation time 1031769264 ps
CPU time 2.86 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201448 kb
Host smart-b440fac5-0d2e-452b-b5a2-66de1d4b077f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737409827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.737409827
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3213842443
Short name T3
Test name
Test status
Simulation time 108704447799 ps
CPU time 395.99 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:59:11 PM PDT 24
Peak memory 201840 kb
Host smart-34470459-ab91-4b43-9e36-3287fda58b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213842443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3213842443
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2947874533
Short name T279
Test name
Test status
Simulation time 325577533009 ps
CPU time 403.74 seconds
Started Aug 01 06:53:47 PM PDT 24
Finished Aug 01 07:00:31 PM PDT 24
Peak memory 201524 kb
Host smart-37b4960a-b53d-46f7-a495-63d401465894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947874533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2947874533
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.79355774
Short name T234
Test name
Test status
Simulation time 592032589291 ps
CPU time 191.47 seconds
Started Aug 01 06:53:47 PM PDT 24
Finished Aug 01 06:56:59 PM PDT 24
Peak memory 201380 kb
Host smart-562f493c-5393-44c0-af6d-943764c06b4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79355774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_w
akeup.79355774
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3663119437
Short name T218
Test name
Test status
Simulation time 500319502183 ps
CPU time 564.52 seconds
Started Aug 01 06:54:36 PM PDT 24
Finished Aug 01 07:04:00 PM PDT 24
Peak memory 201500 kb
Host smart-3189f88e-c2cd-487e-b98e-537df7b9864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663119437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3663119437
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1851751730
Short name T332
Test name
Test status
Simulation time 337539858466 ps
CPU time 827.25 seconds
Started Aug 01 06:55:54 PM PDT 24
Finished Aug 01 07:09:41 PM PDT 24
Peak memory 201360 kb
Host smart-6c2f9caf-9925-4a88-bb59-986662c153ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851751730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1851751730
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.831606011
Short name T335
Test name
Test status
Simulation time 520590354223 ps
CPU time 1228 seconds
Started Aug 01 06:56:29 PM PDT 24
Finished Aug 01 07:16:57 PM PDT 24
Peak memory 201436 kb
Host smart-5840cdb8-f2de-4f4e-913a-8ee815e9f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831606011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.831606011
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2857309907
Short name T340
Test name
Test status
Simulation time 342955025355 ps
CPU time 65.35 seconds
Started Aug 01 06:56:16 PM PDT 24
Finished Aug 01 06:57:22 PM PDT 24
Peak memory 201512 kb
Host smart-c853f446-38c8-4b00-a2c3-2e2dff4f6719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857309907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2857309907
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3937835474
Short name T24
Test name
Test status
Simulation time 454434699036 ps
CPU time 283.1 seconds
Started Aug 01 06:52:11 PM PDT 24
Finished Aug 01 06:56:55 PM PDT 24
Peak memory 210240 kb
Host smart-62c2a5b2-2f01-4530-ab7c-63c5d485d462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937835474 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3937835474
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1021786232
Short name T303
Test name
Test status
Simulation time 382754370974 ps
CPU time 207.65 seconds
Started Aug 01 06:53:57 PM PDT 24
Finished Aug 01 06:57:25 PM PDT 24
Peak memory 201424 kb
Host smart-af7ee9c7-0e6d-4efc-a90d-02505cb15b1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021786232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1021786232
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2981377495
Short name T71
Test name
Test status
Simulation time 4450065816 ps
CPU time 15.5 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:50 PM PDT 24
Peak memory 201492 kb
Host smart-c45ab0c3-113a-419b-9e9e-706a5b14c52e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981377495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2981377495
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1546087523
Short name T320
Test name
Test status
Simulation time 371989784626 ps
CPU time 202.57 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:55:56 PM PDT 24
Peak memory 201432 kb
Host smart-1e7ba8b9-f275-4ac6-a70d-e02b89ab534e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546087523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1546087523
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3891942597
Short name T248
Test name
Test status
Simulation time 518826558646 ps
CPU time 1159.39 seconds
Started Aug 01 06:51:53 PM PDT 24
Finished Aug 01 07:11:13 PM PDT 24
Peak memory 201436 kb
Host smart-fb8c5530-0d58-4d91-8b99-11930a534348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891942597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3891942597
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3651552871
Short name T291
Test name
Test status
Simulation time 495528223217 ps
CPU time 1131.02 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 07:12:49 PM PDT 24
Peak memory 201452 kb
Host smart-d9530657-cd2a-4723-ae16-3e50f2430636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651552871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3651552871
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.435122422
Short name T269
Test name
Test status
Simulation time 517040531914 ps
CPU time 637.11 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 07:02:34 PM PDT 24
Peak memory 201472 kb
Host smart-60ce683c-8e5d-45fa-9a7a-fdbf1bd6e94f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435122422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.435122422
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.4058925445
Short name T347
Test name
Test status
Simulation time 128545601996 ps
CPU time 390.51 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 201892 kb
Host smart-2cb6ed1f-4ba0-4476-9acb-0bcd9df6bad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058925445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4058925445
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1334416302
Short name T327
Test name
Test status
Simulation time 503848779044 ps
CPU time 1153.99 seconds
Started Aug 01 06:53:10 PM PDT 24
Finished Aug 01 07:12:24 PM PDT 24
Peak memory 201456 kb
Host smart-fe256664-9301-45d5-9217-d8721c3b0412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334416302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1334416302
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2525492622
Short name T706
Test name
Test status
Simulation time 378117257486 ps
CPU time 326.21 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 201428 kb
Host smart-1dd6dc56-649a-49a5-a8f4-1e30d2d7d6e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525492622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2525492622
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.436100027
Short name T309
Test name
Test status
Simulation time 339132952276 ps
CPU time 220.23 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 06:59:10 PM PDT 24
Peak memory 201492 kb
Host smart-1a8b0865-ea7c-40b4-91dc-d6dcf7a96475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436100027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.436100027
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.106596419
Short name T41
Test name
Test status
Simulation time 308850495600 ps
CPU time 441.51 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 07:03:27 PM PDT 24
Peak memory 209968 kb
Host smart-47db2082-caeb-4b20-aed7-68f004240bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106596419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
106596419
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.279828862
Short name T298
Test name
Test status
Simulation time 327675391230 ps
CPU time 76.21 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:57:34 PM PDT 24
Peak memory 201452 kb
Host smart-ed56e3d9-9a13-4882-9690-73e456148968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279828862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.279828862
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2315324947
Short name T314
Test name
Test status
Simulation time 489214852365 ps
CPU time 1149.65 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 07:15:27 PM PDT 24
Peak memory 201428 kb
Host smart-333cc4d0-98ba-4253-a6f2-7e153ecdcf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315324947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2315324947
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2587065643
Short name T844
Test name
Test status
Simulation time 454787035 ps
CPU time 3.11 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201612 kb
Host smart-73231304-4166-4166-a723-eb92993d54d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587065643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2587065643
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3882215836
Short name T301
Test name
Test status
Simulation time 330794034973 ps
CPU time 765.84 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 07:04:29 PM PDT 24
Peak memory 201452 kb
Host smart-5d413f3a-f2fd-4776-83b9-40b9fcf0a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882215836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3882215836
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2859197525
Short name T266
Test name
Test status
Simulation time 588833560154 ps
CPU time 416.73 seconds
Started Aug 01 06:52:12 PM PDT 24
Finished Aug 01 06:59:09 PM PDT 24
Peak memory 201720 kb
Host smart-28f42800-01c3-492f-a264-59f101302afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859197525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2859197525
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.527543033
Short name T101
Test name
Test status
Simulation time 187626141141 ps
CPU time 361.36 seconds
Started Aug 01 06:52:25 PM PDT 24
Finished Aug 01 06:58:26 PM PDT 24
Peak memory 201416 kb
Host smart-adc23508-b984-41c0-adab-90319eed4882
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527543033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.527543033
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2789721290
Short name T294
Test name
Test status
Simulation time 327527459447 ps
CPU time 179.64 seconds
Started Aug 01 06:52:31 PM PDT 24
Finished Aug 01 06:55:31 PM PDT 24
Peak memory 201440 kb
Host smart-e7335d33-2354-4e22-93e4-2dd81e9e28f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789721290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2789721290
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1320883631
Short name T21
Test name
Test status
Simulation time 485459136041 ps
CPU time 247.44 seconds
Started Aug 01 06:52:40 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 210136 kb
Host smart-69b3a65d-a084-4812-bb5d-d7f8c4c33bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320883631 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1320883631
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3679867658
Short name T334
Test name
Test status
Simulation time 327982562993 ps
CPU time 187.49 seconds
Started Aug 01 06:52:57 PM PDT 24
Finished Aug 01 06:56:05 PM PDT 24
Peak memory 201356 kb
Host smart-302c8a3b-430d-45a2-8788-7323e166d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679867658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3679867658
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.45066681
Short name T244
Test name
Test status
Simulation time 170253915837 ps
CPU time 101.7 seconds
Started Aug 01 06:52:56 PM PDT 24
Finished Aug 01 06:54:37 PM PDT 24
Peak memory 201496 kb
Host smart-86214cf2-53b4-40da-ac82-c93b56ba131a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45066681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.45066681
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2179376131
Short name T216
Test name
Test status
Simulation time 314943060516 ps
CPU time 410.63 seconds
Started Aug 01 06:53:48 PM PDT 24
Finished Aug 01 07:00:39 PM PDT 24
Peak memory 201796 kb
Host smart-b742f3e4-1c91-48c1-9cf5-be2a3b7fc680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179376131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2179376131
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1045130327
Short name T275
Test name
Test status
Simulation time 176881540779 ps
CPU time 176.77 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 06:54:53 PM PDT 24
Peak memory 201460 kb
Host smart-bc83baf5-4803-4ffb-9fe0-89e7a3f84952
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045130327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1045130327
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3506991291
Short name T201
Test name
Test status
Simulation time 538648930992 ps
CPU time 224.02 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 06:58:12 PM PDT 24
Peak memory 201344 kb
Host smart-1c1c57ec-e57a-41f0-aabf-05cc8da3511c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506991291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3506991291
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1570582856
Short name T310
Test name
Test status
Simulation time 402213991156 ps
CPU time 899.59 seconds
Started Aug 01 06:54:36 PM PDT 24
Finished Aug 01 07:09:36 PM PDT 24
Peak memory 201424 kb
Host smart-4867582c-93de-4a83-9018-67a45644e394
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570582856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1570582856
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.620885315
Short name T346
Test name
Test status
Simulation time 105904735898 ps
CPU time 351.58 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 06:57:55 PM PDT 24
Peak memory 201824 kb
Host smart-f7ceff8c-25b8-4212-8e00-3ce26d0a00dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620885315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.620885315
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2090424485
Short name T138
Test name
Test status
Simulation time 53244391908 ps
CPU time 61.26 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:24:36 PM PDT 24
Peak memory 201452 kb
Host smart-ac0507a9-5c1e-4688-a1e3-08caa87bb642
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090424485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2090424485
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2306900240
Short name T135
Test name
Test status
Simulation time 813588923 ps
CPU time 2.41 seconds
Started Aug 01 06:23:34 PM PDT 24
Finished Aug 01 06:23:37 PM PDT 24
Peak memory 201244 kb
Host smart-f2491e9e-8569-45d8-b9ea-c5a07604d453
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306900240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2306900240
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.904004280
Short name T807
Test name
Test status
Simulation time 445976604 ps
CPU time 1.35 seconds
Started Aug 01 06:23:44 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201432 kb
Host smart-c043ffe5-1213-4323-95c8-593adc80452e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904004280 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.904004280
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2947070961
Short name T133
Test name
Test status
Simulation time 563105122 ps
CPU time 1.16 seconds
Started Aug 01 06:23:37 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 201324 kb
Host smart-2af1dc3e-fa03-4e56-805a-6abbd7685488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947070961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2947070961
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.89635063
Short name T857
Test name
Test status
Simulation time 542043665 ps
CPU time 0.94 seconds
Started Aug 01 06:23:43 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 201320 kb
Host smart-9d094f0d-764d-429a-8281-0d1191781084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89635063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.89635063
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2359448727
Short name T846
Test name
Test status
Simulation time 2478373651 ps
CPU time 3.31 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:46 PM PDT 24
Peak memory 201396 kb
Host smart-ae187a8f-84ac-4d90-b10e-29f4fccc9b89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359448727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2359448727
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2246067187
Short name T895
Test name
Test status
Simulation time 9262278135 ps
CPU time 4.91 seconds
Started Aug 01 06:23:44 PM PDT 24
Finished Aug 01 06:23:49 PM PDT 24
Peak memory 201584 kb
Host smart-9b944a61-b2c5-4c30-b1ab-2c804e65421b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246067187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2246067187
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3681583819
Short name T125
Test name
Test status
Simulation time 595558286 ps
CPU time 1.76 seconds
Started Aug 01 06:23:43 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201508 kb
Host smart-89ff763a-c7f7-40e3-998b-4a25f9318f38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681583819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3681583819
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3471042647
Short name T854
Test name
Test status
Simulation time 26930956331 ps
CPU time 11.96 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:52 PM PDT 24
Peak memory 201496 kb
Host smart-789f10c7-fd43-4fc3-bb82-7d5a3197f922
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471042647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3471042647
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2250831986
Short name T819
Test name
Test status
Simulation time 877422038 ps
CPU time 2.59 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201272 kb
Host smart-09aaeeba-3236-42df-a6ac-b00ea7a2b6ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250831986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2250831986
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.591289735
Short name T875
Test name
Test status
Simulation time 405491329 ps
CPU time 1.09 seconds
Started Aug 01 06:23:44 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201456 kb
Host smart-fda16668-4f94-4753-8f2c-e5df79b1d4b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591289735 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.591289735
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.613769084
Short name T873
Test name
Test status
Simulation time 529549243 ps
CPU time 1 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 201292 kb
Host smart-29136792-2755-4172-870f-1f0cceaa69f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613769084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.613769084
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3892601601
Short name T824
Test name
Test status
Simulation time 366483699 ps
CPU time 1.46 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 201288 kb
Host smart-319fe67c-860b-409e-b19e-b39cbb3d3026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892601601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3892601601
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2635535165
Short name T839
Test name
Test status
Simulation time 471383572 ps
CPU time 3.2 seconds
Started Aug 01 06:23:35 PM PDT 24
Finished Aug 01 06:23:38 PM PDT 24
Peak memory 217424 kb
Host smart-7959cafa-31fa-4ef1-9075-09a3228f52a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635535165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2635535165
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3571129475
Short name T845
Test name
Test status
Simulation time 4550283131 ps
CPU time 9.99 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:51 PM PDT 24
Peak memory 201596 kb
Host smart-713f9618-90ff-4c09-a61a-ecfebc4c3fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571129475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3571129475
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3296316914
Short name T833
Test name
Test status
Simulation time 782647829 ps
CPU time 0.95 seconds
Started Aug 01 06:23:55 PM PDT 24
Finished Aug 01 06:23:56 PM PDT 24
Peak memory 201472 kb
Host smart-09144b53-aebf-4641-b4fb-6f9e9af05338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296316914 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3296316914
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2117786917
Short name T894
Test name
Test status
Simulation time 366867603 ps
CPU time 1.6 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201244 kb
Host smart-7c0c7710-832c-4727-8b86-79fb79fc7ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117786917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2117786917
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3317366920
Short name T876
Test name
Test status
Simulation time 464963522 ps
CPU time 1.18 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201248 kb
Host smart-f8ab4ea6-20d8-4bf1-9298-bdd4a51629c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317366920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3317366920
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.607006069
Short name T848
Test name
Test status
Simulation time 4846287862 ps
CPU time 3.92 seconds
Started Aug 01 06:23:51 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 201536 kb
Host smart-58c8ee37-b71e-4c60-af70-403009908f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607006069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.607006069
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.746985398
Short name T817
Test name
Test status
Simulation time 422092823 ps
CPU time 2.12 seconds
Started Aug 01 06:23:59 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 201616 kb
Host smart-a57353a4-9315-487d-9531-62294c8afc93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746985398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.746985398
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3658981032
Short name T905
Test name
Test status
Simulation time 8159552197 ps
CPU time 19.66 seconds
Started Aug 01 06:23:56 PM PDT 24
Finished Aug 01 06:24:16 PM PDT 24
Peak memory 201612 kb
Host smart-c537450e-1bd2-441a-9292-16b9729ff671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658981032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3658981032
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1550494139
Short name T105
Test name
Test status
Simulation time 363867351 ps
CPU time 1.63 seconds
Started Aug 01 06:23:52 PM PDT 24
Finished Aug 01 06:23:54 PM PDT 24
Peak memory 201268 kb
Host smart-26c46fd5-5fd6-422b-8e03-d69b3d369325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550494139 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1550494139
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2696847331
Short name T883
Test name
Test status
Simulation time 481952110 ps
CPU time 0.98 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 201320 kb
Host smart-423a59d0-6466-47bb-84a5-f01bb60750ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696847331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2696847331
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2493978556
Short name T907
Test name
Test status
Simulation time 377722626 ps
CPU time 1.07 seconds
Started Aug 01 06:23:52 PM PDT 24
Finished Aug 01 06:23:54 PM PDT 24
Peak memory 201276 kb
Host smart-d607a04a-6025-4c66-9cb7-fedc66d20acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493978556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2493978556
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.855415771
Short name T821
Test name
Test status
Simulation time 4798993103 ps
CPU time 3.7 seconds
Started Aug 01 06:23:57 PM PDT 24
Finished Aug 01 06:24:01 PM PDT 24
Peak memory 201568 kb
Host smart-4ddf1ed6-8f67-455b-875e-12c937016b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855415771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.855415771
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2822589289
Short name T91
Test name
Test status
Simulation time 522498113 ps
CPU time 3.27 seconds
Started Aug 01 06:23:51 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 217568 kb
Host smart-52e1fe2a-8af3-4be0-9487-7323621ea514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822589289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2822589289
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3516708500
Short name T83
Test name
Test status
Simulation time 459703070 ps
CPU time 1.52 seconds
Started Aug 01 06:23:52 PM PDT 24
Finished Aug 01 06:23:53 PM PDT 24
Peak memory 201464 kb
Host smart-e0f5eedb-60cd-46a2-9047-cd86e010a090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516708500 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3516708500
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.535414576
Short name T835
Test name
Test status
Simulation time 393639850 ps
CPU time 1.05 seconds
Started Aug 01 06:23:50 PM PDT 24
Finished Aug 01 06:23:51 PM PDT 24
Peak memory 201328 kb
Host smart-411c4aef-8637-4448-a7d2-4dabc0689d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535414576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.535414576
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1184362387
Short name T140
Test name
Test status
Simulation time 2504263696 ps
CPU time 1.76 seconds
Started Aug 01 06:23:50 PM PDT 24
Finished Aug 01 06:23:52 PM PDT 24
Peak memory 201344 kb
Host smart-7de6eee1-3bef-4f09-94f2-5ab5c13e2a76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184362387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1184362387
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4100050029
Short name T896
Test name
Test status
Simulation time 1846790766 ps
CPU time 2.41 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 210844 kb
Host smart-465cd2b1-6e79-4ae2-9fd1-34450a4a0b43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100050029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4100050029
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2802439196
Short name T343
Test name
Test status
Simulation time 8218381538 ps
CPU time 12.18 seconds
Started Aug 01 06:23:52 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201596 kb
Host smart-45a84d6c-d10c-4473-bb84-a8a457ad0b22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802439196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2802439196
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3242118612
Short name T885
Test name
Test status
Simulation time 663695278 ps
CPU time 1.32 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201396 kb
Host smart-7f8b3474-1b66-4aa5-886d-e42322ffed7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242118612 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3242118612
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.923129087
Short name T130
Test name
Test status
Simulation time 570176969 ps
CPU time 1.21 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:03 PM PDT 24
Peak memory 201336 kb
Host smart-234d8959-0aa9-48a4-a0bf-50a40c06177a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923129087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.923129087
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3129511824
Short name T801
Test name
Test status
Simulation time 291249470 ps
CPU time 1.06 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:03 PM PDT 24
Peak memory 201304 kb
Host smart-492e9afb-1256-4dbd-87e9-4d3165b2114f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129511824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3129511824
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1577235964
Short name T144
Test name
Test status
Simulation time 4517905111 ps
CPU time 4.11 seconds
Started Aug 01 06:23:52 PM PDT 24
Finished Aug 01 06:23:56 PM PDT 24
Peak memory 201568 kb
Host smart-82ed837a-64cb-4c07-b91f-5de84b200123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577235964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1577235964
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1572795575
Short name T886
Test name
Test status
Simulation time 795124932 ps
CPU time 2.76 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:05 PM PDT 24
Peak memory 217788 kb
Host smart-793f30d2-df4b-483f-ba3e-ec500376d83f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572795575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1572795575
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3464644528
Short name T874
Test name
Test status
Simulation time 7853867302 ps
CPU time 19.09 seconds
Started Aug 01 06:24:01 PM PDT 24
Finished Aug 01 06:24:20 PM PDT 24
Peak memory 201560 kb
Host smart-7c377774-f3c2-4da8-9a99-4d17dc8ac9de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464644528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3464644528
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1156079047
Short name T913
Test name
Test status
Simulation time 482902068 ps
CPU time 1.24 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201380 kb
Host smart-38b553c6-931e-40c8-bb00-ff784aa2309d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156079047 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1156079047
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2841029595
Short name T889
Test name
Test status
Simulation time 336232249 ps
CPU time 1.46 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:51 PM PDT 24
Peak memory 201296 kb
Host smart-80c2b3bd-a657-4020-af84-9f0e32440516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841029595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2841029595
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2455498874
Short name T827
Test name
Test status
Simulation time 500614633 ps
CPU time 1.41 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201308 kb
Host smart-4fe116e4-0227-402e-b69f-9ff1c7440052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455498874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2455498874
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2504719335
Short name T814
Test name
Test status
Simulation time 4922311643 ps
CPU time 3.4 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:53 PM PDT 24
Peak memory 201540 kb
Host smart-471e6c79-a961-472f-8b56-db864edd8452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504719335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2504719335
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.469501605
Short name T887
Test name
Test status
Simulation time 508033491 ps
CPU time 1.47 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 201600 kb
Host smart-40ea3403-d6f2-4442-94a6-997fba711231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469501605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.469501605
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1154398097
Short name T92
Test name
Test status
Simulation time 8920799039 ps
CPU time 13.04 seconds
Started Aug 01 06:24:01 PM PDT 24
Finished Aug 01 06:24:15 PM PDT 24
Peak memory 201580 kb
Host smart-fff4fe91-eaf8-4549-aa0c-b25c95482714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154398097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1154398097
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1569229130
Short name T851
Test name
Test status
Simulation time 490277310 ps
CPU time 1.21 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 201448 kb
Host smart-e2091e59-ecd5-4848-9896-24a55e9705d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569229130 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1569229130
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1652700394
Short name T838
Test name
Test status
Simulation time 591958134 ps
CPU time 1.18 seconds
Started Aug 01 06:23:53 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 201300 kb
Host smart-4e3819ee-2b18-4290-860c-ba9d5aa72310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652700394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1652700394
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3734522216
Short name T802
Test name
Test status
Simulation time 313151840 ps
CPU time 1.32 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:50 PM PDT 24
Peak memory 201320 kb
Host smart-c665e11b-7d35-402f-9597-335849cb7654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734522216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3734522216
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2702224946
Short name T915
Test name
Test status
Simulation time 2989206799 ps
CPU time 4.15 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:53 PM PDT 24
Peak memory 201384 kb
Host smart-cb1d525d-2f22-484d-a302-0cd334517199
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702224946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2702224946
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3151469310
Short name T85
Test name
Test status
Simulation time 601409206 ps
CPU time 2.39 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:05 PM PDT 24
Peak memory 201640 kb
Host smart-b3db3b6e-87c4-4f09-8e5d-11162baf39a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151469310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3151469310
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3326555181
Short name T911
Test name
Test status
Simulation time 4816381459 ps
CPU time 13.17 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:16 PM PDT 24
Peak memory 201520 kb
Host smart-03eef4c7-a24a-4d7c-a4aa-79af4da313db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326555181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3326555181
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1530412034
Short name T805
Test name
Test status
Simulation time 647945344 ps
CPU time 0.97 seconds
Started Aug 01 06:23:58 PM PDT 24
Finished Aug 01 06:23:59 PM PDT 24
Peak memory 201452 kb
Host smart-e8014777-3efd-4c7d-a3ba-e70c50768583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530412034 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1530412034
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2353776703
Short name T142
Test name
Test status
Simulation time 485524915 ps
CPU time 0.82 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201304 kb
Host smart-40c29333-c8f9-4359-b33e-79d6a3958463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353776703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2353776703
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1520835803
Short name T812
Test name
Test status
Simulation time 287082176 ps
CPU time 1.32 seconds
Started Aug 01 06:24:00 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 201268 kb
Host smart-6d8b2c07-e422-4a5a-b0b6-4478ef3de11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520835803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1520835803
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3355189053
Short name T904
Test name
Test status
Simulation time 5428513125 ps
CPU time 12.12 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:17 PM PDT 24
Peak memory 201400 kb
Host smart-e38c95fa-cdc0-484d-abcb-77bd07141592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355189053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3355189053
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2943598880
Short name T877
Test name
Test status
Simulation time 688151520 ps
CPU time 3.12 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 209708 kb
Host smart-bab288cb-97af-485b-a631-6fa32e54841b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943598880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2943598880
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1665992614
Short name T77
Test name
Test status
Simulation time 4822806671 ps
CPU time 4.05 seconds
Started Aug 01 06:23:55 PM PDT 24
Finished Aug 01 06:23:59 PM PDT 24
Peak memory 201556 kb
Host smart-d89b0190-41ce-460e-accb-4531722bfdad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665992614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1665992614
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.438050876
Short name T855
Test name
Test status
Simulation time 515241040 ps
CPU time 1.04 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 201440 kb
Host smart-8e3ea616-c26d-4082-98b4-a0a3f3af7686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438050876 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.438050876
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.221117720
Short name T126
Test name
Test status
Simulation time 545596498 ps
CPU time 2 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201336 kb
Host smart-45ec4e5c-91b3-479e-8836-bff6ac4ab968
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221117720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.221117720
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3734633584
Short name T809
Test name
Test status
Simulation time 513826536 ps
CPU time 1.91 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201232 kb
Host smart-84e28318-f36e-4840-9c9a-7738a770ad7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734633584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3734633584
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.625026673
Short name T808
Test name
Test status
Simulation time 4796136623 ps
CPU time 10.12 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:22 PM PDT 24
Peak memory 201536 kb
Host smart-88aa9a31-b5b6-4cf3-8e53-6d1996e71e19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625026673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.625026673
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2409788463
Short name T881
Test name
Test status
Simulation time 469092924 ps
CPU time 1.5 seconds
Started Aug 01 06:24:00 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 201616 kb
Host smart-e2337c66-afd0-4a0e-b1b5-dabad4628b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409788463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2409788463
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2397670014
Short name T75
Test name
Test status
Simulation time 8482846827 ps
CPU time 8.68 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 201524 kb
Host smart-38905a07-5714-4dda-b101-4de61803dde6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397670014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2397670014
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1066571354
Short name T871
Test name
Test status
Simulation time 543125129 ps
CPU time 2.2 seconds
Started Aug 01 06:24:00 PM PDT 24
Finished Aug 01 06:24:03 PM PDT 24
Peak memory 201468 kb
Host smart-d9d44501-1cc8-415c-9a5e-d2a62fcaff04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066571354 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1066571354
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3191510635
Short name T136
Test name
Test status
Simulation time 316398408 ps
CPU time 1.61 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201312 kb
Host smart-cd87f7db-7d2d-4330-8b23-7cb8112ba7b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191510635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3191510635
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4093024610
Short name T901
Test name
Test status
Simulation time 474448261 ps
CPU time 0.92 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:05 PM PDT 24
Peak memory 201296 kb
Host smart-a89e8d27-7616-466e-b164-976ddfab5194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093024610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4093024610
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.20554725
Short name T914
Test name
Test status
Simulation time 2151935214 ps
CPU time 3.22 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:07 PM PDT 24
Peak memory 201340 kb
Host smart-9f59e55b-9946-4b39-b6ea-dcb97772f7a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20554725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ct
rl_same_csr_outstanding.20554725
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3465703872
Short name T79
Test name
Test status
Simulation time 379516430 ps
CPU time 1.36 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201636 kb
Host smart-67705760-95b4-4be3-862e-aeb33a85f6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465703872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3465703872
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2484673837
Short name T867
Test name
Test status
Simulation time 4410371120 ps
CPU time 11.76 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:16 PM PDT 24
Peak memory 201588 kb
Host smart-cf43e2a2-5434-4050-9be0-596984e9aa08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484673837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2484673837
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.669772638
Short name T806
Test name
Test status
Simulation time 487121333 ps
CPU time 1.24 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:18 PM PDT 24
Peak memory 201448 kb
Host smart-c80f70b5-abab-4307-9055-8c5967b4a2f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669772638 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.669772638
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2421721741
Short name T912
Test name
Test status
Simulation time 399669221 ps
CPU time 1.73 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201308 kb
Host smart-985f173e-091c-43f6-860b-49b3f1f2a666
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421721741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2421721741
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2810131787
Short name T825
Test name
Test status
Simulation time 474988398 ps
CPU time 1.15 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:13 PM PDT 24
Peak memory 201324 kb
Host smart-6438cfad-4805-40a4-b50a-b925f8d58ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810131787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2810131787
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1615136138
Short name T843
Test name
Test status
Simulation time 2059176488 ps
CPU time 2.87 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:14 PM PDT 24
Peak memory 201320 kb
Host smart-6dd300ad-b268-45fd-bec3-5fcee420b82d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615136138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1615136138
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3009305239
Short name T898
Test name
Test status
Simulation time 529481978 ps
CPU time 2.69 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 201596 kb
Host smart-e6207c7a-ebbd-4bbb-8363-c7f838080bac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009305239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3009305239
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1594117218
Short name T916
Test name
Test status
Simulation time 4527036600 ps
CPU time 3.89 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:13 PM PDT 24
Peak memory 201584 kb
Host smart-95c2d775-72ce-4289-851a-3db4406e649a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594117218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1594117218
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3009892119
Short name T139
Test name
Test status
Simulation time 881302383 ps
CPU time 1.96 seconds
Started Aug 01 06:23:36 PM PDT 24
Finished Aug 01 06:23:38 PM PDT 24
Peak memory 201488 kb
Host smart-794235ee-2f4e-40a8-9f31-415b69cb51b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009892119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3009892119
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4038402061
Short name T134
Test name
Test status
Simulation time 43484377212 ps
CPU time 24.21 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201492 kb
Host smart-c2527029-d40c-45a7-a9b2-a675a4789b03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038402061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4038402061
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.563189913
Short name T918
Test name
Test status
Simulation time 872887982 ps
CPU time 1.65 seconds
Started Aug 01 06:23:47 PM PDT 24
Finished Aug 01 06:23:49 PM PDT 24
Peak memory 201304 kb
Host smart-4f667fc6-8350-4059-82ba-2f02199361b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563189913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.563189913
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.213464959
Short name T90
Test name
Test status
Simulation time 423190808 ps
CPU time 1.85 seconds
Started Aug 01 06:23:44 PM PDT 24
Finished Aug 01 06:23:46 PM PDT 24
Peak memory 201404 kb
Host smart-96f78c8d-a175-4f6a-8864-21816bed3ce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213464959 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.213464959
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2036715180
Short name T128
Test name
Test status
Simulation time 346646085 ps
CPU time 0.94 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 201328 kb
Host smart-0d74b02d-3e73-40a2-ae9d-82a0606d1d1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036715180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2036715180
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2770931090
Short name T893
Test name
Test status
Simulation time 417185718 ps
CPU time 1.49 seconds
Started Aug 01 06:23:43 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201260 kb
Host smart-742ac252-f0cd-4fe9-b45b-70dae02820cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770931090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2770931090
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3343214653
Short name T823
Test name
Test status
Simulation time 4894838143 ps
CPU time 3.32 seconds
Started Aug 01 06:23:36 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 201488 kb
Host smart-df10b9b5-3b06-4f7b-9314-c0badcd535f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343214653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3343214653
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.644163015
Short name T892
Test name
Test status
Simulation time 574542374 ps
CPU time 1.35 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 201596 kb
Host smart-b9e36fd6-1e95-4e10-998b-65cb0eb227a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644163015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.644163015
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.215976840
Short name T832
Test name
Test status
Simulation time 4507575831 ps
CPU time 11.62 seconds
Started Aug 01 06:23:43 PM PDT 24
Finished Aug 01 06:23:54 PM PDT 24
Peak memory 201608 kb
Host smart-f9880d8a-c520-47d5-ad23-d789b6d739c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215976840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.215976840
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2445959434
Short name T829
Test name
Test status
Simulation time 503597916 ps
CPU time 1.59 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 201316 kb
Host smart-77a68dbd-5871-4db3-9999-60cf3f370d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445959434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2445959434
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4058064701
Short name T831
Test name
Test status
Simulation time 496315850 ps
CPU time 0.67 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201328 kb
Host smart-35ec8818-8187-4764-9e3c-2aa8449777bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058064701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4058064701
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1745062702
Short name T853
Test name
Test status
Simulation time 445214871 ps
CPU time 1.11 seconds
Started Aug 01 06:24:08 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 201292 kb
Host smart-a2bcea3b-89dc-45ec-996b-0cf4de32eb7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745062702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1745062702
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2539725939
Short name T820
Test name
Test status
Simulation time 362977623 ps
CPU time 1.16 seconds
Started Aug 01 06:23:58 PM PDT 24
Finished Aug 01 06:23:59 PM PDT 24
Peak memory 201312 kb
Host smart-1900b951-65ba-4517-84fa-df6a278ba517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539725939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2539725939
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3785264776
Short name T828
Test name
Test status
Simulation time 292291306 ps
CPU time 1.28 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201276 kb
Host smart-5e40a20c-38c7-438e-8d99-49d1f3f7e4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785264776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3785264776
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4137863490
Short name T797
Test name
Test status
Simulation time 512594662 ps
CPU time 0.96 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201256 kb
Host smart-d6299b4e-e912-4d41-9aeb-4b73e1cc632a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137863490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4137863490
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3363011618
Short name T840
Test name
Test status
Simulation time 498521667 ps
CPU time 1.18 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 201340 kb
Host smart-f3e9b4f6-6851-456f-aabd-938c26a29241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363011618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3363011618
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2295373770
Short name T804
Test name
Test status
Simulation time 436508820 ps
CPU time 1.55 seconds
Started Aug 01 06:24:07 PM PDT 24
Finished Aug 01 06:24:09 PM PDT 24
Peak memory 201256 kb
Host smart-5c4716fb-f824-4027-ad8a-805aa2bd5169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295373770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2295373770
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.977318118
Short name T842
Test name
Test status
Simulation time 288462261 ps
CPU time 0.91 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201256 kb
Host smart-94db4b0e-527c-4e1b-a3ba-96a8d674c032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977318118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.977318118
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3545369839
Short name T863
Test name
Test status
Simulation time 296596124 ps
CPU time 1.29 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:05 PM PDT 24
Peak memory 201300 kb
Host smart-16258f88-0fc8-4fb1-bcd9-50b7d6e6f3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545369839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3545369839
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3403811686
Short name T127
Test name
Test status
Simulation time 1422263071 ps
CPU time 3.06 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201508 kb
Host smart-dde22d5b-e39d-4dc7-812b-e8374cc03ae1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403811686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3403811686
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3186814591
Short name T145
Test name
Test status
Simulation time 25925016103 ps
CPU time 21.66 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:24:03 PM PDT 24
Peak memory 201544 kb
Host smart-9b2ec00c-5e50-41d6-acd7-94cd5f0e5c82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186814591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3186814591
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2406862932
Short name T813
Test name
Test status
Simulation time 1186454988 ps
CPU time 3.45 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:46 PM PDT 24
Peak memory 201304 kb
Host smart-a21d2903-c4d9-456a-9e5d-6b7f38beb1b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406862932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2406862932
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1349895061
Short name T909
Test name
Test status
Simulation time 520031103 ps
CPU time 1.08 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 201468 kb
Host smart-be0d5be9-5d46-4268-9084-981f6c56af8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349895061 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1349895061
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3387206620
Short name T822
Test name
Test status
Simulation time 518608839 ps
CPU time 0.91 seconds
Started Aug 01 06:23:29 PM PDT 24
Finished Aug 01 06:23:30 PM PDT 24
Peak memory 201264 kb
Host smart-e9e5863b-f33d-4d9e-9718-54478bbb4e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387206620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3387206620
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2808903778
Short name T803
Test name
Test status
Simulation time 373568729 ps
CPU time 0.82 seconds
Started Aug 01 06:23:37 PM PDT 24
Finished Aug 01 06:23:38 PM PDT 24
Peak memory 201296 kb
Host smart-5a5b5750-104d-47fa-a994-261ffafa9c6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808903778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2808903778
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3722280007
Short name T141
Test name
Test status
Simulation time 2358590327 ps
CPU time 8.78 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:51 PM PDT 24
Peak memory 201388 kb
Host smart-0af22672-efac-4ecb-98f9-630ea0cc25b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722280007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3722280007
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1072528652
Short name T852
Test name
Test status
Simulation time 700223848 ps
CPU time 1.19 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 201640 kb
Host smart-ab79aeef-70a6-4613-90e2-0d99ada7934c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072528652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1072528652
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1094373191
Short name T878
Test name
Test status
Simulation time 8575583836 ps
CPU time 7.61 seconds
Started Aug 01 06:23:47 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 201632 kb
Host smart-a51ede27-7cf1-4099-bcce-ff72f665e890
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094373191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1094373191
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3736047743
Short name T858
Test name
Test status
Simulation time 420686492 ps
CPU time 0.7 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201316 kb
Host smart-cf805a6a-ecdb-477e-9b5d-2a92b5676858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736047743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3736047743
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1306726862
Short name T917
Test name
Test status
Simulation time 501009572 ps
CPU time 1.76 seconds
Started Aug 01 06:24:10 PM PDT 24
Finished Aug 01 06:24:12 PM PDT 24
Peak memory 201300 kb
Host smart-0f8aac58-7034-41fb-88c6-1c4340becb15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306726862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1306726862
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3459431614
Short name T834
Test name
Test status
Simulation time 462364140 ps
CPU time 0.9 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 201264 kb
Host smart-87d3b288-903d-45b3-817f-846bc650e280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459431614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3459431614
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1397072620
Short name T897
Test name
Test status
Simulation time 543148699 ps
CPU time 0.79 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:10 PM PDT 24
Peak memory 201256 kb
Host smart-1a56c045-f1c3-46d3-ac47-52fd3aac21e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397072620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1397072620
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.678283280
Short name T799
Test name
Test status
Simulation time 333582781 ps
CPU time 0.97 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:05 PM PDT 24
Peak memory 201256 kb
Host smart-d0cd71c4-03b2-40df-80b5-608fb4e1890d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678283280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.678283280
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2618507125
Short name T866
Test name
Test status
Simulation time 389283639 ps
CPU time 0.71 seconds
Started Aug 01 06:24:01 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 201288 kb
Host smart-e312a67e-d721-4bce-bc1b-5add57e7128f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618507125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2618507125
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2511011131
Short name T882
Test name
Test status
Simulation time 494019372 ps
CPU time 0.92 seconds
Started Aug 01 06:23:59 PM PDT 24
Finished Aug 01 06:24:00 PM PDT 24
Peak memory 201264 kb
Host smart-1cc41d9a-9111-418a-b4fb-f7077488da98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511011131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2511011131
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.505627969
Short name T830
Test name
Test status
Simulation time 390942529 ps
CPU time 0.88 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201260 kb
Host smart-4ddc5b5b-1c2e-4e31-bab3-94d8591be146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505627969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.505627969
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.572670075
Short name T899
Test name
Test status
Simulation time 630579119 ps
CPU time 0.83 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201348 kb
Host smart-c8665cf0-faa0-4295-ba63-619ddb23216d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572670075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.572670075
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1948300486
Short name T837
Test name
Test status
Simulation time 489959334 ps
CPU time 1.68 seconds
Started Aug 01 06:23:54 PM PDT 24
Finished Aug 01 06:23:56 PM PDT 24
Peak memory 201328 kb
Host smart-93d490d1-4a43-4b96-bb7c-b60d89a252b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948300486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1948300486
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2330355575
Short name T131
Test name
Test status
Simulation time 1184921648 ps
CPU time 4.65 seconds
Started Aug 01 06:23:48 PM PDT 24
Finished Aug 01 06:23:52 PM PDT 24
Peak memory 201504 kb
Host smart-c61d4e0a-0a1b-4c33-9fae-e0d264c0abd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330355575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2330355575
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3890055320
Short name T818
Test name
Test status
Simulation time 26791965811 ps
CPU time 13.19 seconds
Started Aug 01 06:23:43 PM PDT 24
Finished Aug 01 06:23:56 PM PDT 24
Peak memory 201576 kb
Host smart-7a4a3a54-8f52-4d3a-af3e-95af8e801aaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890055320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3890055320
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2623137840
Short name T129
Test name
Test status
Simulation time 859597605 ps
CPU time 1.72 seconds
Started Aug 01 06:23:30 PM PDT 24
Finished Aug 01 06:23:32 PM PDT 24
Peak memory 201240 kb
Host smart-19eab5d3-ec65-4c5b-86ca-57f7e3b8adf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623137840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2623137840
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2636903671
Short name T880
Test name
Test status
Simulation time 545733045 ps
CPU time 1.36 seconds
Started Aug 01 06:23:37 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 201492 kb
Host smart-a7b79bf4-4bc2-4366-a3d4-94b17350e016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636903671 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2636903671
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3362891270
Short name T132
Test name
Test status
Simulation time 527327612 ps
CPU time 0.99 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 201276 kb
Host smart-d27193bc-23c4-4535-a3cd-ffe124d6d585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362891270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3362891270
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3885795240
Short name T850
Test name
Test status
Simulation time 363768242 ps
CPU time 1.45 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 201268 kb
Host smart-63fd6497-4f7f-4c62-aeaa-fa297d0853fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885795240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3885795240
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3359513967
Short name T143
Test name
Test status
Simulation time 2305108993 ps
CPU time 1.88 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 201360 kb
Host smart-bd54c57b-8f32-4008-923c-ce4bbe39b627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359513967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3359513967
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.518988390
Short name T859
Test name
Test status
Simulation time 4491700586 ps
CPU time 3.19 seconds
Started Aug 01 06:23:39 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 201592 kb
Host smart-9244eadb-176d-4e4c-b58b-b51ffe6ff187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518988390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.518988390
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3055720344
Short name T910
Test name
Test status
Simulation time 566481397 ps
CPU time 0.71 seconds
Started Aug 01 06:23:54 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 201336 kb
Host smart-08db7d9b-82b4-4c21-be39-8a457a004347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055720344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3055720344
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.716763274
Short name T798
Test name
Test status
Simulation time 396730920 ps
CPU time 0.89 seconds
Started Aug 01 06:24:09 PM PDT 24
Finished Aug 01 06:24:11 PM PDT 24
Peak memory 201256 kb
Host smart-0831f606-1e6b-4397-a50f-e8020d24e997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716763274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.716763274
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.144540572
Short name T870
Test name
Test status
Simulation time 496694565 ps
CPU time 0.95 seconds
Started Aug 01 06:23:55 PM PDT 24
Finished Aug 01 06:23:57 PM PDT 24
Peak memory 201296 kb
Host smart-b584c24f-447a-4831-b045-7b5f093b5479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144540572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.144540572
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2928920223
Short name T869
Test name
Test status
Simulation time 452934410 ps
CPU time 1.67 seconds
Started Aug 01 06:23:54 PM PDT 24
Finished Aug 01 06:23:56 PM PDT 24
Peak memory 201328 kb
Host smart-ec9e6357-d92d-41b3-a6c5-a10535372125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928920223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2928920223
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1376386915
Short name T815
Test name
Test status
Simulation time 352218215 ps
CPU time 1.37 seconds
Started Aug 01 06:24:03 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201348 kb
Host smart-643b56f0-b23f-4916-a489-f6e5e8ea4ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376386915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1376386915
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.666778911
Short name T826
Test name
Test status
Simulation time 322807338 ps
CPU time 1.34 seconds
Started Aug 01 06:24:01 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 201288 kb
Host smart-9aebd594-9955-46c0-a782-5a1bdc48bb66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666778911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.666778911
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2032511144
Short name T847
Test name
Test status
Simulation time 380848585 ps
CPU time 0.74 seconds
Started Aug 01 06:24:04 PM PDT 24
Finished Aug 01 06:24:05 PM PDT 24
Peak memory 201316 kb
Host smart-3bb0d7d8-258a-4b3f-b958-347a7c18edf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032511144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2032511144
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.710794074
Short name T864
Test name
Test status
Simulation time 575139602 ps
CPU time 0.76 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 201292 kb
Host smart-5cc3cc53-98b3-4fd5-b13e-49314c8a4f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710794074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.710794074
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.892641742
Short name T836
Test name
Test status
Simulation time 427074453 ps
CPU time 1.54 seconds
Started Aug 01 06:23:55 PM PDT 24
Finished Aug 01 06:23:57 PM PDT 24
Peak memory 201284 kb
Host smart-fc3d4906-ebed-46a2-a7da-703bb733240e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892641742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.892641742
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2052994948
Short name T816
Test name
Test status
Simulation time 287622782 ps
CPU time 1.01 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201356 kb
Host smart-922ee6f2-2dd2-4df2-965d-04cebd3c6d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052994948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2052994948
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1673970472
Short name T810
Test name
Test status
Simulation time 576635137 ps
CPU time 1.2 seconds
Started Aug 01 06:23:45 PM PDT 24
Finished Aug 01 06:23:46 PM PDT 24
Peak memory 201468 kb
Host smart-3f40c470-f1b5-4fa1-bc75-971c41e5cab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673970472 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1673970472
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.976838488
Short name T906
Test name
Test status
Simulation time 550429112 ps
CPU time 0.99 seconds
Started Aug 01 06:23:43 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 201248 kb
Host smart-e0c4518b-1d37-480e-bf5e-d6909e6146f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976838488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.976838488
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3242458963
Short name T865
Test name
Test status
Simulation time 368054563 ps
CPU time 1.41 seconds
Started Aug 01 06:23:38 PM PDT 24
Finished Aug 01 06:23:39 PM PDT 24
Peak memory 201284 kb
Host smart-c4fc8670-a3fc-4663-9333-0a33595a627d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242458963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3242458963
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3638325805
Short name T884
Test name
Test status
Simulation time 4532465924 ps
CPU time 3.31 seconds
Started Aug 01 06:23:40 PM PDT 24
Finished Aug 01 06:23:44 PM PDT 24
Peak memory 201576 kb
Host smart-2d400082-794f-45a0-987a-d26bc4fd3980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638325805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3638325805
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1534889864
Short name T84
Test name
Test status
Simulation time 388003771 ps
CPU time 2.46 seconds
Started Aug 01 06:23:48 PM PDT 24
Finished Aug 01 06:23:50 PM PDT 24
Peak memory 209836 kb
Host smart-349b4fed-36d9-4eb3-9cc2-a0fe19c6ba69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534889864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1534889864
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1185807658
Short name T76
Test name
Test status
Simulation time 3800678416 ps
CPU time 10.6 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:53 PM PDT 24
Peak memory 201252 kb
Host smart-d15dbb00-ea3c-48b1-b444-a190edc031b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185807658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1185807658
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.705464434
Short name T800
Test name
Test status
Simulation time 468923952 ps
CPU time 1.24 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:42 PM PDT 24
Peak memory 201468 kb
Host smart-808be843-c299-47cd-869e-59c8a8cacec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705464434 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.705464434
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1546729684
Short name T879
Test name
Test status
Simulation time 386598840 ps
CPU time 1.07 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 201268 kb
Host smart-e476bc63-e2bf-4980-b964-34402aca461b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546729684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1546729684
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2627636191
Short name T861
Test name
Test status
Simulation time 454152237 ps
CPU time 1.72 seconds
Started Aug 01 06:23:33 PM PDT 24
Finished Aug 01 06:23:35 PM PDT 24
Peak memory 201248 kb
Host smart-4cfb6603-086c-4d4c-8270-7d34bf59255c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627636191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2627636191
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.941189351
Short name T908
Test name
Test status
Simulation time 4935688174 ps
CPU time 18.32 seconds
Started Aug 01 06:23:43 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 201496 kb
Host smart-4938e5e8-ade0-4207-9538-fa0b7f176332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941189351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.941189351
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1263868360
Short name T89
Test name
Test status
Simulation time 885887017 ps
CPU time 2.67 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 210332 kb
Host smart-afee86bf-d54b-479a-8688-f2ad44b7a7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263868360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1263868360
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1809411356
Short name T891
Test name
Test status
Simulation time 7272734631 ps
CPU time 20.18 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:24:03 PM PDT 24
Peak memory 201352 kb
Host smart-af30ab1c-f5e5-4b55-8678-274c8283dbe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809411356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1809411356
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1409362904
Short name T106
Test name
Test status
Simulation time 547276233 ps
CPU time 2.38 seconds
Started Aug 01 06:23:47 PM PDT 24
Finished Aug 01 06:23:50 PM PDT 24
Peak memory 201420 kb
Host smart-561197ad-604c-452c-9bb3-68e8efed1b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409362904 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1409362904
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3422134855
Short name T902
Test name
Test status
Simulation time 468062084 ps
CPU time 1.29 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:43 PM PDT 24
Peak memory 201348 kb
Host smart-dab988bb-a393-4403-83ae-f0532ebf5d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422134855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3422134855
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.429381430
Short name T849
Test name
Test status
Simulation time 398175882 ps
CPU time 1.49 seconds
Started Aug 01 06:23:30 PM PDT 24
Finished Aug 01 06:23:32 PM PDT 24
Peak memory 201356 kb
Host smart-108d8e31-05e9-4d2b-9759-12f9da2bdea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429381430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.429381430
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1149728087
Short name T72
Test name
Test status
Simulation time 2474411199 ps
CPU time 2.08 seconds
Started Aug 01 06:23:44 PM PDT 24
Finished Aug 01 06:23:47 PM PDT 24
Peak memory 201380 kb
Host smart-4491d604-8f6a-4d92-ae71-105d5f21d3a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149728087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1149728087
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1058995369
Short name T841
Test name
Test status
Simulation time 911623332 ps
CPU time 2.89 seconds
Started Aug 01 06:23:42 PM PDT 24
Finished Aug 01 06:23:45 PM PDT 24
Peak memory 201564 kb
Host smart-4548805b-dd78-45cb-93fd-0f097ccaeaa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058995369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1058995369
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2493292672
Short name T80
Test name
Test status
Simulation time 8983124427 ps
CPU time 7.8 seconds
Started Aug 01 06:23:41 PM PDT 24
Finished Aug 01 06:23:49 PM PDT 24
Peak memory 201660 kb
Host smart-2bb3430c-011d-4b31-aad0-18115970c387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493292672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2493292672
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2459501799
Short name T868
Test name
Test status
Simulation time 534096150 ps
CPU time 1.43 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:50 PM PDT 24
Peak memory 201412 kb
Host smart-ef9366b2-5459-4f1c-805b-853e9a3026c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459501799 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2459501799
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1087126499
Short name T888
Test name
Test status
Simulation time 482909232 ps
CPU time 0.96 seconds
Started Aug 01 06:23:49 PM PDT 24
Finished Aug 01 06:23:50 PM PDT 24
Peak memory 201320 kb
Host smart-8a534128-1a67-419f-9a45-ec78df83ffc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087126499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1087126499
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.707674874
Short name T811
Test name
Test status
Simulation time 342618243 ps
CPU time 1.04 seconds
Started Aug 01 06:23:52 PM PDT 24
Finished Aug 01 06:23:53 PM PDT 24
Peak memory 201336 kb
Host smart-54459333-c1e2-4c3d-829a-02e50a398df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707674874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.707674874
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4263783190
Short name T872
Test name
Test status
Simulation time 2244946251 ps
CPU time 5.24 seconds
Started Aug 01 06:23:50 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 201368 kb
Host smart-fcb2b212-3bb9-430c-8aa8-ca4703fb87f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263783190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.4263783190
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.289206845
Short name T903
Test name
Test status
Simulation time 1226622100 ps
CPU time 2.7 seconds
Started Aug 01 06:23:59 PM PDT 24
Finished Aug 01 06:24:02 PM PDT 24
Peak memory 210820 kb
Host smart-d11171c1-528c-4662-af89-aae979bb8695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289206845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.289206845
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1121354662
Short name T344
Test name
Test status
Simulation time 4069821065 ps
CPU time 3.93 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:06 PM PDT 24
Peak memory 201576 kb
Host smart-62b83968-1354-4219-b484-7e313990742f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121354662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1121354662
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3561848375
Short name T862
Test name
Test status
Simulation time 376579877 ps
CPU time 1.29 seconds
Started Aug 01 06:23:54 PM PDT 24
Finished Aug 01 06:23:55 PM PDT 24
Peak memory 201440 kb
Host smart-0634684b-ba15-4f8d-9276-e92a4f9b0ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561848375 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3561848375
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3370060436
Short name T900
Test name
Test status
Simulation time 522228010 ps
CPU time 1.97 seconds
Started Aug 01 06:24:02 PM PDT 24
Finished Aug 01 06:24:04 PM PDT 24
Peak memory 201316 kb
Host smart-aea9bd76-172d-45bd-803f-3e70f7e93808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370060436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3370060436
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2779668514
Short name T860
Test name
Test status
Simulation time 481473937 ps
CPU time 1.67 seconds
Started Aug 01 06:24:06 PM PDT 24
Finished Aug 01 06:24:08 PM PDT 24
Peak memory 201276 kb
Host smart-1685a5ad-600f-42e1-943f-178c60215f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779668514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2779668514
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4142045090
Short name T70
Test name
Test status
Simulation time 4879567107 ps
CPU time 2.98 seconds
Started Aug 01 06:23:51 PM PDT 24
Finished Aug 01 06:23:54 PM PDT 24
Peak memory 201540 kb
Host smart-1ac05261-2f93-4818-a8be-39da6fd51aa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142045090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4142045090
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.172093063
Short name T856
Test name
Test status
Simulation time 352192879 ps
CPU time 2.62 seconds
Started Aug 01 06:24:05 PM PDT 24
Finished Aug 01 06:24:07 PM PDT 24
Peak memory 201624 kb
Host smart-faaca3a4-4723-40da-a42f-e5d06acd6da0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172093063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.172093063
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2411881004
Short name T890
Test name
Test status
Simulation time 4311513061 ps
CPU time 6.32 seconds
Started Aug 01 06:23:50 PM PDT 24
Finished Aug 01 06:23:57 PM PDT 24
Peak memory 201588 kb
Host smart-5c2c6e61-787a-4b83-a3be-e640e6ddf142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411881004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2411881004
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1128547992
Short name T703
Test name
Test status
Simulation time 458848924 ps
CPU time 1.66 seconds
Started Aug 01 06:51:45 PM PDT 24
Finished Aug 01 06:51:47 PM PDT 24
Peak memory 201220 kb
Host smart-d56fac47-2f2e-4bb4-8d76-09f9707f43b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128547992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1128547992
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.590756542
Short name T196
Test name
Test status
Simulation time 514821657345 ps
CPU time 296.85 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:56:41 PM PDT 24
Peak memory 201420 kb
Host smart-92575e7f-b25f-4521-a4c6-c2c5c59870c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590756542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.590756542
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1003039601
Short name T282
Test name
Test status
Simulation time 331381253354 ps
CPU time 816.49 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 07:05:23 PM PDT 24
Peak memory 201492 kb
Host smart-bfdf9879-2333-4d9b-b598-9ed9c504dfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003039601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1003039601
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2142706499
Short name T241
Test name
Test status
Simulation time 166145232397 ps
CPU time 46.03 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:52:33 PM PDT 24
Peak memory 201460 kb
Host smart-5dba8868-1f80-4a72-8932-802357cf266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142706499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2142706499
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.242610626
Short name T757
Test name
Test status
Simulation time 495002948541 ps
CPU time 257.04 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:56:01 PM PDT 24
Peak memory 201424 kb
Host smart-9b840754-a088-4229-8bc6-9b42cec8c619
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=242610626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.242610626
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3004371288
Short name T655
Test name
Test status
Simulation time 493710216432 ps
CPU time 712.63 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 07:03:40 PM PDT 24
Peak memory 201448 kb
Host smart-89c2b1d9-def1-42cd-b0bd-f6b551c25950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004371288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3004371288
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3036243812
Short name T439
Test name
Test status
Simulation time 492979137355 ps
CPU time 1196.45 seconds
Started Aug 01 06:51:51 PM PDT 24
Finished Aug 01 07:11:47 PM PDT 24
Peak memory 201416 kb
Host smart-345e1587-597a-4e36-9fa1-b9c07a5d1862
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036243812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3036243812
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.271041893
Short name T795
Test name
Test status
Simulation time 168339993704 ps
CPU time 315.26 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 06:57:12 PM PDT 24
Peak memory 201408 kb
Host smart-6fd04b35-9398-4736-9496-97ac6f037d16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271041893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.271041893
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.30522605
Short name T648
Test name
Test status
Simulation time 189254652555 ps
CPU time 409.56 seconds
Started Aug 01 06:51:51 PM PDT 24
Finished Aug 01 06:58:41 PM PDT 24
Peak memory 201436 kb
Host smart-bd1ca731-54b3-48ea-91f0-0f330b845d3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.30522605
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3633944607
Short name T208
Test name
Test status
Simulation time 82746395067 ps
CPU time 322 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:57:07 PM PDT 24
Peak memory 201792 kb
Host smart-a1ede7c3-21c6-4226-b0e9-c01bf6bc94fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633944607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3633944607
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1933440606
Short name T556
Test name
Test status
Simulation time 25676448794 ps
CPU time 57.35 seconds
Started Aug 01 06:51:48 PM PDT 24
Finished Aug 01 06:52:45 PM PDT 24
Peak memory 201352 kb
Host smart-e33b7ee6-c70c-4b88-a336-7083f73dc7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933440606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1933440606
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1144557733
Short name T405
Test name
Test status
Simulation time 4695429467 ps
CPU time 3.41 seconds
Started Aug 01 06:51:50 PM PDT 24
Finished Aug 01 06:51:54 PM PDT 24
Peak memory 201360 kb
Host smart-0fa1216f-9bc0-4fae-ac6e-08f30d2f366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144557733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1144557733
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1099481413
Short name T82
Test name
Test status
Simulation time 7817153192 ps
CPU time 9.71 seconds
Started Aug 01 06:51:42 PM PDT 24
Finished Aug 01 06:51:52 PM PDT 24
Peak memory 218200 kb
Host smart-333a3406-2bca-4ea5-8023-184d444edeed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099481413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1099481413
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.424140670
Short name T673
Test name
Test status
Simulation time 5576917419 ps
CPU time 2.74 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:51:49 PM PDT 24
Peak memory 201320 kb
Host smart-513c55f8-69c1-4199-87bd-020444916859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424140670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.424140670
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1507805342
Short name T192
Test name
Test status
Simulation time 205340006934 ps
CPU time 122.99 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 06:53:46 PM PDT 24
Peak memory 201460 kb
Host smart-0623573c-43da-4262-8376-a8780ed3fab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507805342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1507805342
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1738049212
Short name T606
Test name
Test status
Simulation time 463895706 ps
CPU time 0.85 seconds
Started Aug 01 06:51:51 PM PDT 24
Finished Aug 01 06:51:52 PM PDT 24
Peak memory 201260 kb
Host smart-bd5670de-fd07-42e4-8b75-42d5c852d5e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738049212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1738049212
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3220130842
Short name T32
Test name
Test status
Simulation time 163405425435 ps
CPU time 396.73 seconds
Started Aug 01 06:51:45 PM PDT 24
Finished Aug 01 06:58:22 PM PDT 24
Peak memory 201492 kb
Host smart-086e93d0-1467-48f6-aa51-2c60a9e008d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220130842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3220130842
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2895600457
Short name T176
Test name
Test status
Simulation time 172642332840 ps
CPU time 52.19 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 06:52:49 PM PDT 24
Peak memory 201432 kb
Host smart-2ca01117-4e86-4ee0-92bc-9e0597926491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895600457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2895600457
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2889007457
Short name T504
Test name
Test status
Simulation time 160468847130 ps
CPU time 174.3 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 06:54:38 PM PDT 24
Peak memory 201412 kb
Host smart-0e1dd7f2-1083-4a9c-b46f-bd82e933ff73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889007457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2889007457
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1145565588
Short name T58
Test name
Test status
Simulation time 333749496722 ps
CPU time 177.33 seconds
Started Aug 01 06:51:49 PM PDT 24
Finished Aug 01 06:54:46 PM PDT 24
Peak memory 201440 kb
Host smart-216d102c-8b57-4dba-bbb2-ddca292ab134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145565588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1145565588
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1098999358
Short name T618
Test name
Test status
Simulation time 323370804513 ps
CPU time 520.12 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 07:00:28 PM PDT 24
Peak memory 201372 kb
Host smart-eded3bf2-e554-4232-8569-6f422d48da6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098999358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1098999358
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1524956689
Short name T235
Test name
Test status
Simulation time 170824384773 ps
CPU time 188.38 seconds
Started Aug 01 06:51:49 PM PDT 24
Finished Aug 01 06:54:58 PM PDT 24
Peak memory 201448 kb
Host smart-788a04aa-30b3-48e7-ac78-11de6b97750f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524956689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1524956689
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1150884466
Short name T15
Test name
Test status
Simulation time 190875903288 ps
CPU time 204.24 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 06:55:09 PM PDT 24
Peak memory 201412 kb
Host smart-1309336d-74c1-4b3f-aa9b-823c6253d2d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150884466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1150884466
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.28332790
Short name T733
Test name
Test status
Simulation time 99258002792 ps
CPU time 572.77 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 07:01:19 PM PDT 24
Peak memory 201780 kb
Host smart-826618bf-83cb-4c0a-8e40-0230412f6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28332790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.28332790
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1257016727
Short name T440
Test name
Test status
Simulation time 38656731043 ps
CPU time 82.33 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:53:09 PM PDT 24
Peak memory 201352 kb
Host smart-064eebbf-4ae8-4d5e-9224-3efcfd820e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257016727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1257016727
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.452535054
Short name T586
Test name
Test status
Simulation time 3507617455 ps
CPU time 2.76 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:52:03 PM PDT 24
Peak memory 201312 kb
Host smart-82585596-dc3b-4a89-aafd-69fae4b6822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452535054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.452535054
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.322884919
Short name T95
Test name
Test status
Simulation time 8007026920 ps
CPU time 5.82 seconds
Started Aug 01 06:51:51 PM PDT 24
Finished Aug 01 06:51:57 PM PDT 24
Peak memory 217852 kb
Host smart-6aba24dc-a3d6-4f61-b13b-97aa54307ba3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322884919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.322884919
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1108038366
Short name T782
Test name
Test status
Simulation time 5835579158 ps
CPU time 9.19 seconds
Started Aug 01 06:51:48 PM PDT 24
Finished Aug 01 06:51:57 PM PDT 24
Peak memory 201316 kb
Host smart-8130d54c-2ce5-4b84-8668-bf720faea3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108038366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1108038366
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3076913811
Short name T326
Test name
Test status
Simulation time 541432874912 ps
CPU time 1068.49 seconds
Started Aug 01 06:51:45 PM PDT 24
Finished Aug 01 07:09:34 PM PDT 24
Peak memory 201424 kb
Host smart-7caac87e-1d03-4a57-8b1f-6c2a61b9dc72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076913811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3076913811
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2477804076
Short name T666
Test name
Test status
Simulation time 235477201752 ps
CPU time 101.44 seconds
Started Aug 01 06:51:51 PM PDT 24
Finished Aug 01 06:53:32 PM PDT 24
Peak memory 210148 kb
Host smart-1631bf25-de30-4bca-9642-ef8a9460b55b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477804076 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2477804076
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3668192677
Short name T779
Test name
Test status
Simulation time 436115410 ps
CPU time 0.84 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 06:52:15 PM PDT 24
Peak memory 201236 kb
Host smart-58200d3e-32b5-4c46-b0a7-2fa95b87ba7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668192677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3668192677
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.54212005
Short name T796
Test name
Test status
Simulation time 361673455111 ps
CPU time 399.42 seconds
Started Aug 01 06:52:04 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 201456 kb
Host smart-061f662e-3767-487a-becb-831113b72dfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54212005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gatin
g.54212005
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3298208876
Short name T117
Test name
Test status
Simulation time 165308504722 ps
CPU time 93.73 seconds
Started Aug 01 06:52:16 PM PDT 24
Finished Aug 01 06:53:49 PM PDT 24
Peak memory 201432 kb
Host smart-c33ab260-7d0f-421b-a191-61b54c8fa95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298208876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3298208876
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1275515132
Short name T168
Test name
Test status
Simulation time 166735507712 ps
CPU time 200.61 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 06:55:24 PM PDT 24
Peak memory 201488 kb
Host smart-4c091f0f-8048-45e1-8769-8f1a6e98dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275515132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1275515132
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.36493170
Short name T365
Test name
Test status
Simulation time 324878285992 ps
CPU time 726.43 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 07:04:10 PM PDT 24
Peak memory 201436 kb
Host smart-1e73f547-3942-44fd-8276-aed631e63bd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=36493170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt
_fixed.36493170
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.4197806197
Short name T182
Test name
Test status
Simulation time 318723799036 ps
CPU time 66.06 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:53:08 PM PDT 24
Peak memory 201432 kb
Host smart-37385f0f-322d-43dd-a7b9-c798b9cda0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197806197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4197806197
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1930699670
Short name T400
Test name
Test status
Simulation time 493863309788 ps
CPU time 103.13 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 06:53:52 PM PDT 24
Peak memory 200456 kb
Host smart-02da5e33-7348-4afc-bdd8-aaaaf87076b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930699670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1930699670
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.537141407
Short name T590
Test name
Test status
Simulation time 529806469043 ps
CPU time 1275.58 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 07:13:22 PM PDT 24
Peak memory 201484 kb
Host smart-4e9e7aea-b407-481c-bc4a-1662dfc2d113
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537141407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.537141407
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.52861526
Short name T358
Test name
Test status
Simulation time 199330352816 ps
CPU time 423.6 seconds
Started Aug 01 06:52:08 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 201424 kb
Host smart-1e3a50ba-49a3-42fd-985c-7284ae80850d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52861526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.a
dc_ctrl_filters_wakeup_fixed.52861526
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.51259225
Short name T521
Test name
Test status
Simulation time 60488272973 ps
CPU time 352.1 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:57:54 PM PDT 24
Peak memory 201844 kb
Host smart-0a35d7d4-e260-4b99-a781-32493192dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51259225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.51259225
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3360624283
Short name T732
Test name
Test status
Simulation time 44828982658 ps
CPU time 26.26 seconds
Started Aug 01 06:52:19 PM PDT 24
Finished Aug 01 06:52:45 PM PDT 24
Peak memory 201356 kb
Host smart-b3a28ab1-a9fa-4f7e-acf8-44b7de55ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360624283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3360624283
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1626199395
Short name T702
Test name
Test status
Simulation time 4852495424 ps
CPU time 11.89 seconds
Started Aug 01 06:52:08 PM PDT 24
Finished Aug 01 06:52:20 PM PDT 24
Peak memory 201344 kb
Host smart-40b31ba2-5000-4f8c-97e3-6d1475b58208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626199395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1626199395
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3622293749
Short name T375
Test name
Test status
Simulation time 5720301110 ps
CPU time 7.19 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 06:52:11 PM PDT 24
Peak memory 201344 kb
Host smart-34c683d0-f260-4fd1-bccc-06070b7e6f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622293749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3622293749
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3387365701
Short name T489
Test name
Test status
Simulation time 409104200737 ps
CPU time 510.04 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:00:44 PM PDT 24
Peak memory 201824 kb
Host smart-05e5a808-9c62-45e7-a759-6d9d455449b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387365701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3387365701
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3452456191
Short name T51
Test name
Test status
Simulation time 31926598548 ps
CPU time 34.47 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 06:52:44 PM PDT 24
Peak memory 218308 kb
Host smart-527895a6-3175-4275-b48c-279ef8c8189d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452456191 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3452456191
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1249909183
Short name T711
Test name
Test status
Simulation time 400308959 ps
CPU time 0.75 seconds
Started Aug 01 06:52:07 PM PDT 24
Finished Aug 01 06:52:08 PM PDT 24
Peak memory 201256 kb
Host smart-0f53bf09-7445-4409-a7db-fe47abd78909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249909183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1249909183
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3894104477
Short name T508
Test name
Test status
Simulation time 165233177879 ps
CPU time 106.36 seconds
Started Aug 01 06:52:19 PM PDT 24
Finished Aug 01 06:54:06 PM PDT 24
Peak memory 201444 kb
Host smart-9d392941-50c7-4150-967f-87abbf87d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894104477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3894104477
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4286958467
Short name T647
Test name
Test status
Simulation time 495831482803 ps
CPU time 1087.8 seconds
Started Aug 01 06:52:21 PM PDT 24
Finished Aug 01 07:10:29 PM PDT 24
Peak memory 201420 kb
Host smart-57777c72-2365-4573-a98b-354732458904
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286958467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.4286958467
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2483089281
Short name T222
Test name
Test status
Simulation time 166218451324 ps
CPU time 34.67 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 06:52:48 PM PDT 24
Peak memory 201456 kb
Host smart-7e41930c-5e83-47b2-a4e5-53a9162977aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483089281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2483089281
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1743382618
Short name T357
Test name
Test status
Simulation time 341607241561 ps
CPU time 92.5 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 06:53:42 PM PDT 24
Peak memory 201372 kb
Host smart-9ac8a5f6-8994-41f9-b522-5b33eabea467
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743382618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1743382618
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2113907889
Short name T274
Test name
Test status
Simulation time 547244776431 ps
CPU time 1182.96 seconds
Started Aug 01 06:52:08 PM PDT 24
Finished Aug 01 07:11:51 PM PDT 24
Peak memory 201464 kb
Host smart-0c56cc14-fa47-4742-aed3-bbf1066a2993
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113907889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2113907889
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1680329025
Short name T748
Test name
Test status
Simulation time 204547411348 ps
CPU time 267.25 seconds
Started Aug 01 06:52:16 PM PDT 24
Finished Aug 01 06:56:43 PM PDT 24
Peak memory 201420 kb
Host smart-f40e4841-05e3-495b-8d47-1a3ef5cd6af3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680329025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1680329025
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2813370825
Short name T729
Test name
Test status
Simulation time 78066391915 ps
CPU time 295.99 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 06:56:59 PM PDT 24
Peak memory 201832 kb
Host smart-3f99bdeb-7812-4099-a0d4-df83301af7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813370825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2813370825
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3585445816
Short name T368
Test name
Test status
Simulation time 37975265882 ps
CPU time 23.18 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:52:29 PM PDT 24
Peak memory 201384 kb
Host smart-38e4f3e8-c731-4f23-a4ab-2f53b2831f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585445816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3585445816
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1250754120
Short name T445
Test name
Test status
Simulation time 4078893783 ps
CPU time 8.56 seconds
Started Aug 01 06:52:24 PM PDT 24
Finished Aug 01 06:52:33 PM PDT 24
Peak memory 201368 kb
Host smart-64598cac-90ff-49e1-93ea-bdfc0c044745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250754120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1250754120
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2910617026
Short name T453
Test name
Test status
Simulation time 6040187822 ps
CPU time 4.92 seconds
Started Aug 01 06:52:12 PM PDT 24
Finished Aug 01 06:52:17 PM PDT 24
Peak memory 201272 kb
Host smart-f2f74c20-1035-4af3-b297-ce270ef03b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910617026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2910617026
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1727742729
Short name T20
Test name
Test status
Simulation time 47621079239 ps
CPU time 114.62 seconds
Started Aug 01 06:52:07 PM PDT 24
Finished Aug 01 06:54:02 PM PDT 24
Peak memory 217920 kb
Host smart-0834e7d5-bf1c-427e-97a6-daffe79f18de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727742729 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1727742729
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3892670367
Short name T639
Test name
Test status
Simulation time 519704810 ps
CPU time 0.88 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:52:14 PM PDT 24
Peak memory 201208 kb
Host smart-717770fd-655c-45ed-866a-79a5bc2d7876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892670367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3892670367
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.322361722
Short name T113
Test name
Test status
Simulation time 323538101937 ps
CPU time 300.81 seconds
Started Aug 01 06:52:12 PM PDT 24
Finished Aug 01 06:57:13 PM PDT 24
Peak memory 201452 kb
Host smart-eb012faa-3ab3-45e3-8352-b1e7294afb08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322361722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.322361722
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3372410437
Short name T329
Test name
Test status
Simulation time 348395618775 ps
CPU time 222.57 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:56:17 PM PDT 24
Peak memory 201508 kb
Host smart-58109fea-582d-4570-aa23-3057b1bda95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372410437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3372410437
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.709358289
Short name T776
Test name
Test status
Simulation time 161481244980 ps
CPU time 340.54 seconds
Started Aug 01 06:52:30 PM PDT 24
Finished Aug 01 06:58:10 PM PDT 24
Peak memory 201456 kb
Host smart-fdd85125-18d8-424d-b95f-6d11a6478e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709358289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.709358289
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3232689824
Short name T363
Test name
Test status
Simulation time 498661352941 ps
CPU time 1203.55 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 07:12:17 PM PDT 24
Peak memory 201428 kb
Host smart-c5d3273e-d9cc-4add-beb5-6e24c81c87b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232689824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3232689824
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1042886170
Short name T247
Test name
Test status
Simulation time 324452239230 ps
CPU time 369.68 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:58:23 PM PDT 24
Peak memory 201372 kb
Host smart-7eab9e3c-b979-439d-a6a4-f40ac121bf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042886170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1042886170
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2441341350
Short name T11
Test name
Test status
Simulation time 323096683880 ps
CPU time 733.05 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:04:27 PM PDT 24
Peak memory 201456 kb
Host smart-1ab63489-4b14-4cbb-9701-7f1ea02b86c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441341350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2441341350
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1869729759
Short name T646
Test name
Test status
Simulation time 192436089643 ps
CPU time 215.04 seconds
Started Aug 01 06:52:17 PM PDT 24
Finished Aug 01 06:55:52 PM PDT 24
Peak memory 201432 kb
Host smart-fe37a14a-e9bf-48ea-b9f9-8353fd221f8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869729759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1869729759
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2074929185
Short name T523
Test name
Test status
Simulation time 583943853108 ps
CPU time 1214.49 seconds
Started Aug 01 06:52:15 PM PDT 24
Finished Aug 01 07:12:30 PM PDT 24
Peak memory 201436 kb
Host smart-5a6d8fca-01a6-45b7-9ca9-764b269415ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074929185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2074929185
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4229121578
Short name T582
Test name
Test status
Simulation time 90642365513 ps
CPU time 326.33 seconds
Started Aug 01 06:52:32 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 201836 kb
Host smart-17d6174f-af89-48da-aef6-8d3a2bfc0421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229121578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4229121578
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.606710840
Short name T676
Test name
Test status
Simulation time 23325699135 ps
CPU time 13.28 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:52:40 PM PDT 24
Peak memory 201344 kb
Host smart-ab2bbdf3-f0e3-423b-ac62-414eb0ce905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606710840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.606710840
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3284195794
Short name T758
Test name
Test status
Simulation time 5405430280 ps
CPU time 3.71 seconds
Started Aug 01 06:52:25 PM PDT 24
Finished Aug 01 06:52:29 PM PDT 24
Peak memory 201336 kb
Host smart-1c467a4a-aa75-4700-81d7-4ea2800a3917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284195794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3284195794
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2529983010
Short name T412
Test name
Test status
Simulation time 5756676664 ps
CPU time 4.29 seconds
Started Aug 01 06:52:23 PM PDT 24
Finished Aug 01 06:52:27 PM PDT 24
Peak memory 201332 kb
Host smart-a70b3875-c807-4b97-87ee-31f190b3c3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529983010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2529983010
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.924395193
Short name T157
Test name
Test status
Simulation time 516624054245 ps
CPU time 268.24 seconds
Started Aug 01 06:52:22 PM PDT 24
Finished Aug 01 06:56:51 PM PDT 24
Peak memory 201412 kb
Host smart-dfb01cec-ff70-415a-80bb-55a1a1edefef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924395193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
924395193
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3336063593
Short name T253
Test name
Test status
Simulation time 90002502624 ps
CPU time 155.68 seconds
Started Aug 01 06:52:20 PM PDT 24
Finished Aug 01 06:54:56 PM PDT 24
Peak memory 209848 kb
Host smart-f37e65b9-119b-4390-9d28-a6fa98b13a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336063593 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3336063593
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2355675975
Short name T579
Test name
Test status
Simulation time 479768762 ps
CPU time 0.9 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:52:28 PM PDT 24
Peak memory 201204 kb
Host smart-a1d27558-24e0-4637-a0a1-425a307b8e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355675975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2355675975
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2130048442
Short name T318
Test name
Test status
Simulation time 396337569895 ps
CPU time 358.34 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:58:12 PM PDT 24
Peak memory 201424 kb
Host smart-d32f3897-8f46-4505-a7e9-f1c31014d904
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130048442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2130048442
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1813003741
Short name T608
Test name
Test status
Simulation time 493589825679 ps
CPU time 1132.91 seconds
Started Aug 01 06:52:11 PM PDT 24
Finished Aug 01 07:11:04 PM PDT 24
Peak memory 201432 kb
Host smart-0414f7d8-2984-4dc5-b9e8-ed02816482a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813003741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1813003741
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2887094814
Short name T491
Test name
Test status
Simulation time 324857414555 ps
CPU time 763.59 seconds
Started Aug 01 06:52:25 PM PDT 24
Finished Aug 01 07:05:09 PM PDT 24
Peak memory 201456 kb
Host smart-7abbe706-76d6-4427-87b5-0da475e085d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887094814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2887094814
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3306985392
Short name T514
Test name
Test status
Simulation time 331962912303 ps
CPU time 785.22 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:05:20 PM PDT 24
Peak memory 201464 kb
Host smart-6357c79b-a1dd-418d-bb37-fcdd2047aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306985392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3306985392
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.496195650
Short name T166
Test name
Test status
Simulation time 325264336398 ps
CPU time 377.67 seconds
Started Aug 01 06:52:11 PM PDT 24
Finished Aug 01 06:58:29 PM PDT 24
Peak memory 201424 kb
Host smart-a27b173a-89ce-4fc3-8cdd-684b29ebbded
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=496195650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.496195650
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3131040763
Short name T726
Test name
Test status
Simulation time 597203524423 ps
CPU time 190.3 seconds
Started Aug 01 06:52:28 PM PDT 24
Finished Aug 01 06:55:38 PM PDT 24
Peak memory 201416 kb
Host smart-c16450b2-6e86-4c97-af57-d2cb2181f7ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131040763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3131040763
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4159623611
Short name T562
Test name
Test status
Simulation time 116589785487 ps
CPU time 449.9 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:59:57 PM PDT 24
Peak memory 201848 kb
Host smart-0428ad65-2a98-4b71-9d44-f4278211cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159623611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4159623611
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3662249748
Short name T393
Test name
Test status
Simulation time 29393946436 ps
CPU time 60.65 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:53:14 PM PDT 24
Peak memory 201356 kb
Host smart-ef1ed322-a571-45ca-9287-f3fa960053a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662249748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3662249748
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3893412861
Short name T568
Test name
Test status
Simulation time 4578209492 ps
CPU time 6.29 seconds
Started Aug 01 06:52:22 PM PDT 24
Finished Aug 01 06:52:29 PM PDT 24
Peak memory 201548 kb
Host smart-54b3f1fc-ce9b-43c0-91aa-22ed4a744ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893412861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3893412861
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3875478494
Short name T746
Test name
Test status
Simulation time 5841560759 ps
CPU time 4.16 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 06:52:31 PM PDT 24
Peak memory 201424 kb
Host smart-7c695fd1-96e7-4de4-b0a8-a4d6247c93fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875478494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3875478494
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3422733186
Short name T554
Test name
Test status
Simulation time 337956073971 ps
CPU time 125.27 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:54:18 PM PDT 24
Peak memory 201404 kb
Host smart-3cfb10e2-64f2-448e-9f82-b42320d163ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422733186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3422733186
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2786157744
Short name T638
Test name
Test status
Simulation time 347964319 ps
CPU time 1.07 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 06:52:27 PM PDT 24
Peak memory 201208 kb
Host smart-e35d7e62-f64c-4e06-9b7f-b351b378f708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786157744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2786157744
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3737345671
Short name T181
Test name
Test status
Simulation time 496631344544 ps
CPU time 1063.38 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:09:57 PM PDT 24
Peak memory 201452 kb
Host smart-01ddf88f-1579-4447-971d-33e8293cf163
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737345671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3737345671
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.925899945
Short name T503
Test name
Test status
Simulation time 485020881366 ps
CPU time 1048.39 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:09:42 PM PDT 24
Peak memory 201440 kb
Host smart-44a9a21f-bb89-4d10-b7df-a96480cf21f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925899945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.925899945
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2600229727
Short name T751
Test name
Test status
Simulation time 489586907280 ps
CPU time 96.81 seconds
Started Aug 01 06:52:22 PM PDT 24
Finished Aug 01 06:53:59 PM PDT 24
Peak memory 201476 kb
Host smart-a231b7ff-9f48-404c-a26a-371da206915b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600229727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2600229727
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1001041830
Short name T297
Test name
Test status
Simulation time 500252657330 ps
CPU time 272.45 seconds
Started Aug 01 06:52:22 PM PDT 24
Finished Aug 01 06:56:55 PM PDT 24
Peak memory 201388 kb
Host smart-742919b8-97cc-4933-af3f-877010e07619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001041830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1001041830
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.4126016546
Short name T448
Test name
Test status
Simulation time 164431253137 ps
CPU time 106.36 seconds
Started Aug 01 06:52:22 PM PDT 24
Finished Aug 01 06:54:08 PM PDT 24
Peak memory 201424 kb
Host smart-0fa13c7b-6c56-49c3-9399-7c88053eec66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126016546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.4126016546
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2319832073
Short name T189
Test name
Test status
Simulation time 603939512223 ps
CPU time 348.11 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:58:22 PM PDT 24
Peak memory 201464 kb
Host smart-0fdfeacc-a176-469b-95aa-5f2a7d294341
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319832073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2319832073
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.639670887
Short name T115
Test name
Test status
Simulation time 399101235143 ps
CPU time 927.17 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 07:07:53 PM PDT 24
Peak memory 201404 kb
Host smart-47172ff3-8c67-4d98-b5d8-63d9d8c45c80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639670887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.639670887
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.711226800
Short name T589
Test name
Test status
Simulation time 28387207925 ps
CPU time 15.01 seconds
Started Aug 01 06:52:13 PM PDT 24
Finished Aug 01 06:52:28 PM PDT 24
Peak memory 201352 kb
Host smart-6cf86b36-8485-4d70-81b8-6845feed0061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711226800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.711226800
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.559974441
Short name T98
Test name
Test status
Simulation time 3675522239 ps
CPU time 8.56 seconds
Started Aug 01 06:52:24 PM PDT 24
Finished Aug 01 06:52:33 PM PDT 24
Peak memory 201364 kb
Host smart-c5faa92a-12e1-44be-a55c-e6290e94b2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559974441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.559974441
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4074129627
Short name T744
Test name
Test status
Simulation time 5910963872 ps
CPU time 5.99 seconds
Started Aug 01 06:52:18 PM PDT 24
Finished Aug 01 06:52:24 PM PDT 24
Peak memory 201368 kb
Host smart-fd11398d-957b-4b76-b87d-1bea6c998a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074129627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4074129627
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1225016005
Short name T306
Test name
Test status
Simulation time 319522870526 ps
CPU time 734.99 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:04:29 PM PDT 24
Peak memory 201780 kb
Host smart-4f09d350-a2d3-446c-8fae-4066ead6aa76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225016005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1225016005
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3321164614
Short name T496
Test name
Test status
Simulation time 47459099069 ps
CPU time 57.62 seconds
Started Aug 01 06:52:25 PM PDT 24
Finished Aug 01 06:53:23 PM PDT 24
Peak memory 201652 kb
Host smart-3bb26611-cb97-4c56-947b-c52e8954ccb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321164614 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3321164614
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.265512330
Short name T468
Test name
Test status
Simulation time 324314186 ps
CPU time 1.31 seconds
Started Aug 01 06:52:30 PM PDT 24
Finished Aug 01 06:52:32 PM PDT 24
Peak memory 201188 kb
Host smart-6941ddf9-6436-4b4a-8662-800f8ee3d4fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265512330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.265512330
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3521443780
Short name T712
Test name
Test status
Simulation time 326562577370 ps
CPU time 161.46 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:55:09 PM PDT 24
Peak memory 201432 kb
Host smart-5b8945b7-d6de-4510-b30f-cc1d4b34a5bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521443780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3521443780
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.173788278
Short name T120
Test name
Test status
Simulation time 349023292123 ps
CPU time 67.4 seconds
Started Aug 01 06:52:24 PM PDT 24
Finished Aug 01 06:53:31 PM PDT 24
Peak memory 201484 kb
Host smart-7a409f1b-3471-44e2-bbdd-a665bca5ddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173788278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.173788278
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2334665966
Short name T202
Test name
Test status
Simulation time 324690182787 ps
CPU time 189.99 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:55:37 PM PDT 24
Peak memory 201452 kb
Host smart-af714886-d524-416f-bca0-5d7191a1cd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334665966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2334665966
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3883694968
Short name T472
Test name
Test status
Simulation time 491983548175 ps
CPU time 312.4 seconds
Started Aug 01 06:52:32 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 201488 kb
Host smart-1f0d2286-c95f-4d6a-b834-09ab4ed39545
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883694968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3883694968
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2854462631
Short name T605
Test name
Test status
Simulation time 328453125029 ps
CPU time 206.88 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:56:00 PM PDT 24
Peak memory 201432 kb
Host smart-f57ebe87-33a6-45ae-93df-a22c4bfbb861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854462631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2854462631
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2832428738
Short name T458
Test name
Test status
Simulation time 166705246099 ps
CPU time 92.74 seconds
Started Aug 01 06:52:31 PM PDT 24
Finished Aug 01 06:54:04 PM PDT 24
Peak memory 201356 kb
Host smart-3a6076aa-ac1a-409b-ab8a-f880da2b86ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832428738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2832428738
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3999244630
Short name T13
Test name
Test status
Simulation time 598080412704 ps
CPU time 354.27 seconds
Started Aug 01 06:52:28 PM PDT 24
Finished Aug 01 06:58:22 PM PDT 24
Peak memory 201436 kb
Host smart-6c3bbda9-7e6e-41d7-b3fb-c9805e0dcf0f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999244630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3999244630
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3089657513
Short name T635
Test name
Test status
Simulation time 41414363034 ps
CPU time 101.23 seconds
Started Aug 01 06:52:30 PM PDT 24
Finished Aug 01 06:54:12 PM PDT 24
Peak memory 201064 kb
Host smart-1a0cb0a8-8bd9-4f0e-9c45-3db5f06911f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089657513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3089657513
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4185608105
Short name T416
Test name
Test status
Simulation time 2822305821 ps
CPU time 7.6 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 06:52:34 PM PDT 24
Peak memory 201344 kb
Host smart-1302f2e0-e302-4425-bc0c-fa6eb72cddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185608105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4185608105
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2573894384
Short name T689
Test name
Test status
Simulation time 5932242343 ps
CPU time 14.63 seconds
Started Aug 01 06:52:25 PM PDT 24
Finished Aug 01 06:52:40 PM PDT 24
Peak memory 201368 kb
Host smart-a7278384-3bb8-4cc7-a261-498aeb622271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573894384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2573894384
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.613284167
Short name T522
Test name
Test status
Simulation time 328859848294 ps
CPU time 207.57 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 06:55:54 PM PDT 24
Peak memory 201464 kb
Host smart-05cf3987-a8e9-4e06-aa94-e903865936e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613284167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
613284167
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3538263570
Short name T283
Test name
Test status
Simulation time 874550227476 ps
CPU time 1062.67 seconds
Started Aug 01 06:52:24 PM PDT 24
Finished Aug 01 07:10:07 PM PDT 24
Peak memory 210184 kb
Host smart-d8c1e4f1-77ea-4932-9dd1-110466f4feaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538263570 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3538263570
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.835983904
Short name T642
Test name
Test status
Simulation time 470143749 ps
CPU time 1.72 seconds
Started Aug 01 06:52:32 PM PDT 24
Finished Aug 01 06:52:34 PM PDT 24
Peak memory 201248 kb
Host smart-cc377bd7-7f50-4a59-ae89-29013a7b54c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835983904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.835983904
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4084570980
Short name T794
Test name
Test status
Simulation time 330665456525 ps
CPU time 791.37 seconds
Started Aug 01 06:52:24 PM PDT 24
Finished Aug 01 07:05:36 PM PDT 24
Peak memory 201400 kb
Host smart-c6950ab2-2038-47a9-ac59-36ed96bcb9d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084570980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4084570980
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.367509990
Short name T44
Test name
Test status
Simulation time 516477262159 ps
CPU time 1230.43 seconds
Started Aug 01 06:52:23 PM PDT 24
Finished Aug 01 07:12:54 PM PDT 24
Peak memory 201456 kb
Host smart-376f0372-b884-47a7-a444-4fa7b623c0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367509990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.367509990
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3962506131
Short name T704
Test name
Test status
Simulation time 162368986199 ps
CPU time 185.4 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:55:40 PM PDT 24
Peak memory 201356 kb
Host smart-cf8737f2-b6d7-45fe-ba0d-1be0c9090b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962506131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3962506131
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.845848521
Short name T475
Test name
Test status
Simulation time 485292579700 ps
CPU time 1184.19 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 07:12:19 PM PDT 24
Peak memory 201452 kb
Host smart-36514e7d-4ace-4d7e-bbd4-5b3e467e0d69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=845848521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.845848521
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1538795696
Short name T482
Test name
Test status
Simulation time 161668413784 ps
CPU time 192.96 seconds
Started Aug 01 06:52:22 PM PDT 24
Finished Aug 01 06:55:36 PM PDT 24
Peak memory 201392 kb
Host smart-58d9c1f8-8a1f-464c-91ef-ea17b29753ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538795696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1538795696
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1628674624
Short name T433
Test name
Test status
Simulation time 165213429368 ps
CPU time 120.74 seconds
Started Aug 01 06:52:30 PM PDT 24
Finished Aug 01 06:54:30 PM PDT 24
Peak memory 201464 kb
Host smart-11ca4626-3ffe-4d35-93be-e237f1da877d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628674624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1628674624
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3057062961
Short name T187
Test name
Test status
Simulation time 573675135572 ps
CPU time 302.6 seconds
Started Aug 01 06:52:27 PM PDT 24
Finished Aug 01 06:57:30 PM PDT 24
Peak memory 201460 kb
Host smart-e26763b4-23e1-42d6-97a2-885b0668c1b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057062961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3057062961
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1366816212
Short name T9
Test name
Test status
Simulation time 398499714086 ps
CPU time 207.95 seconds
Started Aug 01 06:52:25 PM PDT 24
Finished Aug 01 06:55:53 PM PDT 24
Peak memory 201452 kb
Host smart-e3045c15-7e61-41e0-b60b-0569b4ca5334
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366816212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1366816212
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2365168844
Short name T492
Test name
Test status
Simulation time 133722599445 ps
CPU time 717.23 seconds
Started Aug 01 06:52:23 PM PDT 24
Finished Aug 01 07:04:20 PM PDT 24
Peak memory 201908 kb
Host smart-cc6630ad-1daf-4ffb-b3d5-8b4733a9c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365168844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2365168844
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.70010127
Short name T108
Test name
Test status
Simulation time 44062554889 ps
CPU time 28.93 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 06:52:55 PM PDT 24
Peak memory 201344 kb
Host smart-fc93ddbc-d214-481b-acfe-f9fd24c82953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70010127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.70010127
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3024639082
Short name T680
Test name
Test status
Simulation time 2731332128 ps
CPU time 3.86 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:52:37 PM PDT 24
Peak memory 201376 kb
Host smart-ddb1bb9e-d15b-453f-ab48-35c487727d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024639082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3024639082
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3984035398
Short name T604
Test name
Test status
Simulation time 5941703031 ps
CPU time 7.74 seconds
Started Aug 01 06:52:23 PM PDT 24
Finished Aug 01 06:52:30 PM PDT 24
Peak memory 201376 kb
Host smart-8108238a-43bc-4bc3-89f3-d63c41a40cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984035398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3984035398
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.383363509
Short name T43
Test name
Test status
Simulation time 338589770054 ps
CPU time 196.21 seconds
Started Aug 01 06:52:30 PM PDT 24
Finished Aug 01 06:55:46 PM PDT 24
Peak memory 201452 kb
Host smart-791c6e8a-348d-4d3b-b5c2-60be7dce7d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383363509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
383363509
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.894371430
Short name T719
Test name
Test status
Simulation time 21459317291 ps
CPU time 79.01 seconds
Started Aug 01 06:52:29 PM PDT 24
Finished Aug 01 06:53:48 PM PDT 24
Peak memory 215908 kb
Host smart-f2c34950-27c8-4b9c-9ba4-a57d05b08cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894371430 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.894371430
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3390674596
Short name T654
Test name
Test status
Simulation time 345604193 ps
CPU time 1 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:52:34 PM PDT 24
Peak memory 201228 kb
Host smart-3f96bd1d-d069-4b9b-8f43-9cf4b3497f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390674596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3390674596
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.935103265
Short name T657
Test name
Test status
Simulation time 165284191538 ps
CPU time 101.12 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 06:54:08 PM PDT 24
Peak memory 201452 kb
Host smart-df839944-d0c5-4ced-a434-3764ebac3479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935103265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.935103265
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4147036280
Short name T434
Test name
Test status
Simulation time 161364117608 ps
CPU time 382.41 seconds
Started Aug 01 06:52:30 PM PDT 24
Finished Aug 01 06:58:53 PM PDT 24
Peak memory 201080 kb
Host smart-1a640779-05b3-4be1-a52f-9760f44b3361
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147036280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4147036280
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.831910297
Short name T632
Test name
Test status
Simulation time 330436769242 ps
CPU time 371 seconds
Started Aug 01 06:52:28 PM PDT 24
Finished Aug 01 06:58:39 PM PDT 24
Peak memory 201496 kb
Host smart-5f92d894-e9e0-4324-8c39-64dcb9f93c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831910297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.831910297
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3304597809
Short name T361
Test name
Test status
Simulation time 497373894662 ps
CPU time 1035.72 seconds
Started Aug 01 06:52:26 PM PDT 24
Finished Aug 01 07:09:42 PM PDT 24
Peak memory 201468 kb
Host smart-3fd17784-7ad5-47e3-a895-0f8fdeee5e8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304597809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3304597809
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2102201300
Short name T170
Test name
Test status
Simulation time 528610566313 ps
CPU time 529.93 seconds
Started Aug 01 06:52:29 PM PDT 24
Finished Aug 01 07:01:20 PM PDT 24
Peak memory 201472 kb
Host smart-9bc616c9-e902-43de-bc0c-3447c9a367c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102201300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2102201300
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2882330343
Short name T441
Test name
Test status
Simulation time 406026218364 ps
CPU time 240.41 seconds
Started Aug 01 06:52:23 PM PDT 24
Finished Aug 01 06:56:23 PM PDT 24
Peak memory 201464 kb
Host smart-1a955788-05fd-47d8-b69e-89519b1f2f2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882330343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2882330343
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.287641010
Short name T530
Test name
Test status
Simulation time 64976824722 ps
CPU time 281.62 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:57:17 PM PDT 24
Peak memory 201764 kb
Host smart-dbf5dd7a-d8d5-48f0-bda5-37cac844cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287641010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.287641010
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.420194215
Short name T397
Test name
Test status
Simulation time 38880231260 ps
CPU time 50.46 seconds
Started Aug 01 06:52:28 PM PDT 24
Finished Aug 01 06:53:19 PM PDT 24
Peak memory 201352 kb
Host smart-62afeb6b-2ea5-4b57-99ac-93e468188668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420194215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.420194215
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2656542921
Short name T531
Test name
Test status
Simulation time 3783237558 ps
CPU time 9.42 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:52:43 PM PDT 24
Peak memory 201248 kb
Host smart-58ae1191-be18-41d7-b60a-97ec608a6c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656542921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2656542921
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4139036082
Short name T515
Test name
Test status
Simulation time 5919128746 ps
CPU time 12.9 seconds
Started Aug 01 06:52:23 PM PDT 24
Finished Aug 01 06:52:36 PM PDT 24
Peak memory 201288 kb
Host smart-a7d6820a-5965-4e80-bf71-ad3ca7f093b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139036082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4139036082
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1518035353
Short name T532
Test name
Test status
Simulation time 197690373554 ps
CPU time 135.34 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:54:49 PM PDT 24
Peak memory 201444 kb
Host smart-561c28eb-dd66-46ad-8b79-96b06db5d77a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518035353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1518035353
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.111173518
Short name T792
Test name
Test status
Simulation time 378426636 ps
CPU time 0.84 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:52:35 PM PDT 24
Peak memory 201168 kb
Host smart-e9d1f487-22e4-46fa-974b-6d95eeea8392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111173518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.111173518
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.305015301
Short name T302
Test name
Test status
Simulation time 334512232515 ps
CPU time 363.44 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:58:38 PM PDT 24
Peak memory 201480 kb
Host smart-599ee349-e478-4c5a-8ae7-eb62c98aefa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305015301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.305015301
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.165431483
Short name T760
Test name
Test status
Simulation time 332475446076 ps
CPU time 826.29 seconds
Started Aug 01 06:52:39 PM PDT 24
Finished Aug 01 07:06:25 PM PDT 24
Peak memory 201512 kb
Host smart-3128a078-5011-456d-9005-a8524fcf43be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165431483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.165431483
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.63157894
Short name T600
Test name
Test status
Simulation time 326821713549 ps
CPU time 201.36 seconds
Started Aug 01 06:52:37 PM PDT 24
Finished Aug 01 06:55:58 PM PDT 24
Peak memory 201512 kb
Host smart-6857060b-97f6-4f16-a5c6-22b0f161d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63157894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.63157894
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3743090356
Short name T429
Test name
Test status
Simulation time 328298832625 ps
CPU time 744.94 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 07:05:00 PM PDT 24
Peak memory 201432 kb
Host smart-a6e954d1-4f25-454e-b095-aad6366b0e5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743090356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3743090356
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2821292171
Short name T428
Test name
Test status
Simulation time 329176417853 ps
CPU time 754.1 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 07:05:09 PM PDT 24
Peak memory 201508 kb
Host smart-52f38fd7-20c9-47fa-80b4-8f71a4192920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821292171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2821292171
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2574326720
Short name T366
Test name
Test status
Simulation time 325379891811 ps
CPU time 788.91 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 07:05:42 PM PDT 24
Peak memory 201428 kb
Host smart-d5339382-b1d8-4362-b571-a3638a720851
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574326720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2574326720
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3204534784
Short name T603
Test name
Test status
Simulation time 168969701153 ps
CPU time 102.06 seconds
Started Aug 01 06:52:38 PM PDT 24
Finished Aug 01 06:54:20 PM PDT 24
Peak memory 201364 kb
Host smart-b20270de-7665-4e53-afc2-2139394371ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204534784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3204534784
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2576681523
Short name T552
Test name
Test status
Simulation time 430636973543 ps
CPU time 911.7 seconds
Started Aug 01 06:52:39 PM PDT 24
Finished Aug 01 07:07:51 PM PDT 24
Peak memory 201440 kb
Host smart-ec704391-71ca-4c08-90d8-b87f2ca162b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576681523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2576681523
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.101649172
Short name T484
Test name
Test status
Simulation time 85788067740 ps
CPU time 292.58 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:57:27 PM PDT 24
Peak memory 201832 kb
Host smart-3267e62e-0d84-478b-a49d-b7b6ab991370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101649172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.101649172
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2063845774
Short name T97
Test name
Test status
Simulation time 35879704056 ps
CPU time 75.69 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:53:51 PM PDT 24
Peak memory 201380 kb
Host smart-cb2eead0-617a-43f7-823a-6a6cab6af94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063845774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2063845774
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2529235511
Short name T411
Test name
Test status
Simulation time 2907225664 ps
CPU time 4.06 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:52:39 PM PDT 24
Peak memory 201344 kb
Host smart-8bda671a-5e0e-4f41-8283-94ad19e68997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529235511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2529235511
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2552704284
Short name T378
Test name
Test status
Simulation time 5931398388 ps
CPU time 3.34 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:52:37 PM PDT 24
Peak memory 201380 kb
Host smart-02005975-e2b5-454d-9f50-afcd06a817f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552704284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2552704284
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.448379448
Short name T225
Test name
Test status
Simulation time 330931933641 ps
CPU time 100.79 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 06:54:15 PM PDT 24
Peak memory 201544 kb
Host smart-9e857504-4fb6-4ff1-93c6-1bd1435f3836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448379448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
448379448
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3182380887
Short name T287
Test name
Test status
Simulation time 43540345076 ps
CPU time 144.9 seconds
Started Aug 01 06:52:39 PM PDT 24
Finished Aug 01 06:55:05 PM PDT 24
Peak memory 210148 kb
Host smart-fd0d4f5c-dc72-4a0e-8392-dbe101ddc014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182380887 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3182380887
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4015834748
Short name T628
Test name
Test status
Simulation time 536695044049 ps
CPU time 1172.1 seconds
Started Aug 01 06:52:34 PM PDT 24
Finished Aug 01 07:12:06 PM PDT 24
Peak memory 201444 kb
Host smart-a8a73900-9076-4fa2-b950-6bbe0efaa88d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015834748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4015834748
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2219901806
Short name T585
Test name
Test status
Simulation time 337569858585 ps
CPU time 714.15 seconds
Started Aug 01 06:52:37 PM PDT 24
Finished Aug 01 07:04:31 PM PDT 24
Peak memory 201460 kb
Host smart-d7417dca-8bb0-4cef-89ed-d5daf59d6c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219901806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2219901806
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2836905202
Short name T323
Test name
Test status
Simulation time 497228521206 ps
CPU time 588.16 seconds
Started Aug 01 06:52:40 PM PDT 24
Finished Aug 01 07:02:28 PM PDT 24
Peak memory 201444 kb
Host smart-7fb7c604-53a2-476d-a7af-669ddb7e8b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836905202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2836905202
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2964822467
Short name T640
Test name
Test status
Simulation time 164541752648 ps
CPU time 149.74 seconds
Started Aug 01 06:52:39 PM PDT 24
Finished Aug 01 06:55:09 PM PDT 24
Peak memory 201440 kb
Host smart-f04b080e-6cc4-48f1-9a0b-8ed1f894de99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964822467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2964822467
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1547936686
Short name T598
Test name
Test status
Simulation time 329247276425 ps
CPU time 230.57 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:56:23 PM PDT 24
Peak memory 201400 kb
Host smart-eb3e2ccd-904e-4971-a698-59a571f27f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547936686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1547936686
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1094939828
Short name T121
Test name
Test status
Simulation time 169253510117 ps
CPU time 106.03 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:54:19 PM PDT 24
Peak memory 201412 kb
Host smart-e3526d53-575b-4aea-8c4b-a618f4bbc6a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094939828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1094939828
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3231675712
Short name T791
Test name
Test status
Simulation time 374949686439 ps
CPU time 196.51 seconds
Started Aug 01 06:52:33 PM PDT 24
Finished Aug 01 06:55:50 PM PDT 24
Peak memory 201444 kb
Host smart-adec5dab-da13-42c8-b08c-952161267290
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231675712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3231675712
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2461973438
Short name T580
Test name
Test status
Simulation time 585797850107 ps
CPU time 1263.39 seconds
Started Aug 01 06:52:40 PM PDT 24
Finished Aug 01 07:13:44 PM PDT 24
Peak memory 201368 kb
Host smart-2d703aad-0ed8-4e5c-bff1-994074a42758
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461973438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2461973438
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4056642579
Short name T214
Test name
Test status
Simulation time 88494291936 ps
CPU time 321.45 seconds
Started Aug 01 06:52:41 PM PDT 24
Finished Aug 01 06:58:03 PM PDT 24
Peak memory 201744 kb
Host smart-fa59dd60-f785-4209-ac80-834eff6cc1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056642579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4056642579
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1275488935
Short name T413
Test name
Test status
Simulation time 35624916242 ps
CPU time 79.21 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:53:55 PM PDT 24
Peak memory 201312 kb
Host smart-d7c32a0b-364c-410b-b96b-7f81060e4b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275488935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1275488935
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4243609782
Short name T480
Test name
Test status
Simulation time 4297384616 ps
CPU time 3.29 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:52:38 PM PDT 24
Peak memory 201304 kb
Host smart-081667c7-ad9d-4461-92c6-c766e1c5f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243609782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4243609782
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3992866151
Short name T360
Test name
Test status
Simulation time 5761904114 ps
CPU time 7.17 seconds
Started Aug 01 06:52:38 PM PDT 24
Finished Aug 01 06:52:45 PM PDT 24
Peak memory 201324 kb
Host smart-940dae8e-ef1f-412c-9526-d6c8440f1492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992866151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3992866151
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.989385609
Short name T684
Test name
Test status
Simulation time 403436584517 ps
CPU time 53.91 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:53:29 PM PDT 24
Peak memory 201436 kb
Host smart-c66c4615-6681-4ea2-a645-58520f35ab0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989385609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
989385609
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2108013384
Short name T18
Test name
Test status
Simulation time 297523586216 ps
CPU time 463.23 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 07:00:28 PM PDT 24
Peak memory 210276 kb
Host smart-121edb1e-77f2-4a36-b028-cc2c40957b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108013384 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2108013384
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4476335
Short name T510
Test name
Test status
Simulation time 417360656 ps
CPU time 0.83 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 06:52:04 PM PDT 24
Peak memory 201240 kb
Host smart-70715965-886f-45ac-bee6-503d0875b859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4476335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4476335
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3181243364
Short name T258
Test name
Test status
Simulation time 159963944653 ps
CPU time 280.3 seconds
Started Aug 01 06:51:46 PM PDT 24
Finished Aug 01 06:56:27 PM PDT 24
Peak memory 201456 kb
Host smart-b137e2bc-a5b8-435a-b4c4-5924549a9383
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181243364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3181243364
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2598060036
Short name T685
Test name
Test status
Simulation time 355848958562 ps
CPU time 814.42 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 07:05:18 PM PDT 24
Peak memory 201516 kb
Host smart-0d3f8250-22fa-4cfe-b6a6-73239f8440f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598060036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2598060036
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.962584751
Short name T220
Test name
Test status
Simulation time 156586546156 ps
CPU time 332.95 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:57:21 PM PDT 24
Peak memory 201460 kb
Host smart-784ba18d-2fe1-4b5d-97d0-829e876c29d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962584751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.962584751
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2166526061
Short name T255
Test name
Test status
Simulation time 160299804233 ps
CPU time 193.62 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:55:01 PM PDT 24
Peak memory 201460 kb
Host smart-c67f1236-0020-4a0e-8902-a3baa35af744
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166526061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2166526061
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3374984623
Short name T205
Test name
Test status
Simulation time 500323235007 ps
CPU time 1111.66 seconds
Started Aug 01 06:51:45 PM PDT 24
Finished Aug 01 07:10:17 PM PDT 24
Peak memory 201416 kb
Host smart-43cb417a-6ddd-40ee-b36e-d31586c4a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374984623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3374984623
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2695691708
Short name T563
Test name
Test status
Simulation time 168964249869 ps
CPU time 322.53 seconds
Started Aug 01 06:51:47 PM PDT 24
Finished Aug 01 06:57:10 PM PDT 24
Peak memory 201480 kb
Host smart-eaa74d9a-c45e-44a0-bbed-61468b4d6f8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695691708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2695691708
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.644456422
Short name T321
Test name
Test status
Simulation time 550855721994 ps
CPU time 175.6 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:54:55 PM PDT 24
Peak memory 201544 kb
Host smart-05913e4b-6ca6-4c2d-8c6e-82a2a134fe49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644456422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.644456422
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.701991438
Short name T561
Test name
Test status
Simulation time 597501343809 ps
CPU time 1392.49 seconds
Started Aug 01 06:51:49 PM PDT 24
Finished Aug 01 07:15:02 PM PDT 24
Peak memory 201440 kb
Host smart-a4f4239c-940e-4306-b643-4e176932783d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701991438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.701991438
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.77850003
Short name T68
Test name
Test status
Simulation time 118254209619 ps
CPU time 624 seconds
Started Aug 01 06:51:44 PM PDT 24
Finished Aug 01 07:02:09 PM PDT 24
Peak memory 201824 kb
Host smart-313bf68c-3afe-4cf4-8fed-f92bbf623eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77850003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.77850003
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2704085576
Short name T679
Test name
Test status
Simulation time 36518785624 ps
CPU time 20.37 seconds
Started Aug 01 06:51:48 PM PDT 24
Finished Aug 01 06:52:09 PM PDT 24
Peak memory 201352 kb
Host smart-8cd3984d-ffe5-435d-baae-9775912f9036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704085576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2704085576
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3550465859
Short name T180
Test name
Test status
Simulation time 4156592143 ps
CPU time 10.73 seconds
Started Aug 01 06:51:43 PM PDT 24
Finished Aug 01 06:51:54 PM PDT 24
Peak memory 201264 kb
Host smart-ce193ca9-1bc4-482c-8377-a02bddda399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550465859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3550465859
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1656345270
Short name T560
Test name
Test status
Simulation time 5932565820 ps
CPU time 3.99 seconds
Started Aug 01 06:51:45 PM PDT 24
Finished Aug 01 06:51:49 PM PDT 24
Peak memory 201352 kb
Host smart-180a7114-94ff-45da-99c0-642d9cb30c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656345270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1656345270
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.157633792
Short name T159
Test name
Test status
Simulation time 306957389200 ps
CPU time 400.1 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:58:39 PM PDT 24
Peak memory 211428 kb
Host smart-86d3d3d8-90a5-4a7a-b884-c5b2012424b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157633792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.157633792
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3922523249
Short name T324
Test name
Test status
Simulation time 73345798844 ps
CPU time 57.04 seconds
Started Aug 01 06:51:55 PM PDT 24
Finished Aug 01 06:52:52 PM PDT 24
Peak memory 209916 kb
Host smart-7affad23-6727-4336-95b8-cd533ff8e54e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922523249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3922523249
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2157694222
Short name T527
Test name
Test status
Simulation time 333024326 ps
CPU time 1.27 seconds
Started Aug 01 06:52:47 PM PDT 24
Finished Aug 01 06:52:49 PM PDT 24
Peak memory 201224 kb
Host smart-86118827-0060-4dc2-b544-d690a9e35790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157694222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2157694222
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.533867703
Short name T190
Test name
Test status
Simulation time 178014171383 ps
CPU time 111.21 seconds
Started Aug 01 06:52:46 PM PDT 24
Finished Aug 01 06:54:39 PM PDT 24
Peak memory 201512 kb
Host smart-a4ba8e79-77cf-444c-bbe6-61734dc28b08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533867703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.533867703
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3749502070
Short name T265
Test name
Test status
Simulation time 532230838166 ps
CPU time 1168.31 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 07:12:13 PM PDT 24
Peak memory 201432 kb
Host smart-53555bf0-850e-406d-b7d8-538623925685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749502070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3749502070
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4279292214
Short name T442
Test name
Test status
Simulation time 331403362323 ps
CPU time 774.25 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 07:05:39 PM PDT 24
Peak memory 201492 kb
Host smart-6711da38-8bf1-47be-9d1f-db3fdf3f446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279292214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4279292214
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2979231686
Short name T470
Test name
Test status
Simulation time 164343028672 ps
CPU time 193.18 seconds
Started Aug 01 06:52:47 PM PDT 24
Finished Aug 01 06:56:01 PM PDT 24
Peak memory 201476 kb
Host smart-ea5c44cd-5271-4293-8388-8cfc9264dee6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979231686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2979231686
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3566734128
Short name T591
Test name
Test status
Simulation time 168941175572 ps
CPU time 49.97 seconds
Started Aug 01 06:52:46 PM PDT 24
Finished Aug 01 06:53:38 PM PDT 24
Peak memory 201408 kb
Host smart-455b3c2b-a84d-4c04-ab6b-41a7b557a6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566734128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3566734128
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3287286748
Short name T406
Test name
Test status
Simulation time 497240520192 ps
CPU time 319.62 seconds
Started Aug 01 06:52:47 PM PDT 24
Finished Aug 01 06:58:07 PM PDT 24
Peak memory 201468 kb
Host smart-ed923cdb-4466-4ec6-86fb-de5c01a3f119
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287286748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3287286748
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3611747893
Short name T229
Test name
Test status
Simulation time 198337896159 ps
CPU time 55.61 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 06:53:40 PM PDT 24
Peak memory 201440 kb
Host smart-d6f0a7b2-0c38-493b-a521-295be4587537
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611747893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3611747893
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2390547474
Short name T467
Test name
Test status
Simulation time 381497041835 ps
CPU time 138.68 seconds
Started Aug 01 06:52:43 PM PDT 24
Finished Aug 01 06:55:02 PM PDT 24
Peak memory 201432 kb
Host smart-61de9b75-2944-416b-8c59-21ed79ccdb62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390547474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2390547474
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3221772671
Short name T424
Test name
Test status
Simulation time 127356952232 ps
CPU time 653.79 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 07:03:38 PM PDT 24
Peak memory 201808 kb
Host smart-1a51e0c6-36d5-4d3f-850b-486eabadbf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221772671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3221772671
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2630622149
Short name T696
Test name
Test status
Simulation time 29503616729 ps
CPU time 67.87 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 06:53:53 PM PDT 24
Peak memory 201332 kb
Host smart-2a49e27c-7464-406d-8a80-8112fa9c80bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630622149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2630622149
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3693105356
Short name T773
Test name
Test status
Simulation time 4244029470 ps
CPU time 11.27 seconds
Started Aug 01 06:52:47 PM PDT 24
Finished Aug 01 06:52:59 PM PDT 24
Peak memory 201300 kb
Host smart-83c54f25-e0b6-436a-90f6-55db8d44077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693105356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3693105356
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1631294986
Short name T450
Test name
Test status
Simulation time 5581847685 ps
CPU time 11.81 seconds
Started Aug 01 06:52:35 PM PDT 24
Finished Aug 01 06:52:47 PM PDT 24
Peak memory 201372 kb
Host smart-c4d9c0d0-6546-4f32-a78e-6134ea9afc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631294986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1631294986
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3527417717
Short name T513
Test name
Test status
Simulation time 350860443097 ps
CPU time 128.68 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 06:54:53 PM PDT 24
Peak memory 201444 kb
Host smart-855ae75c-c91d-4b87-a60e-51ddcff065d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527417717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3527417717
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1010581112
Short name T124
Test name
Test status
Simulation time 257612238817 ps
CPU time 150.32 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 06:55:16 PM PDT 24
Peak memory 209752 kb
Host smart-3c8f019c-67e6-416f-8840-d2e34953aa73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010581112 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1010581112
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.469546982
Short name T697
Test name
Test status
Simulation time 281297920 ps
CPU time 1.25 seconds
Started Aug 01 06:52:47 PM PDT 24
Finished Aug 01 06:52:49 PM PDT 24
Peak memory 201224 kb
Host smart-a6267917-59b8-4a0c-852e-8f67bebd8b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469546982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.469546982
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.4275547639
Short name T171
Test name
Test status
Simulation time 487136832879 ps
CPU time 987.74 seconds
Started Aug 01 06:52:48 PM PDT 24
Finished Aug 01 07:09:16 PM PDT 24
Peak memory 201424 kb
Host smart-56da8cbf-19c5-4fa8-bc2e-78f1c2fab842
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275547639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.4275547639
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1105488199
Short name T64
Test name
Test status
Simulation time 341090500776 ps
CPU time 389.08 seconds
Started Aug 01 06:52:48 PM PDT 24
Finished Aug 01 06:59:17 PM PDT 24
Peak memory 201464 kb
Host smart-cceea2c2-62d2-4402-b872-20f50157f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105488199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1105488199
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1364718175
Short name T493
Test name
Test status
Simulation time 160893534743 ps
CPU time 101.26 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 06:54:26 PM PDT 24
Peak memory 201436 kb
Host smart-fa3c30a7-0af9-4452-a872-5a894f969c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364718175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1364718175
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.568821352
Short name T388
Test name
Test status
Simulation time 485185366848 ps
CPU time 293.85 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 06:57:39 PM PDT 24
Peak memory 201468 kb
Host smart-8092d00a-7380-436e-b3a4-7b737d417691
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=568821352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.568821352
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2193823057
Short name T462
Test name
Test status
Simulation time 322064134521 ps
CPU time 317.45 seconds
Started Aug 01 06:52:46 PM PDT 24
Finished Aug 01 06:58:03 PM PDT 24
Peak memory 201420 kb
Host smart-07b5a4e1-757c-4456-8f44-46e10ae50677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193823057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2193823057
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2395444898
Short name T430
Test name
Test status
Simulation time 166023648047 ps
CPU time 83.63 seconds
Started Aug 01 06:52:46 PM PDT 24
Finished Aug 01 06:54:09 PM PDT 24
Peak memory 201480 kb
Host smart-ec53874c-c121-4b69-b1e2-746c0e08534a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395444898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2395444898
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3386602127
Short name T272
Test name
Test status
Simulation time 537680968389 ps
CPU time 610.24 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 07:02:56 PM PDT 24
Peak memory 201468 kb
Host smart-0efa8b35-43f3-4f21-963f-0102700daf3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386602127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3386602127
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.127170437
Short name T63
Test name
Test status
Simulation time 405890229888 ps
CPU time 176.74 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 06:55:42 PM PDT 24
Peak memory 201444 kb
Host smart-648a0dc9-86a5-4283-9a96-4cacb8961f96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127170437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.127170437
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3440349454
Short name T476
Test name
Test status
Simulation time 112039110465 ps
CPU time 595.47 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 07:02:41 PM PDT 24
Peak memory 201828 kb
Host smart-c149cec0-0437-4e38-9b94-9728da0eb6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440349454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3440349454
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.279488511
Short name T767
Test name
Test status
Simulation time 27794887082 ps
CPU time 11.61 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 06:52:56 PM PDT 24
Peak memory 201548 kb
Host smart-148728fd-c02f-4d6c-8f35-78d482641388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279488511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.279488511
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2006987976
Short name T509
Test name
Test status
Simulation time 3987750028 ps
CPU time 5.04 seconds
Started Aug 01 06:52:44 PM PDT 24
Finished Aug 01 06:52:49 PM PDT 24
Peak memory 201340 kb
Host smart-e47fc34f-88ce-40a4-90f9-2096d4bb082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006987976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2006987976
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.104715014
Short name T763
Test name
Test status
Simulation time 5547645283 ps
CPU time 3.97 seconds
Started Aug 01 06:52:48 PM PDT 24
Finished Aug 01 06:52:52 PM PDT 24
Peak memory 201380 kb
Host smart-ed9c046a-3464-4ff8-8bd7-612f9257f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104715014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.104715014
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2064727693
Short name T331
Test name
Test status
Simulation time 365947443409 ps
CPU time 783.25 seconds
Started Aug 01 06:52:48 PM PDT 24
Finished Aug 01 07:05:51 PM PDT 24
Peak memory 201512 kb
Host smart-258d6afb-14be-4307-9535-eda8e34774d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064727693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2064727693
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1518511854
Short name T584
Test name
Test status
Simulation time 15578897921 ps
CPU time 50.33 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 06:53:36 PM PDT 24
Peak memory 202240 kb
Host smart-9dba8919-6706-4237-988f-3ba25a1363b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518511854 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1518511854
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3188073580
Short name T86
Test name
Test status
Simulation time 491565754 ps
CPU time 1.68 seconds
Started Aug 01 06:52:55 PM PDT 24
Finished Aug 01 06:52:57 PM PDT 24
Peak memory 201252 kb
Host smart-0fe34016-fbd2-46c2-b44b-aa69f007895b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188073580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3188073580
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4131097321
Short name T172
Test name
Test status
Simulation time 527071621979 ps
CPU time 439.41 seconds
Started Aug 01 06:52:55 PM PDT 24
Finished Aug 01 07:00:14 PM PDT 24
Peak memory 201312 kb
Host smart-a4c6c777-f415-4e42-8197-1847ace3f17b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131097321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4131097321
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3270540265
Short name T474
Test name
Test status
Simulation time 491682626610 ps
CPU time 163.28 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 06:55:38 PM PDT 24
Peak memory 201460 kb
Host smart-4b382e2c-2678-4522-ab6e-fa5061303060
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270540265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3270540265
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4243502268
Short name T781
Test name
Test status
Simulation time 331700810951 ps
CPU time 175 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 06:55:41 PM PDT 24
Peak memory 201456 kb
Host smart-d1a8265d-a14e-4664-aa8a-ae722bdc17d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243502268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4243502268
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.911651452
Short name T759
Test name
Test status
Simulation time 492270418547 ps
CPU time 1129.64 seconds
Started Aug 01 06:52:45 PM PDT 24
Finished Aug 01 07:11:35 PM PDT 24
Peak memory 201472 kb
Host smart-fc216528-05f9-405c-9d43-f0b2b8e383c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=911651452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.911651452
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.4106152212
Short name T203
Test name
Test status
Simulation time 564220404361 ps
CPU time 331.42 seconds
Started Aug 01 06:52:55 PM PDT 24
Finished Aug 01 06:58:26 PM PDT 24
Peak memory 201432 kb
Host smart-36a8933d-58ab-4ebf-9ad8-f5098c7c4878
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106152212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.4106152212
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3307726416
Short name T700
Test name
Test status
Simulation time 607804007731 ps
CPU time 178.86 seconds
Started Aug 01 06:52:57 PM PDT 24
Finished Aug 01 06:55:56 PM PDT 24
Peak memory 201388 kb
Host smart-e3111940-a832-4906-8d3b-d1b5a8e78321
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307726416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3307726416
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.369372933
Short name T620
Test name
Test status
Simulation time 76268717790 ps
CPU time 389.39 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 06:59:24 PM PDT 24
Peak memory 201832 kb
Host smart-ec848809-ebd1-401b-ab89-64c4682ae85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369372933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.369372933
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3107500324
Short name T356
Test name
Test status
Simulation time 41664840083 ps
CPU time 24.7 seconds
Started Aug 01 06:52:53 PM PDT 24
Finished Aug 01 06:53:18 PM PDT 24
Peak memory 201364 kb
Host smart-48b2c1c9-8c80-49f7-b898-30d71a34c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107500324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3107500324
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3554391338
Short name T34
Test name
Test status
Simulation time 5277515374 ps
CPU time 1.85 seconds
Started Aug 01 06:52:56 PM PDT 24
Finished Aug 01 06:52:59 PM PDT 24
Peak memory 201360 kb
Host smart-cf8541fb-6b8f-4611-a542-cb69d6747955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554391338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3554391338
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1853026860
Short name T755
Test name
Test status
Simulation time 5959759882 ps
CPU time 14.26 seconds
Started Aug 01 06:52:46 PM PDT 24
Finished Aug 01 06:53:00 PM PDT 24
Peak memory 201292 kb
Host smart-2188ed71-c229-4848-ac57-939febc19c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853026860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1853026860
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2525391693
Short name T417
Test name
Test status
Simulation time 37451396808 ps
CPU time 41.91 seconds
Started Aug 01 06:52:58 PM PDT 24
Finished Aug 01 06:53:40 PM PDT 24
Peak memory 201440 kb
Host smart-c3627340-8938-417a-a794-045aa92b3773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525391693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2525391693
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2523379533
Short name T60
Test name
Test status
Simulation time 99452014228 ps
CPU time 127.33 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 06:55:02 PM PDT 24
Peak memory 210120 kb
Host smart-682d7b3c-863f-48e1-b42c-c82afac31d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523379533 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2523379533
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.80387203
Short name T752
Test name
Test status
Simulation time 326678388 ps
CPU time 0.81 seconds
Started Aug 01 06:52:58 PM PDT 24
Finished Aug 01 06:52:59 PM PDT 24
Peak memory 201292 kb
Host smart-3877e3a8-737f-4f57-a156-fff5db03528b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80387203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.80387203
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1784469143
Short name T250
Test name
Test status
Simulation time 339809868503 ps
CPU time 790.13 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 07:06:04 PM PDT 24
Peak memory 201424 kb
Host smart-a1b03e5d-02f6-4065-b834-42593ac6aca4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784469143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1784469143
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2903523458
Short name T528
Test name
Test status
Simulation time 167468489161 ps
CPU time 84.72 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 06:54:19 PM PDT 24
Peak memory 201496 kb
Host smart-ae21eb86-3a88-413e-9553-2a4b7b337d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903523458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2903523458
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1180930707
Short name T641
Test name
Test status
Simulation time 161019809814 ps
CPU time 137.68 seconds
Started Aug 01 06:52:55 PM PDT 24
Finished Aug 01 06:55:13 PM PDT 24
Peak memory 201372 kb
Host smart-88c5d989-5059-47ea-aeaa-419c58bec4c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180930707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1180930707
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1381130114
Short name T597
Test name
Test status
Simulation time 161556642864 ps
CPU time 93.56 seconds
Started Aug 01 06:52:56 PM PDT 24
Finished Aug 01 06:54:31 PM PDT 24
Peak memory 201448 kb
Host smart-188299b7-cdec-4b86-9bcd-6fd857db80d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381130114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1381130114
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1892436081
Short name T578
Test name
Test status
Simulation time 332970749172 ps
CPU time 185.51 seconds
Started Aug 01 06:52:56 PM PDT 24
Finished Aug 01 06:56:03 PM PDT 24
Peak memory 201400 kb
Host smart-a00d6e47-1853-4c8c-9e59-cd79f951bc4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892436081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1892436081
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3625798126
Short name T692
Test name
Test status
Simulation time 343572892088 ps
CPU time 716.23 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 07:04:50 PM PDT 24
Peak memory 201388 kb
Host smart-121f5dc9-e999-42c4-961a-69fef65e8441
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625798126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3625798126
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3467730640
Short name T394
Test name
Test status
Simulation time 192634792727 ps
CPU time 109.94 seconds
Started Aug 01 06:52:55 PM PDT 24
Finished Aug 01 06:54:45 PM PDT 24
Peak memory 201456 kb
Host smart-b2c769b6-88be-4825-924b-65685c71b9e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467730640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3467730640
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1357416913
Short name T348
Test name
Test status
Simulation time 97237075608 ps
CPU time 402.93 seconds
Started Aug 01 06:52:53 PM PDT 24
Finished Aug 01 06:59:36 PM PDT 24
Peak memory 201796 kb
Host smart-bb71cda8-4625-4241-a724-d9b9a3d48ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357416913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1357416913
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3209888098
Short name T660
Test name
Test status
Simulation time 39099052799 ps
CPU time 10.19 seconds
Started Aug 01 06:52:56 PM PDT 24
Finished Aug 01 06:53:07 PM PDT 24
Peak memory 201384 kb
Host smart-54ccb08f-3896-439c-b45a-99ebb86f7fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209888098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3209888098
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2581354345
Short name T569
Test name
Test status
Simulation time 5086773922 ps
CPU time 5.91 seconds
Started Aug 01 06:52:53 PM PDT 24
Finished Aug 01 06:53:00 PM PDT 24
Peak memory 201308 kb
Host smart-411341cd-be87-4c88-8d8e-9ad9cd7c3b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581354345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2581354345
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1057700559
Short name T109
Test name
Test status
Simulation time 5725008054 ps
CPU time 13.94 seconds
Started Aug 01 06:52:53 PM PDT 24
Finished Aug 01 06:53:07 PM PDT 24
Peak memory 201352 kb
Host smart-e1ded9ce-0084-4377-82da-2552f03c1f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057700559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1057700559
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1415987338
Short name T25
Test name
Test status
Simulation time 145152410704 ps
CPU time 60.24 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 06:53:54 PM PDT 24
Peak memory 209732 kb
Host smart-5ed01a30-d228-461e-b3ef-4d7d38c0d543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415987338 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1415987338
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1588395115
Short name T373
Test name
Test status
Simulation time 380478192 ps
CPU time 1.47 seconds
Started Aug 01 06:53:09 PM PDT 24
Finished Aug 01 06:53:10 PM PDT 24
Peak memory 201244 kb
Host smart-21099061-8b3c-4543-84b8-88e19f7afad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588395115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1588395115
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1127706570
Short name T267
Test name
Test status
Simulation time 193188281167 ps
CPU time 29.44 seconds
Started Aug 01 06:53:03 PM PDT 24
Finished Aug 01 06:53:33 PM PDT 24
Peak memory 201432 kb
Host smart-1cba7f09-12f1-491a-b337-1365233d3d76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127706570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1127706570
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3332495420
Short name T520
Test name
Test status
Simulation time 166956332383 ps
CPU time 75.83 seconds
Started Aug 01 06:52:55 PM PDT 24
Finished Aug 01 06:54:11 PM PDT 24
Peak memory 201452 kb
Host smart-2ebac745-fcdf-491d-8345-156568190080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332495420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3332495420
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2613883625
Short name T595
Test name
Test status
Simulation time 163427396353 ps
CPU time 361.77 seconds
Started Aug 01 06:52:55 PM PDT 24
Finished Aug 01 06:58:57 PM PDT 24
Peak memory 201300 kb
Host smart-7228a95c-988c-4ef2-8aad-6cd3ac8a9db3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613883625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2613883625
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2056056629
Short name T634
Test name
Test status
Simulation time 491948231347 ps
CPU time 1170.95 seconds
Started Aug 01 06:52:58 PM PDT 24
Finished Aug 01 07:12:29 PM PDT 24
Peak memory 201512 kb
Host smart-f93b2662-d16b-41e2-9b4e-9a4658e6bcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056056629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2056056629
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1639155982
Short name T631
Test name
Test status
Simulation time 489521318786 ps
CPU time 1136.18 seconds
Started Aug 01 06:52:57 PM PDT 24
Finished Aug 01 07:11:53 PM PDT 24
Peak memory 201372 kb
Host smart-67bd9a83-6700-4aa2-b423-ee38c3693782
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639155982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1639155982
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2861256644
Short name T490
Test name
Test status
Simulation time 374648871937 ps
CPU time 229.23 seconds
Started Aug 01 06:53:08 PM PDT 24
Finished Aug 01 06:56:57 PM PDT 24
Peak memory 201388 kb
Host smart-6eb6a0ac-4a2e-4c12-b4c4-8addfbc8d7dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861256644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2861256644
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1778503510
Short name T674
Test name
Test status
Simulation time 593068855330 ps
CPU time 1374.67 seconds
Started Aug 01 06:53:04 PM PDT 24
Finished Aug 01 07:15:58 PM PDT 24
Peak memory 201428 kb
Host smart-ecae4843-3a2f-4fbb-8c8c-d19810f2c44e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778503510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1778503510
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1450562887
Short name T652
Test name
Test status
Simulation time 104320848535 ps
CPU time 361.33 seconds
Started Aug 01 06:53:09 PM PDT 24
Finished Aug 01 06:59:10 PM PDT 24
Peak memory 201860 kb
Host smart-977e5f53-1900-4517-a0f0-e935987ea82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450562887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1450562887
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1407616911
Short name T793
Test name
Test status
Simulation time 39448090164 ps
CPU time 24.05 seconds
Started Aug 01 06:53:04 PM PDT 24
Finished Aug 01 06:53:28 PM PDT 24
Peak memory 201320 kb
Host smart-555fe443-222b-4458-be96-ec89e91de3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407616911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1407616911
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3426453333
Short name T550
Test name
Test status
Simulation time 3901998747 ps
CPU time 10.78 seconds
Started Aug 01 06:53:05 PM PDT 24
Finished Aug 01 06:53:16 PM PDT 24
Peak memory 201348 kb
Host smart-255cb898-a758-45dd-9d1a-75887fd439f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426453333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3426453333
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2962049483
Short name T754
Test name
Test status
Simulation time 5960422180 ps
CPU time 13.44 seconds
Started Aug 01 06:52:54 PM PDT 24
Finished Aug 01 06:53:07 PM PDT 24
Peak memory 201212 kb
Host smart-91f13074-285a-4311-ab29-58da95b9f7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962049483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2962049483
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2878333805
Short name T261
Test name
Test status
Simulation time 283353820852 ps
CPU time 896.26 seconds
Started Aug 01 06:53:04 PM PDT 24
Finished Aug 01 07:08:00 PM PDT 24
Peak memory 201796 kb
Host smart-00ec590a-de91-49f8-9ee0-a1b72351796c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878333805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2878333805
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1180024569
Short name T52
Test name
Test status
Simulation time 34261195218 ps
CPU time 66.75 seconds
Started Aug 01 06:53:06 PM PDT 24
Finished Aug 01 06:54:13 PM PDT 24
Peak memory 210152 kb
Host smart-aa69e605-08fd-404c-b86b-e68d4406ab05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180024569 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1180024569
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2789475879
Short name T407
Test name
Test status
Simulation time 397743000 ps
CPU time 1.43 seconds
Started Aug 01 06:53:17 PM PDT 24
Finished Aug 01 06:53:18 PM PDT 24
Peak memory 201248 kb
Host smart-0cacf100-80c2-4046-82c2-1b617da11b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789475879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2789475879
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2949578196
Short name T456
Test name
Test status
Simulation time 165616179807 ps
CPU time 39.24 seconds
Started Aug 01 06:53:06 PM PDT 24
Finished Aug 01 06:53:45 PM PDT 24
Peak memory 201496 kb
Host smart-62d78cd1-022d-4eb1-9955-ce0d5a6da6be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949578196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2949578196
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3461888455
Short name T725
Test name
Test status
Simulation time 164738761097 ps
CPU time 97.43 seconds
Started Aug 01 06:53:10 PM PDT 24
Finished Aug 01 06:54:47 PM PDT 24
Peak memory 201456 kb
Host smart-389e3000-8d3b-4724-b53e-f8578d88d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461888455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3461888455
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4256906366
Short name T788
Test name
Test status
Simulation time 494348716410 ps
CPU time 1075.36 seconds
Started Aug 01 06:53:07 PM PDT 24
Finished Aug 01 07:11:02 PM PDT 24
Peak memory 201460 kb
Host smart-efc7dd83-093c-4e3d-af80-ee35f37d50aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256906366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4256906366
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.877021717
Short name T607
Test name
Test status
Simulation time 494696258514 ps
CPU time 221.6 seconds
Started Aug 01 06:53:06 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 201480 kb
Host smart-768a2985-5829-4d82-a6d4-e369e8b091cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=877021717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.877021717
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1711253690
Short name T116
Test name
Test status
Simulation time 166820443330 ps
CPU time 187.24 seconds
Started Aug 01 06:53:04 PM PDT 24
Finished Aug 01 06:56:12 PM PDT 24
Peak memory 201452 kb
Host smart-e2e3edcc-8ddb-429c-a3c6-b79e2555e7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711253690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1711253690
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3167822221
Short name T437
Test name
Test status
Simulation time 165320150306 ps
CPU time 104.2 seconds
Started Aug 01 06:53:04 PM PDT 24
Finished Aug 01 06:54:48 PM PDT 24
Peak memory 201428 kb
Host smart-1bc00cce-8c5c-46bc-bca6-b8e3fc026b12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167822221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3167822221
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3101159285
Short name T519
Test name
Test status
Simulation time 247312623687 ps
CPU time 146.01 seconds
Started Aug 01 06:53:09 PM PDT 24
Finished Aug 01 06:55:35 PM PDT 24
Peak memory 201492 kb
Host smart-fb612a9a-9059-4a41-9d6a-5da2b6833d6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101159285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3101159285
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.338427011
Short name T465
Test name
Test status
Simulation time 192531286610 ps
CPU time 425.25 seconds
Started Aug 01 06:53:07 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 201388 kb
Host smart-95cd17a6-9bda-4bec-8b8a-a7cb795b5ef6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338427011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.338427011
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2119413465
Short name T28
Test name
Test status
Simulation time 80906056368 ps
CPU time 395.4 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 06:59:49 PM PDT 24
Peak memory 201840 kb
Host smart-003b4ecb-79d2-4318-b9a2-7c857f19e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119413465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2119413465
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1000289340
Short name T587
Test name
Test status
Simulation time 32778777974 ps
CPU time 6.57 seconds
Started Aug 01 06:53:04 PM PDT 24
Finished Aug 01 06:53:11 PM PDT 24
Peak memory 201332 kb
Host smart-75924b7f-c352-41ac-be64-ab227c7f61af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000289340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1000289340
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1398484199
Short name T469
Test name
Test status
Simulation time 2890815340 ps
CPU time 7.6 seconds
Started Aug 01 06:53:05 PM PDT 24
Finished Aug 01 06:53:12 PM PDT 24
Peak memory 201352 kb
Host smart-fd0a322f-ebef-4144-a373-ed5d01df94f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398484199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1398484199
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.640838512
Short name T370
Test name
Test status
Simulation time 6003041727 ps
CPU time 7.74 seconds
Started Aug 01 06:53:04 PM PDT 24
Finished Aug 01 06:53:12 PM PDT 24
Peak memory 201380 kb
Host smart-dcdb463c-45cf-4d71-be8b-4a2027191712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640838512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.640838512
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.22212398
Short name T740
Test name
Test status
Simulation time 652847569989 ps
CPU time 1603.15 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 07:19:58 PM PDT 24
Peak memory 201400 kb
Host smart-c828a619-619f-40c7-b61c-304ae9fdaafd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22212398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.22212398
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3961158533
Short name T87
Test name
Test status
Simulation time 388413657 ps
CPU time 1.29 seconds
Started Aug 01 06:53:15 PM PDT 24
Finished Aug 01 06:53:17 PM PDT 24
Peak memory 201168 kb
Host smart-68cd4241-b341-423e-a2ac-798364434a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961158533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3961158533
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2276133927
Short name T549
Test name
Test status
Simulation time 184286746307 ps
CPU time 418.13 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 201408 kb
Host smart-76f4084d-2e59-4845-a449-1285a770a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276133927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2276133927
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2928535304
Short name T191
Test name
Test status
Simulation time 499532128984 ps
CPU time 91.8 seconds
Started Aug 01 06:53:15 PM PDT 24
Finished Aug 01 06:54:47 PM PDT 24
Peak memory 201432 kb
Host smart-d4ec6cf9-349c-4e0a-af9d-c1d99f8831a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928535304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2928535304
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3057696427
Short name T609
Test name
Test status
Simulation time 159607445342 ps
CPU time 181.33 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 06:56:16 PM PDT 24
Peak memory 201452 kb
Host smart-36de57a9-0125-4488-b51f-bb5d203729ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057696427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3057696427
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1600036384
Short name T667
Test name
Test status
Simulation time 160872300320 ps
CPU time 343.89 seconds
Started Aug 01 06:53:17 PM PDT 24
Finished Aug 01 06:59:01 PM PDT 24
Peak memory 201524 kb
Host smart-c4a620b7-4cf5-47c2-9c45-cff6e917b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600036384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1600036384
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3583558286
Short name T7
Test name
Test status
Simulation time 324569411040 ps
CPU time 189.66 seconds
Started Aug 01 06:53:16 PM PDT 24
Finished Aug 01 06:56:26 PM PDT 24
Peak memory 201400 kb
Host smart-d829ba00-4a7d-4941-9098-3fb4466223fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583558286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3583558286
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2914851507
Short name T206
Test name
Test status
Simulation time 201549198104 ps
CPU time 99.7 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 06:54:54 PM PDT 24
Peak memory 201544 kb
Host smart-d57b254d-4cc0-423d-8247-ba1735835280
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914851507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2914851507
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.4019347477
Short name T505
Test name
Test status
Simulation time 195603365607 ps
CPU time 199.62 seconds
Started Aug 01 06:53:15 PM PDT 24
Finished Aug 01 06:56:35 PM PDT 24
Peak memory 201468 kb
Host smart-3db50612-77b2-48bd-aeb0-c16f32dad17a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019347477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.4019347477
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2199658147
Short name T498
Test name
Test status
Simulation time 71651074800 ps
CPU time 341.62 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 06:58:55 PM PDT 24
Peak memory 201820 kb
Host smart-fd9558f4-dcb8-4c79-80d7-83d49bdd01e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199658147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2199658147
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2809420324
Short name T769
Test name
Test status
Simulation time 33940130968 ps
CPU time 78.2 seconds
Started Aug 01 06:53:15 PM PDT 24
Finished Aug 01 06:54:33 PM PDT 24
Peak memory 201544 kb
Host smart-9c4cd587-733a-4bbf-814a-d3e6ce357f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809420324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2809420324
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.436705483
Short name T637
Test name
Test status
Simulation time 3124347775 ps
CPU time 7.43 seconds
Started Aug 01 06:53:16 PM PDT 24
Finished Aug 01 06:53:23 PM PDT 24
Peak memory 201264 kb
Host smart-29f663bd-89ad-459e-a5c9-474e1046bc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436705483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.436705483
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1778987871
Short name T175
Test name
Test status
Simulation time 5863460472 ps
CPU time 7.1 seconds
Started Aug 01 06:53:15 PM PDT 24
Finished Aug 01 06:53:23 PM PDT 24
Peak memory 201364 kb
Host smart-256069b3-4999-4355-8bd2-1a226a6303e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778987871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1778987871
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.172749892
Short name T747
Test name
Test status
Simulation time 150112782344 ps
CPU time 584.72 seconds
Started Aug 01 06:53:14 PM PDT 24
Finished Aug 01 07:02:59 PM PDT 24
Peak memory 209972 kb
Host smart-52f1c450-32a9-4e2c-90b1-c74acfc1964f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172749892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
172749892
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.4004686330
Short name T451
Test name
Test status
Simulation time 470565364 ps
CPU time 1.54 seconds
Started Aug 01 06:53:23 PM PDT 24
Finished Aug 01 06:53:25 PM PDT 24
Peak memory 201228 kb
Host smart-4e6f65e3-ebae-4c1d-bd60-f94249310209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004686330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4004686330
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1546099532
Short name T325
Test name
Test status
Simulation time 357919523777 ps
CPU time 131.55 seconds
Started Aug 01 06:53:27 PM PDT 24
Finished Aug 01 06:55:38 PM PDT 24
Peak memory 201364 kb
Host smart-542745fb-33a2-4bc1-a184-839e53006f5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546099532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1546099532
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2763220315
Short name T224
Test name
Test status
Simulation time 524619534706 ps
CPU time 325.52 seconds
Started Aug 01 06:53:25 PM PDT 24
Finished Aug 01 06:58:50 PM PDT 24
Peak memory 201420 kb
Host smart-a5b3fdd2-e986-46b7-8b6f-3d322de42b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763220315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2763220315
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2219101228
Short name T304
Test name
Test status
Simulation time 491765177482 ps
CPU time 511.52 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 201476 kb
Host smart-028955d9-f750-456c-9876-fca3dfc9d6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219101228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2219101228
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2563850985
Short name T581
Test name
Test status
Simulation time 332320082048 ps
CPU time 518.29 seconds
Started Aug 01 06:53:25 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 201484 kb
Host smart-a09694d7-cd7a-4042-a827-15b915c296ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563850985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2563850985
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1612358681
Short name T262
Test name
Test status
Simulation time 162840177994 ps
CPU time 179.73 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 06:56:23 PM PDT 24
Peak memory 201408 kb
Host smart-8fed18a9-36bc-469f-9dce-efc6237d7e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612358681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1612358681
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1339078661
Short name T627
Test name
Test status
Simulation time 163608537338 ps
CPU time 47.18 seconds
Started Aug 01 06:53:26 PM PDT 24
Finished Aug 01 06:54:13 PM PDT 24
Peak memory 201456 kb
Host smart-4682116a-cd5e-4218-914b-b3b868eb6ddf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339078661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1339078661
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3396484859
Short name T259
Test name
Test status
Simulation time 342392878630 ps
CPU time 788.94 seconds
Started Aug 01 06:53:25 PM PDT 24
Finished Aug 01 07:06:34 PM PDT 24
Peak memory 201468 kb
Host smart-a4fd0d3e-2bba-46b9-a631-6cc4dfd69505
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396484859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3396484859
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1499476863
Short name T524
Test name
Test status
Simulation time 586943123658 ps
CPU time 1230.26 seconds
Started Aug 01 06:53:26 PM PDT 24
Finished Aug 01 07:13:56 PM PDT 24
Peak memory 201456 kb
Host smart-dac4e447-8cb6-4815-8a0c-a07e08007d22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499476863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1499476863
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2324961349
Short name T625
Test name
Test status
Simulation time 96659415232 ps
CPU time 522.31 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 07:02:07 PM PDT 24
Peak memory 201892 kb
Host smart-4e462d9c-45ce-42d9-8f5d-6e2dab38e2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324961349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2324961349
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2074674865
Short name T350
Test name
Test status
Simulation time 33891601342 ps
CPU time 19.18 seconds
Started Aug 01 06:53:26 PM PDT 24
Finished Aug 01 06:53:45 PM PDT 24
Peak memory 201264 kb
Host smart-a658a53c-295b-43bc-a312-f96a5ee2949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074674865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2074674865
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3930676120
Short name T649
Test name
Test status
Simulation time 3845601200 ps
CPU time 3.18 seconds
Started Aug 01 06:53:23 PM PDT 24
Finished Aug 01 06:53:26 PM PDT 24
Peak memory 201308 kb
Host smart-634f11f6-35b0-418b-8d7f-528ad5c6737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930676120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3930676120
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3940001195
Short name T664
Test name
Test status
Simulation time 5649040336 ps
CPU time 13.42 seconds
Started Aug 01 06:53:26 PM PDT 24
Finished Aug 01 06:53:39 PM PDT 24
Peak memory 201324 kb
Host smart-effdac60-d7c3-4820-98ba-196cf3a643c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940001195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3940001195
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.4075430195
Short name T789
Test name
Test status
Simulation time 521967286 ps
CPU time 1.27 seconds
Started Aug 01 06:53:33 PM PDT 24
Finished Aug 01 06:53:35 PM PDT 24
Peak memory 201212 kb
Host smart-dad1780c-f5c9-4db2-9854-7da3ce384a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075430195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.4075430195
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1610473712
Short name T242
Test name
Test status
Simulation time 330621226875 ps
CPU time 661.22 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 07:04:25 PM PDT 24
Peak memory 201436 kb
Host smart-1f23ff64-485f-4ab1-939e-e33d29f282d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610473712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1610473712
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3185251478
Short name T516
Test name
Test status
Simulation time 158140210698 ps
CPU time 99.43 seconds
Started Aug 01 06:53:25 PM PDT 24
Finished Aug 01 06:55:04 PM PDT 24
Peak memory 201412 kb
Host smart-b21cb0cf-4994-482e-9a76-31ecb6a27a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185251478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3185251478
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.558054246
Short name T658
Test name
Test status
Simulation time 496406827979 ps
CPU time 228.63 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 06:57:13 PM PDT 24
Peak memory 201428 kb
Host smart-1148a9a8-46f6-4448-84cf-e5d8c96dd976
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=558054246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.558054246
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3460367447
Short name T281
Test name
Test status
Simulation time 484372252233 ps
CPU time 1200.89 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 07:13:25 PM PDT 24
Peak memory 201444 kb
Host smart-09b40ed6-27df-435c-be11-24ab1821e353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460367447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3460367447
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.240206875
Short name T567
Test name
Test status
Simulation time 161518255227 ps
CPU time 90.24 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 06:54:54 PM PDT 24
Peak memory 201420 kb
Host smart-c2f6c660-ecbe-496f-87ed-a6a0305d4fde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=240206875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.240206875
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3068639593
Short name T555
Test name
Test status
Simulation time 198210612050 ps
CPU time 437.96 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 07:00:42 PM PDT 24
Peak memory 201436 kb
Host smart-6bfea9d9-3564-48bd-9999-9c5119566891
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068639593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3068639593
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1030463960
Short name T66
Test name
Test status
Simulation time 116139235377 ps
CPU time 589.5 seconds
Started Aug 01 06:53:33 PM PDT 24
Finished Aug 01 07:03:23 PM PDT 24
Peak memory 201840 kb
Host smart-d8d6c00d-2ab0-44ed-96a9-7583cd13b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030463960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1030463960
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.942398403
Short name T53
Test name
Test status
Simulation time 22460054751 ps
CPU time 27.62 seconds
Started Aug 01 06:53:34 PM PDT 24
Finished Aug 01 06:54:02 PM PDT 24
Peak memory 201368 kb
Host smart-6dbc58d5-96b5-4f16-8896-394ce34c640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942398403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.942398403
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2634466325
Short name T573
Test name
Test status
Simulation time 3309479908 ps
CPU time 7.49 seconds
Started Aug 01 06:53:32 PM PDT 24
Finished Aug 01 06:53:40 PM PDT 24
Peak memory 201364 kb
Host smart-ed8523b1-6f24-402b-b2c4-9232e107e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634466325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2634466325
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2059960415
Short name T431
Test name
Test status
Simulation time 5893497023 ps
CPU time 7.19 seconds
Started Aug 01 06:53:24 PM PDT 24
Finished Aug 01 06:53:31 PM PDT 24
Peak memory 201344 kb
Host smart-e7f8b0ca-5c64-4d5a-97bb-cc699972c856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059960415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2059960415
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2024743105
Short name T45
Test name
Test status
Simulation time 210062875664 ps
CPU time 116.97 seconds
Started Aug 01 06:53:35 PM PDT 24
Finished Aug 01 06:55:32 PM PDT 24
Peak memory 201424 kb
Host smart-fa593855-59ca-4446-ac1c-04e4849cb38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024743105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2024743105
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2581264642
Short name T443
Test name
Test status
Simulation time 402230978 ps
CPU time 1.09 seconds
Started Aug 01 06:53:48 PM PDT 24
Finished Aug 01 06:53:49 PM PDT 24
Peak memory 201252 kb
Host smart-c17e180a-3bc7-42d7-89af-e5bd6021c193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581264642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2581264642
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.256164621
Short name T188
Test name
Test status
Simulation time 329300950059 ps
CPU time 198.96 seconds
Started Aug 01 06:53:34 PM PDT 24
Finished Aug 01 06:56:53 PM PDT 24
Peak memory 201492 kb
Host smart-0c056a72-123a-4d48-8b07-a83c2b6bf2dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256164621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.256164621
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1036143215
Short name T307
Test name
Test status
Simulation time 176433145326 ps
CPU time 207.36 seconds
Started Aug 01 06:53:32 PM PDT 24
Finished Aug 01 06:57:00 PM PDT 24
Peak memory 201456 kb
Host smart-264bb3be-215d-4406-804f-abe7953c9596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036143215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1036143215
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3016678751
Short name T670
Test name
Test status
Simulation time 165614868391 ps
CPU time 195.16 seconds
Started Aug 01 06:53:32 PM PDT 24
Finished Aug 01 06:56:47 PM PDT 24
Peak memory 201456 kb
Host smart-f38d08ad-b03c-4272-9190-d8cc7c57bef4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016678751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3016678751
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.242629003
Short name T319
Test name
Test status
Simulation time 323574571224 ps
CPU time 397.04 seconds
Started Aug 01 06:53:35 PM PDT 24
Finished Aug 01 07:00:12 PM PDT 24
Peak memory 201432 kb
Host smart-fd258480-d5ec-4203-9f3b-c91556c50078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242629003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.242629003
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1768505726
Short name T672
Test name
Test status
Simulation time 485601964667 ps
CPU time 293.4 seconds
Started Aug 01 06:53:33 PM PDT 24
Finished Aug 01 06:58:26 PM PDT 24
Peak memory 201464 kb
Host smart-d9a3f930-0e6a-4678-b20d-95c9282680c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768505726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1768505726
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3604848477
Short name T197
Test name
Test status
Simulation time 329749291100 ps
CPU time 128.69 seconds
Started Aug 01 06:53:32 PM PDT 24
Finished Aug 01 06:55:41 PM PDT 24
Peak memory 201484 kb
Host smart-13a5d5f8-aea5-4b26-a4a1-05600367effc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604848477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3604848477
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3541691993
Short name T774
Test name
Test status
Simulation time 206505411740 ps
CPU time 498.72 seconds
Started Aug 01 06:53:33 PM PDT 24
Finished Aug 01 07:01:51 PM PDT 24
Peak memory 201416 kb
Host smart-858b3b22-fb2e-4cfb-9177-51804abda3de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541691993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3541691993
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2095976725
Short name T67
Test name
Test status
Simulation time 83963745606 ps
CPU time 320.56 seconds
Started Aug 01 06:53:46 PM PDT 24
Finished Aug 01 06:59:07 PM PDT 24
Peak memory 201892 kb
Host smart-00f8526b-b129-4af3-a0d8-c45b87edc300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095976725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2095976725
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.156723086
Short name T650
Test name
Test status
Simulation time 25845189728 ps
CPU time 30.07 seconds
Started Aug 01 06:53:47 PM PDT 24
Finished Aug 01 06:54:17 PM PDT 24
Peak memory 201336 kb
Host smart-592c4fd1-ed28-4840-88f1-4b56b22c5952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156723086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.156723086
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3765262327
Short name T526
Test name
Test status
Simulation time 5159843439 ps
CPU time 12.47 seconds
Started Aug 01 06:53:47 PM PDT 24
Finished Aug 01 06:54:00 PM PDT 24
Peak memory 201332 kb
Host smart-06de3df2-8620-4261-bb7b-6f71b26a0548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765262327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3765262327
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1086915544
Short name T459
Test name
Test status
Simulation time 5870523913 ps
CPU time 15.79 seconds
Started Aug 01 06:53:32 PM PDT 24
Finished Aug 01 06:53:48 PM PDT 24
Peak memory 201376 kb
Host smart-6468ba7a-c802-4653-9e40-43e395b06ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086915544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1086915544
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.320697416
Short name T238
Test name
Test status
Simulation time 236510571460 ps
CPU time 86.28 seconds
Started Aug 01 06:53:47 PM PDT 24
Finished Aug 01 06:55:13 PM PDT 24
Peak memory 210136 kb
Host smart-5f37dfa4-8a89-4eec-8ab0-430eb58e93e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320697416 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.320697416
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3497901818
Short name T494
Test name
Test status
Simulation time 424267939 ps
CPU time 1.54 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 06:51:58 PM PDT 24
Peak memory 201220 kb
Host smart-a2407e14-04b6-45ab-b615-b6528872e50f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497901818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3497901818
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3491133799
Short name T544
Test name
Test status
Simulation time 158776743351 ps
CPU time 172.76 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:54:58 PM PDT 24
Peak memory 201440 kb
Host smart-e15375f1-e367-4ad2-aa86-5d9bca33eb68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491133799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3491133799
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.383693008
Short name T551
Test name
Test status
Simulation time 165426531705 ps
CPU time 376.33 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:58:22 PM PDT 24
Peak memory 201448 kb
Host smart-fed8bd12-398d-47dc-a626-1773e4aad6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383693008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.383693008
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.690667019
Short name T543
Test name
Test status
Simulation time 322816729275 ps
CPU time 706.15 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 07:03:45 PM PDT 24
Peak memory 201452 kb
Host smart-9131ace7-99e8-431b-b673-bf4aab222de8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=690667019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.690667019
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1632007855
Short name T264
Test name
Test status
Simulation time 165973807493 ps
CPU time 287.63 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:56:46 PM PDT 24
Peak memory 201440 kb
Host smart-3a826d86-d7ce-4e8c-868a-b12910528416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632007855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1632007855
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2873124492
Short name T548
Test name
Test status
Simulation time 165078892427 ps
CPU time 387.84 seconds
Started Aug 01 06:51:55 PM PDT 24
Finished Aug 01 06:58:23 PM PDT 24
Peak memory 201416 kb
Host smart-9969c4da-e12b-47a1-a600-ce02ee64b289
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873124492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2873124492
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3009485664
Short name T371
Test name
Test status
Simulation time 609455979463 ps
CPU time 363.22 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:58:05 PM PDT 24
Peak memory 201424 kb
Host smart-6a548bbb-94b7-4bba-8878-88646fb1ff8d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009485664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3009485664
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2166289637
Short name T119
Test name
Test status
Simulation time 126986019900 ps
CPU time 443.97 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 06:59:31 PM PDT 24
Peak memory 201908 kb
Host smart-c44133b4-7d7f-4cf6-9961-7457cf7ee91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166289637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2166289637
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3779305995
Short name T479
Test name
Test status
Simulation time 29623175723 ps
CPU time 69.23 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:53:11 PM PDT 24
Peak memory 201352 kb
Host smart-680ea7b2-d40b-48d1-ad27-1ff93c1583bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779305995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3779305995
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3719333385
Short name T54
Test name
Test status
Simulation time 4606705715 ps
CPU time 10.62 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 06:52:09 PM PDT 24
Peak memory 201352 kb
Host smart-65a617c3-2488-4eb8-973d-4acdf7cdbe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719333385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3719333385
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1731102168
Short name T96
Test name
Test status
Simulation time 7975001947 ps
CPU time 16.57 seconds
Started Aug 01 06:51:52 PM PDT 24
Finished Aug 01 06:52:09 PM PDT 24
Peak memory 217904 kb
Host smart-85e96b5d-81bf-481d-a2b3-9eb7f09ab83f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731102168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1731102168
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.395689047
Short name T601
Test name
Test status
Simulation time 6069238129 ps
CPU time 13.26 seconds
Started Aug 01 06:52:04 PM PDT 24
Finished Aug 01 06:52:18 PM PDT 24
Peak memory 201216 kb
Host smart-4b134151-75b3-4e25-9d73-2a110b1445eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395689047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.395689047
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3562315139
Short name T720
Test name
Test status
Simulation time 512290331844 ps
CPU time 672.01 seconds
Started Aug 01 06:51:52 PM PDT 24
Finished Aug 01 07:03:04 PM PDT 24
Peak memory 212296 kb
Host smart-c04a2427-61d0-460e-b9b0-6aa3e67af9a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562315139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3562315139
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.640913946
Short name T22
Test name
Test status
Simulation time 54616553600 ps
CPU time 91.76 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:53:31 PM PDT 24
Peak memory 210084 kb
Host smart-bde33cb8-ffb5-49bb-ac49-fd634579df2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640913946 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.640913946
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2970930385
Short name T682
Test name
Test status
Simulation time 509150361 ps
CPU time 1.14 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 06:54:00 PM PDT 24
Peak memory 201244 kb
Host smart-f2093c76-9a14-4efe-a639-09ed38bb7b1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970930385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2970930385
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2475412324
Short name T401
Test name
Test status
Simulation time 165939990573 ps
CPU time 398.23 seconds
Started Aug 01 06:53:48 PM PDT 24
Finished Aug 01 07:00:27 PM PDT 24
Peak memory 201424 kb
Host smart-3d99f4b4-101a-45b2-b0ee-c0adb3d73913
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475412324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2475412324
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.324658996
Short name T161
Test name
Test status
Simulation time 167369096968 ps
CPU time 101.77 seconds
Started Aug 01 06:53:47 PM PDT 24
Finished Aug 01 06:55:29 PM PDT 24
Peak memory 201424 kb
Host smart-402ef9ae-7fbc-4067-ac84-c4e9d0fb77f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324658996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.324658996
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.233471977
Short name T546
Test name
Test status
Simulation time 493696681894 ps
CPU time 277.73 seconds
Started Aug 01 06:53:48 PM PDT 24
Finished Aug 01 06:58:26 PM PDT 24
Peak memory 201444 kb
Host smart-0bb98813-f521-4fdb-844f-369e76bbe825
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=233471977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.233471977
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1674996990
Short name T623
Test name
Test status
Simulation time 192049345214 ps
CPU time 75.91 seconds
Started Aug 01 06:53:47 PM PDT 24
Finished Aug 01 06:55:03 PM PDT 24
Peak memory 201468 kb
Host smart-d637934a-9633-4993-ba84-578dafb1e063
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674996990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1674996990
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2330825381
Short name T8
Test name
Test status
Simulation time 87438410343 ps
CPU time 299.32 seconds
Started Aug 01 06:53:59 PM PDT 24
Finished Aug 01 06:58:59 PM PDT 24
Peak memory 201840 kb
Host smart-8248ffa2-b1ce-4124-b533-206a0577d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330825381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2330825381
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2563950905
Short name T512
Test name
Test status
Simulation time 24096947489 ps
CPU time 15.12 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 06:54:13 PM PDT 24
Peak memory 201380 kb
Host smart-953b9655-089a-40b9-882b-c5521a060c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563950905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2563950905
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1649883918
Short name T349
Test name
Test status
Simulation time 5098720333 ps
CPU time 11.86 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 06:54:10 PM PDT 24
Peak memory 201360 kb
Host smart-0c9a3fa3-cbec-4a31-a681-ce8c136b77c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649883918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1649883918
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3006910204
Short name T511
Test name
Test status
Simulation time 5663100488 ps
CPU time 11.36 seconds
Started Aug 01 06:53:48 PM PDT 24
Finished Aug 01 06:53:59 PM PDT 24
Peak memory 201364 kb
Host smart-9ae10a08-e6e3-40d6-b06e-8b65545d2f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006910204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3006910204
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2501281845
Short name T678
Test name
Test status
Simulation time 175641449563 ps
CPU time 368.25 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 07:00:06 PM PDT 24
Peak memory 201444 kb
Host smart-74725363-4160-4fa7-8286-ceaa193f9ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501281845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2501281845
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1302205732
Short name T35
Test name
Test status
Simulation time 80318018533 ps
CPU time 143.71 seconds
Started Aug 01 06:53:59 PM PDT 24
Finished Aug 01 06:56:23 PM PDT 24
Peak memory 210148 kb
Host smart-c672f823-97f8-4840-b694-281e8b682114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302205732 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1302205732
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2359768790
Short name T477
Test name
Test status
Simulation time 391574192 ps
CPU time 1.05 seconds
Started Aug 01 06:53:57 PM PDT 24
Finished Aug 01 06:53:59 PM PDT 24
Peak memory 201220 kb
Host smart-fbc66123-9c73-431e-8804-afe1db63deb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359768790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2359768790
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.446075188
Short name T195
Test name
Test status
Simulation time 492380943822 ps
CPU time 166.82 seconds
Started Aug 01 06:54:02 PM PDT 24
Finished Aug 01 06:56:49 PM PDT 24
Peak memory 201380 kb
Host smart-eea1b69b-64db-472e-8369-9af8b741ac73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446075188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.446075188
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2520262055
Short name T621
Test name
Test status
Simulation time 322773677813 ps
CPU time 769.06 seconds
Started Aug 01 06:53:59 PM PDT 24
Finished Aug 01 07:06:49 PM PDT 24
Peak memory 201432 kb
Host smart-fc7fb1af-7820-4d9d-9ce7-94cb2f272307
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520262055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2520262055
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.885669500
Short name T30
Test name
Test status
Simulation time 166730823955 ps
CPU time 355.02 seconds
Started Aug 01 06:54:00 PM PDT 24
Finished Aug 01 06:59:55 PM PDT 24
Peak memory 201428 kb
Host smart-a187dcc1-e6f6-4d96-95a8-6abeb52fa8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885669500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.885669500
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.175375547
Short name T383
Test name
Test status
Simulation time 330832033625 ps
CPU time 368.48 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 07:00:07 PM PDT 24
Peak memory 201512 kb
Host smart-e6305bae-b083-4310-8c2a-0900bcb2bac9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=175375547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.175375547
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.4227455801
Short name T379
Test name
Test status
Simulation time 192415742764 ps
CPU time 99.71 seconds
Started Aug 01 06:53:57 PM PDT 24
Finished Aug 01 06:55:37 PM PDT 24
Peak memory 201464 kb
Host smart-d82f3a86-c83e-4752-b717-44f8c74c7066
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227455801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.4227455801
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2562772603
Short name T662
Test name
Test status
Simulation time 76314762942 ps
CPU time 405.32 seconds
Started Aug 01 06:54:01 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 201776 kb
Host smart-33a6a7e5-e0ca-47fc-bf65-92df01bd62d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562772603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2562772603
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1409579805
Short name T529
Test name
Test status
Simulation time 42653473520 ps
CPU time 90.37 seconds
Started Aug 01 06:53:59 PM PDT 24
Finished Aug 01 06:55:30 PM PDT 24
Peak memory 201364 kb
Host smart-529efc37-b98c-44d5-810f-cdf26277b208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409579805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1409579805
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2475019232
Short name T624
Test name
Test status
Simulation time 3780436742 ps
CPU time 5.13 seconds
Started Aug 01 06:53:59 PM PDT 24
Finished Aug 01 06:54:04 PM PDT 24
Peak memory 201548 kb
Host smart-f28f7de7-3e2b-4f82-99b5-602b2741d989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475019232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2475019232
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2218960722
Short name T565
Test name
Test status
Simulation time 6110824816 ps
CPU time 7.93 seconds
Started Aug 01 06:53:57 PM PDT 24
Finished Aug 01 06:54:06 PM PDT 24
Peak memory 201368 kb
Host smart-fb90a24c-623e-46eb-b5fb-921b8fe80bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218960722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2218960722
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1306589056
Short name T46
Test name
Test status
Simulation time 330616386810 ps
CPU time 188.93 seconds
Started Aug 01 06:53:59 PM PDT 24
Finished Aug 01 06:57:08 PM PDT 24
Peak memory 201512 kb
Host smart-4b0507d8-0649-4826-9931-fb24b918a41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306589056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1306589056
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.155923381
Short name T338
Test name
Test status
Simulation time 332492540136 ps
CPU time 260.1 seconds
Started Aug 01 06:54:00 PM PDT 24
Finished Aug 01 06:58:20 PM PDT 24
Peak memory 210176 kb
Host smart-2c432261-531b-49c3-b54d-dbd9f688d184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155923381 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.155923381
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3594965173
Short name T540
Test name
Test status
Simulation time 341032323 ps
CPU time 0.81 seconds
Started Aug 01 06:54:07 PM PDT 24
Finished Aug 01 06:54:08 PM PDT 24
Peak memory 201212 kb
Host smart-77ecf1b0-95a8-439b-8c1a-062e99e45e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594965173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3594965173
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4220034970
Short name T537
Test name
Test status
Simulation time 163336884661 ps
CPU time 385.43 seconds
Started Aug 01 06:53:59 PM PDT 24
Finished Aug 01 07:00:24 PM PDT 24
Peak memory 201476 kb
Host smart-d6cb3396-c9ae-48e0-ba4c-2167c11dff64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220034970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4220034970
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.4266972030
Short name T162
Test name
Test status
Simulation time 354984728416 ps
CPU time 379.5 seconds
Started Aug 01 06:54:00 PM PDT 24
Finished Aug 01 07:00:19 PM PDT 24
Peak memory 201528 kb
Host smart-e17664ad-3a4b-41f8-876b-36cff73de907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266972030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.4266972030
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1366104131
Short name T577
Test name
Test status
Simulation time 481432920037 ps
CPU time 1053.7 seconds
Started Aug 01 06:54:00 PM PDT 24
Finished Aug 01 07:11:34 PM PDT 24
Peak memory 201524 kb
Host smart-ef7e67fe-0fbe-4fca-bbba-8ea2e75863e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366104131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1366104131
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3374615187
Short name T486
Test name
Test status
Simulation time 491707361172 ps
CPU time 287.31 seconds
Started Aug 01 06:54:01 PM PDT 24
Finished Aug 01 06:58:49 PM PDT 24
Peak memory 201372 kb
Host smart-18894184-6b37-42a2-889f-ab48fa545716
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374615187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3374615187
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1065032330
Short name T576
Test name
Test status
Simulation time 484851602788 ps
CPU time 1160.66 seconds
Started Aug 01 06:54:00 PM PDT 24
Finished Aug 01 07:13:21 PM PDT 24
Peak memory 201436 kb
Host smart-1852c070-dfb0-4aac-88f4-8433499efe29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065032330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1065032330
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.818801884
Short name T722
Test name
Test status
Simulation time 164793309348 ps
CPU time 97.7 seconds
Started Aug 01 06:53:57 PM PDT 24
Finished Aug 01 06:55:34 PM PDT 24
Peak memory 201444 kb
Host smart-6b285ddd-6273-4c70-bafa-b60b92449de6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=818801884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.818801884
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.800106646
Short name T761
Test name
Test status
Simulation time 567247087953 ps
CPU time 352.12 seconds
Started Aug 01 06:54:00 PM PDT 24
Finished Aug 01 06:59:52 PM PDT 24
Peak memory 201428 kb
Host smart-58cfe681-11ec-43a4-a8da-1030d26fbcdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800106646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.800106646
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1079865877
Short name T390
Test name
Test status
Simulation time 591011401917 ps
CPU time 328.76 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 06:59:27 PM PDT 24
Peak memory 201432 kb
Host smart-2f7eea6c-35a0-45fe-a4ea-c3ad221161ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079865877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1079865877
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1433170784
Short name T384
Test name
Test status
Simulation time 103339694811 ps
CPU time 523.23 seconds
Started Aug 01 06:54:08 PM PDT 24
Finished Aug 01 07:02:52 PM PDT 24
Peak memory 201852 kb
Host smart-6d992667-7762-45e4-abb8-817eef6c7ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433170784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1433170784
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.439364070
Short name T542
Test name
Test status
Simulation time 45127436977 ps
CPU time 99.21 seconds
Started Aug 01 06:53:58 PM PDT 24
Finished Aug 01 06:55:37 PM PDT 24
Peak memory 201348 kb
Host smart-f0efdeff-121a-4213-9bcd-5dd265329d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439364070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.439364070
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.493758029
Short name T762
Test name
Test status
Simulation time 5301791030 ps
CPU time 6.83 seconds
Started Aug 01 06:54:00 PM PDT 24
Finished Aug 01 06:54:07 PM PDT 24
Peak memory 201348 kb
Host smart-5af2d569-f2cd-461e-b9be-183e6b4b3e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493758029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.493758029
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.809745880
Short name T501
Test name
Test status
Simulation time 5802461451 ps
CPU time 15.08 seconds
Started Aug 01 06:54:16 PM PDT 24
Finished Aug 01 06:54:31 PM PDT 24
Peak memory 201380 kb
Host smart-6ae25483-8b06-41ac-8d17-652a415768e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809745880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.809745880
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2678139172
Short name T339
Test name
Test status
Simulation time 477014708732 ps
CPU time 1359.04 seconds
Started Aug 01 06:54:07 PM PDT 24
Finished Aug 01 07:16:46 PM PDT 24
Peak memory 201744 kb
Host smart-cfbef374-000d-4d1c-9353-cc4e566af29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678139172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2678139172
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3492990794
Short name T50
Test name
Test status
Simulation time 194134750176 ps
CPU time 223.08 seconds
Started Aug 01 06:54:05 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 209756 kb
Host smart-28712538-0097-41e6-8b05-45f96aa91414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492990794 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3492990794
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1507364094
Short name T753
Test name
Test status
Simulation time 530836932 ps
CPU time 1.37 seconds
Started Aug 01 06:54:17 PM PDT 24
Finished Aug 01 06:54:18 PM PDT 24
Peak memory 201204 kb
Host smart-ba55f22b-157b-4e12-8a9c-83c809365964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507364094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1507364094
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3251519649
Short name T741
Test name
Test status
Simulation time 339006235962 ps
CPU time 81.49 seconds
Started Aug 01 06:54:17 PM PDT 24
Finished Aug 01 06:55:39 PM PDT 24
Peak memory 201424 kb
Host smart-a714642e-0f28-477a-b78d-c2ba427916d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251519649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3251519649
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.153679837
Short name T256
Test name
Test status
Simulation time 529656020404 ps
CPU time 621.65 seconds
Started Aug 01 06:54:19 PM PDT 24
Finished Aug 01 07:04:40 PM PDT 24
Peak memory 201432 kb
Host smart-5d60a863-d36a-4eb3-ba38-f2b2b3e20d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153679837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.153679837
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.394460291
Short name T786
Test name
Test status
Simulation time 171197639384 ps
CPU time 288.89 seconds
Started Aug 01 06:54:11 PM PDT 24
Finished Aug 01 06:59:00 PM PDT 24
Peak memory 201452 kb
Host smart-ed796cdb-b475-455b-9eed-53e9514cae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394460291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.394460291
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2716999865
Short name T418
Test name
Test status
Simulation time 494165958112 ps
CPU time 1084.77 seconds
Started Aug 01 06:54:08 PM PDT 24
Finished Aug 01 07:12:13 PM PDT 24
Peak memory 201504 kb
Host smart-e13a140a-e97b-4a0e-bbab-bb6699776cf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716999865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2716999865
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1601849747
Short name T236
Test name
Test status
Simulation time 164186400466 ps
CPU time 83.53 seconds
Started Aug 01 06:54:07 PM PDT 24
Finished Aug 01 06:55:31 PM PDT 24
Peak memory 201488 kb
Host smart-ae1adbb2-b5c6-4b87-8f39-765d5abfcc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601849747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1601849747
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3089907053
Short name T352
Test name
Test status
Simulation time 325831277424 ps
CPU time 145.88 seconds
Started Aug 01 06:54:06 PM PDT 24
Finished Aug 01 06:56:32 PM PDT 24
Peak memory 201436 kb
Host smart-701fb5f1-c9a1-430d-912e-7f3c0d2b94ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089907053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3089907053
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2899361330
Short name T110
Test name
Test status
Simulation time 525346585684 ps
CPU time 664.65 seconds
Started Aug 01 06:54:08 PM PDT 24
Finished Aug 01 07:05:13 PM PDT 24
Peak memory 201380 kb
Host smart-fa079aab-f4c6-48cf-919e-57c8482106c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899361330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2899361330
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.4007709626
Short name T122
Test name
Test status
Simulation time 199949018432 ps
CPU time 441.33 seconds
Started Aug 01 06:54:17 PM PDT 24
Finished Aug 01 07:01:38 PM PDT 24
Peak memory 201432 kb
Host smart-8e3d7434-cfef-4733-90c7-9a6a6a1ddf6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007709626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.4007709626
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2912565915
Short name T425
Test name
Test status
Simulation time 118211637993 ps
CPU time 448.19 seconds
Started Aug 01 06:54:19 PM PDT 24
Finished Aug 01 07:01:47 PM PDT 24
Peak memory 201824 kb
Host smart-bc62859f-4db8-499b-a71a-e9b0a28e6400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912565915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2912565915
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2784274283
Short name T396
Test name
Test status
Simulation time 48702754579 ps
CPU time 53.67 seconds
Started Aug 01 06:54:17 PM PDT 24
Finished Aug 01 06:55:11 PM PDT 24
Peak memory 201360 kb
Host smart-9518bbab-026c-48c7-b649-3e3c8b26d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784274283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2784274283
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3106975959
Short name T449
Test name
Test status
Simulation time 4943528143 ps
CPU time 3.07 seconds
Started Aug 01 06:54:18 PM PDT 24
Finished Aug 01 06:54:21 PM PDT 24
Peak memory 201420 kb
Host smart-4f5a038d-3988-43d3-9981-0851ef9cc530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106975959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3106975959
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3202188390
Short name T435
Test name
Test status
Simulation time 5833333979 ps
CPU time 14.97 seconds
Started Aug 01 06:54:11 PM PDT 24
Finished Aug 01 06:54:26 PM PDT 24
Peak memory 201368 kb
Host smart-974ba611-9387-461b-8a19-a05562b2c236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202188390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3202188390
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.802370105
Short name T246
Test name
Test status
Simulation time 167675323776 ps
CPU time 42.49 seconds
Started Aug 01 06:54:20 PM PDT 24
Finished Aug 01 06:55:03 PM PDT 24
Peak memory 201508 kb
Host smart-5b620986-ada8-451e-8ee3-1dca664b722b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802370105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
802370105
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2992792681
Short name T47
Test name
Test status
Simulation time 22295426358 ps
CPU time 45.21 seconds
Started Aug 01 06:54:17 PM PDT 24
Finished Aug 01 06:55:02 PM PDT 24
Peak memory 217988 kb
Host smart-3f8c81d5-4a76-4edc-84b8-a496e4a285c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992792681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2992792681
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3318909202
Short name T444
Test name
Test status
Simulation time 461800962 ps
CPU time 1.37 seconds
Started Aug 01 06:54:29 PM PDT 24
Finished Aug 01 06:54:30 PM PDT 24
Peak memory 201248 kb
Host smart-fec96f5b-292c-492d-bbc8-90b6c6f00eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318909202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3318909202
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3934449098
Short name T152
Test name
Test status
Simulation time 327862054518 ps
CPU time 197.73 seconds
Started Aug 01 06:54:27 PM PDT 24
Finished Aug 01 06:57:45 PM PDT 24
Peak memory 201420 kb
Host smart-52a69784-cc33-4dae-9dfc-edc6fbf0857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934449098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3934449098
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2883810186
Short name T284
Test name
Test status
Simulation time 169095931553 ps
CPU time 191.68 seconds
Started Aug 01 06:54:17 PM PDT 24
Finished Aug 01 06:57:29 PM PDT 24
Peak memory 201444 kb
Host smart-12bdfcd8-adda-4e63-8166-877ee8a8638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883810186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2883810186
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2845922151
Short name T263
Test name
Test status
Simulation time 323294685690 ps
CPU time 187.83 seconds
Started Aug 01 06:54:16 PM PDT 24
Finished Aug 01 06:57:24 PM PDT 24
Peak memory 201464 kb
Host smart-0953342b-0b14-457f-be84-824ff820bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845922151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2845922151
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2090767571
Short name T541
Test name
Test status
Simulation time 493196416961 ps
CPU time 261.75 seconds
Started Aug 01 06:54:16 PM PDT 24
Finished Aug 01 06:58:38 PM PDT 24
Peak memory 201360 kb
Host smart-b5b893ef-49ec-424b-bf9c-58937f4f257f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090767571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2090767571
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2469853124
Short name T681
Test name
Test status
Simulation time 187708181985 ps
CPU time 220.29 seconds
Started Aug 01 06:54:31 PM PDT 24
Finished Aug 01 06:58:11 PM PDT 24
Peak memory 201436 kb
Host smart-85067447-21f2-43e8-b017-73b7a2a170e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469853124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2469853124
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.574460386
Short name T39
Test name
Test status
Simulation time 384750660520 ps
CPU time 449.75 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 07:01:58 PM PDT 24
Peak memory 201460 kb
Host smart-ee99baa1-d5b6-476d-b21c-c04709185b74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574460386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.574460386
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2073627600
Short name T500
Test name
Test status
Simulation time 94802920530 ps
CPU time 367.61 seconds
Started Aug 01 06:54:27 PM PDT 24
Finished Aug 01 07:00:35 PM PDT 24
Peak memory 201896 kb
Host smart-2d9b2a00-bff7-41fc-a696-ba73cb1d0876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073627600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2073627600
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.788158016
Short name T447
Test name
Test status
Simulation time 44981069733 ps
CPU time 27.01 seconds
Started Aug 01 06:54:29 PM PDT 24
Finished Aug 01 06:54:56 PM PDT 24
Peak memory 201380 kb
Host smart-905c4b51-67be-4062-8dc4-305886540758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788158016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.788158016
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1424069435
Short name T785
Test name
Test status
Simulation time 3965232766 ps
CPU time 10.36 seconds
Started Aug 01 06:54:25 PM PDT 24
Finished Aug 01 06:54:36 PM PDT 24
Peak memory 201380 kb
Host smart-6884a9b1-e29e-4815-96cb-59abdd32336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424069435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1424069435
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.498301419
Short name T165
Test name
Test status
Simulation time 5764913963 ps
CPU time 7.32 seconds
Started Aug 01 06:54:16 PM PDT 24
Finished Aug 01 06:54:24 PM PDT 24
Peak memory 201328 kb
Host smart-a946e864-4898-4bc7-934e-21ef4287e881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498301419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.498301419
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.602176703
Short name T311
Test name
Test status
Simulation time 369442050116 ps
CPU time 825.78 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 07:08:14 PM PDT 24
Peak memory 201448 kb
Host smart-bb79ee88-93a8-41da-915e-f3b60ac90d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602176703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
602176703
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.4184101001
Short name T535
Test name
Test status
Simulation time 475973535 ps
CPU time 0.74 seconds
Started Aug 01 06:54:35 PM PDT 24
Finished Aug 01 06:54:36 PM PDT 24
Peak memory 201220 kb
Host smart-9937ffb1-b7c7-4a6f-a1e6-2ee4d0f29f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184101001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.4184101001
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.726163655
Short name T714
Test name
Test status
Simulation time 544254412614 ps
CPU time 1292.62 seconds
Started Aug 01 06:54:26 PM PDT 24
Finished Aug 01 07:15:59 PM PDT 24
Peak memory 201400 kb
Host smart-090a2f06-92c3-48ae-aa83-6ecf76633d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726163655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.726163655
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2976674866
Short name T686
Test name
Test status
Simulation time 481558175514 ps
CPU time 1160.32 seconds
Started Aug 01 06:54:27 PM PDT 24
Finished Aug 01 07:13:47 PM PDT 24
Peak memory 201420 kb
Host smart-d463a4c5-5696-46d5-a486-418bf5e1785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976674866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2976674866
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.4284065133
Short name T457
Test name
Test status
Simulation time 495006525867 ps
CPU time 290.41 seconds
Started Aug 01 06:54:27 PM PDT 24
Finished Aug 01 06:59:17 PM PDT 24
Peak memory 201456 kb
Host smart-4215a392-39ff-428f-b4bf-f04574ed54de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284065133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.4284065133
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2155108108
Short name T186
Test name
Test status
Simulation time 327272287311 ps
CPU time 181.29 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 06:57:30 PM PDT 24
Peak memory 201456 kb
Host smart-3bdc7879-3257-49be-aec8-a7366abc9459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155108108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2155108108
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2401919191
Short name T574
Test name
Test status
Simulation time 494910355330 ps
CPU time 1056.03 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 07:12:04 PM PDT 24
Peak memory 201472 kb
Host smart-f16ca76c-5c89-4b8c-8fe0-94d3f7740f1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401919191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2401919191
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1269246644
Short name T539
Test name
Test status
Simulation time 184889839009 ps
CPU time 114.09 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 06:56:22 PM PDT 24
Peak memory 201524 kb
Host smart-f1a9e9e8-5ab8-4cff-ad25-c3bff9a5df8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269246644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1269246644
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3638760825
Short name T536
Test name
Test status
Simulation time 194723521077 ps
CPU time 56.32 seconds
Started Aug 01 06:54:26 PM PDT 24
Finished Aug 01 06:55:22 PM PDT 24
Peak memory 201440 kb
Host smart-b1059d3d-7a6a-489c-ab55-d70f9bd863ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638760825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3638760825
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2511591440
Short name T55
Test name
Test status
Simulation time 81220175253 ps
CPU time 353.66 seconds
Started Aug 01 06:54:37 PM PDT 24
Finished Aug 01 07:00:31 PM PDT 24
Peak memory 201820 kb
Host smart-a3c380c9-ee8f-4af9-904a-4b0c22e3b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511591440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2511591440
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3438367329
Short name T663
Test name
Test status
Simulation time 40395926345 ps
CPU time 7.81 seconds
Started Aug 01 06:54:29 PM PDT 24
Finished Aug 01 06:54:37 PM PDT 24
Peak memory 201344 kb
Host smart-5d7129cc-b47c-485e-a721-1749f5a0654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438367329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3438367329
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2785848756
Short name T420
Test name
Test status
Simulation time 4834310411 ps
CPU time 6.07 seconds
Started Aug 01 06:54:28 PM PDT 24
Finished Aug 01 06:54:34 PM PDT 24
Peak memory 201332 kb
Host smart-9c0ac031-6af0-443e-8629-816312695464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785848756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2785848756
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2063326102
Short name T408
Test name
Test status
Simulation time 5977804756 ps
CPU time 7.43 seconds
Started Aug 01 06:54:27 PM PDT 24
Finished Aug 01 06:54:34 PM PDT 24
Peak memory 201376 kb
Host smart-82f07357-1a9a-451b-9774-930c7d4dc899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063326102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2063326102
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3930866895
Short name T695
Test name
Test status
Simulation time 28001104008 ps
CPU time 55.17 seconds
Started Aug 01 06:54:36 PM PDT 24
Finished Aug 01 06:55:31 PM PDT 24
Peak memory 209792 kb
Host smart-e6473645-3c70-4263-8807-0cca9bfb43a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930866895 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3930866895
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3940942196
Short name T705
Test name
Test status
Simulation time 540277693 ps
CPU time 1.17 seconds
Started Aug 01 06:54:47 PM PDT 24
Finished Aug 01 06:54:48 PM PDT 24
Peak memory 201212 kb
Host smart-f293592f-bf9c-48ce-bd87-1f428f39c860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940942196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3940942196
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2679208572
Short name T553
Test name
Test status
Simulation time 164531473164 ps
CPU time 10.51 seconds
Started Aug 01 06:54:36 PM PDT 24
Finished Aug 01 06:54:47 PM PDT 24
Peak memory 201388 kb
Host smart-4e0789d9-1d38-4977-a9d2-e7d62c051dc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679208572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2679208572
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1142724911
Short name T219
Test name
Test status
Simulation time 497665176086 ps
CPU time 319.24 seconds
Started Aug 01 06:54:37 PM PDT 24
Finished Aug 01 06:59:56 PM PDT 24
Peak memory 201452 kb
Host smart-cf494bc3-9e9b-47d4-bebb-32728e09adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142724911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1142724911
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.180336744
Short name T316
Test name
Test status
Simulation time 327854864325 ps
CPU time 378.32 seconds
Started Aug 01 06:54:35 PM PDT 24
Finished Aug 01 07:00:54 PM PDT 24
Peak memory 201436 kb
Host smart-6f44cb2d-9276-44c8-ba76-5368e21fd2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180336744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.180336744
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2639084953
Short name T369
Test name
Test status
Simulation time 166803723966 ps
CPU time 100.66 seconds
Started Aug 01 06:54:36 PM PDT 24
Finished Aug 01 06:56:17 PM PDT 24
Peak memory 201460 kb
Host smart-f03793b8-3998-4f27-b2ca-9507cb7ce96f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639084953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2639084953
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2114727633
Short name T559
Test name
Test status
Simulation time 164771044681 ps
CPU time 391.44 seconds
Started Aug 01 06:54:38 PM PDT 24
Finished Aug 01 07:01:09 PM PDT 24
Peak memory 201544 kb
Host smart-2a21275b-c71e-42eb-bf48-1d983ddf1829
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114727633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2114727633
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2665675059
Short name T362
Test name
Test status
Simulation time 403737699737 ps
CPU time 804.8 seconds
Started Aug 01 06:54:35 PM PDT 24
Finished Aug 01 07:08:00 PM PDT 24
Peak memory 201460 kb
Host smart-369acf63-ba7c-4c4c-872b-2b21dbe1f2c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665675059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2665675059
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.529177607
Short name T56
Test name
Test status
Simulation time 63263145334 ps
CPU time 236.05 seconds
Started Aug 01 06:54:45 PM PDT 24
Finished Aug 01 06:58:41 PM PDT 24
Peak memory 201888 kb
Host smart-a011dc2f-443b-4b5c-87dd-acf33481d557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529177607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.529177607
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3299858074
Short name T387
Test name
Test status
Simulation time 35336605864 ps
CPU time 85.23 seconds
Started Aug 01 06:54:46 PM PDT 24
Finished Aug 01 06:56:11 PM PDT 24
Peak memory 201372 kb
Host smart-8248e94e-baee-4e0b-89d7-41cbd36bd1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299858074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3299858074
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2216331019
Short name T566
Test name
Test status
Simulation time 4682329607 ps
CPU time 3.16 seconds
Started Aug 01 06:54:37 PM PDT 24
Finished Aug 01 06:54:40 PM PDT 24
Peak memory 201268 kb
Host smart-f7ee5a85-8f2a-4ab2-8497-b9b322fee996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216331019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2216331019
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3804622075
Short name T377
Test name
Test status
Simulation time 5807760255 ps
CPU time 2.55 seconds
Started Aug 01 06:54:36 PM PDT 24
Finished Aug 01 06:54:39 PM PDT 24
Peak memory 201332 kb
Host smart-456c8c34-b82d-4f01-bcaa-b9a14c7700e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804622075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3804622075
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2812828603
Short name T74
Test name
Test status
Simulation time 218741108700 ps
CPU time 124.98 seconds
Started Aug 01 06:54:48 PM PDT 24
Finished Aug 01 06:56:53 PM PDT 24
Peak memory 201456 kb
Host smart-1f491b9a-8435-4f4b-b3cc-5a2da0fad294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812828603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2812828603
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1107419873
Short name T626
Test name
Test status
Simulation time 90386126666 ps
CPU time 94.5 seconds
Started Aug 01 06:54:46 PM PDT 24
Finished Aug 01 06:56:21 PM PDT 24
Peak memory 209772 kb
Host smart-467d61d4-0d3e-4beb-860b-779e008c9f34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107419873 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1107419873
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1976978956
Short name T466
Test name
Test status
Simulation time 480275025 ps
CPU time 0.68 seconds
Started Aug 01 06:54:45 PM PDT 24
Finished Aug 01 06:54:46 PM PDT 24
Peak memory 201236 kb
Host smart-4e48974f-b08a-4ae0-95ef-d0e288b210c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976978956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1976978956
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2153620371
Short name T518
Test name
Test status
Simulation time 321442911474 ps
CPU time 358.34 seconds
Started Aug 01 06:54:45 PM PDT 24
Finished Aug 01 07:00:43 PM PDT 24
Peak memory 201392 kb
Host smart-116bfe29-4a29-40a6-82e1-083951d804b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153620371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2153620371
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1424149455
Short name T293
Test name
Test status
Simulation time 171190925676 ps
CPU time 201.23 seconds
Started Aug 01 06:54:47 PM PDT 24
Finished Aug 01 06:58:08 PM PDT 24
Peak memory 201416 kb
Host smart-2644c6a8-0a0a-44fb-97c3-8cf47773d99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424149455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1424149455
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2449202797
Short name T148
Test name
Test status
Simulation time 502325654575 ps
CPU time 171.34 seconds
Started Aug 01 06:54:49 PM PDT 24
Finished Aug 01 06:57:41 PM PDT 24
Peak memory 201448 kb
Host smart-9a60d106-6f90-4895-b23f-a5f55e32d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449202797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2449202797
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2033736194
Short name T118
Test name
Test status
Simulation time 321971153765 ps
CPU time 70.22 seconds
Started Aug 01 06:54:46 PM PDT 24
Finished Aug 01 06:55:56 PM PDT 24
Peak memory 201496 kb
Host smart-e41b8480-d7c0-433c-b310-ce85c263abf9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033736194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2033736194
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2224886760
Short name T290
Test name
Test status
Simulation time 156604707277 ps
CPU time 182.26 seconds
Started Aug 01 06:54:47 PM PDT 24
Finished Aug 01 06:57:49 PM PDT 24
Peak memory 201392 kb
Host smart-20347766-fa31-4fa6-896c-80b9a9ea693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224886760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2224886760
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.234866307
Short name T404
Test name
Test status
Simulation time 323193845649 ps
CPU time 120.87 seconds
Started Aug 01 06:54:45 PM PDT 24
Finished Aug 01 06:56:46 PM PDT 24
Peak memory 201456 kb
Host smart-79f70ba4-3090-44a7-8d7b-13a16c138c1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=234866307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.234866307
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.286522049
Short name T771
Test name
Test status
Simulation time 522229428995 ps
CPU time 1137.07 seconds
Started Aug 01 06:54:45 PM PDT 24
Finished Aug 01 07:13:42 PM PDT 24
Peak memory 201432 kb
Host smart-510a9185-9c8f-4d50-97c0-d5ae4c8234bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286522049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.286522049
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.269691057
Short name T599
Test name
Test status
Simulation time 604525857941 ps
CPU time 359.4 seconds
Started Aug 01 06:54:45 PM PDT 24
Finished Aug 01 07:00:44 PM PDT 24
Peak memory 201408 kb
Host smart-cbda0379-f4ec-4950-80d0-f2d30e517977
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269691057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.269691057
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4116744957
Short name T210
Test name
Test status
Simulation time 81304710221 ps
CPU time 371.63 seconds
Started Aug 01 06:54:48 PM PDT 24
Finished Aug 01 07:00:59 PM PDT 24
Peak memory 201896 kb
Host smart-8b023c15-56d6-4542-a1e0-a718cbea05c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116744957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4116744957
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1137906992
Short name T402
Test name
Test status
Simulation time 26030861472 ps
CPU time 61.53 seconds
Started Aug 01 06:54:46 PM PDT 24
Finished Aug 01 06:55:48 PM PDT 24
Peak memory 201356 kb
Host smart-b854cdcb-0c2e-495f-ab4a-9e49607f9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137906992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1137906992
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3122136913
Short name T507
Test name
Test status
Simulation time 3463067763 ps
CPU time 1.65 seconds
Started Aug 01 06:54:49 PM PDT 24
Finished Aug 01 06:54:50 PM PDT 24
Peak memory 201336 kb
Host smart-3f2ed90d-53a0-4c57-b1f4-1bd7cd94aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122136913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3122136913
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1274464157
Short name T661
Test name
Test status
Simulation time 5800600628 ps
CPU time 7.1 seconds
Started Aug 01 06:54:48 PM PDT 24
Finished Aug 01 06:54:56 PM PDT 24
Peak memory 201376 kb
Host smart-c0df2416-a970-4ba6-b868-9367ba7bb0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274464157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1274464157
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3192305735
Short name T653
Test name
Test status
Simulation time 118611905650 ps
CPU time 377.87 seconds
Started Aug 01 06:54:46 PM PDT 24
Finished Aug 01 07:01:04 PM PDT 24
Peak memory 201824 kb
Host smart-cd229e7f-5e5d-4627-b545-ea7d252606eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192305735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3192305735
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.496536310
Short name T48
Test name
Test status
Simulation time 113447149209 ps
CPU time 124.04 seconds
Started Aug 01 06:54:47 PM PDT 24
Finished Aug 01 06:56:51 PM PDT 24
Peak memory 217304 kb
Host smart-4ad8d40e-03d5-473c-b83c-36778a42240b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496536310 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.496536310
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1445380547
Short name T768
Test name
Test status
Simulation time 362409191 ps
CPU time 1.37 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 06:54:58 PM PDT 24
Peak memory 201216 kb
Host smart-1da39ad3-ffbd-4ed7-ad45-37148aaaf23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445380547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1445380547
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2238399753
Short name T376
Test name
Test status
Simulation time 166334161820 ps
CPU time 99.12 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 06:56:35 PM PDT 24
Peak memory 201396 kb
Host smart-0fed6c99-adac-43ac-a5d7-b9c30727c860
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238399753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2238399753
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.179944805
Short name T154
Test name
Test status
Simulation time 328466576082 ps
CPU time 188.04 seconds
Started Aug 01 06:54:45 PM PDT 24
Finished Aug 01 06:57:54 PM PDT 24
Peak memory 201420 kb
Host smart-08803b5e-fac0-4f6b-9834-972a8fc7d74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179944805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.179944805
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3945000516
Short name T164
Test name
Test status
Simulation time 326057348656 ps
CPU time 767.03 seconds
Started Aug 01 06:54:46 PM PDT 24
Finished Aug 01 07:07:33 PM PDT 24
Peak memory 201436 kb
Host smart-ffd88f89-0aba-4ad5-a0d1-ff3b9338a195
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945000516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3945000516
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3027523067
Short name T337
Test name
Test status
Simulation time 361694538633 ps
CPU time 320.4 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 07:00:16 PM PDT 24
Peak memory 201464 kb
Host smart-544628e4-3ce9-49c8-94b2-433711c18389
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027523067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3027523067
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2023471738
Short name T772
Test name
Test status
Simulation time 398313287010 ps
CPU time 239.96 seconds
Started Aug 01 06:54:58 PM PDT 24
Finished Aug 01 06:58:58 PM PDT 24
Peak memory 201448 kb
Host smart-328603a8-e7fb-49a0-bae7-b4d4b37d67a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023471738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2023471738
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.808705651
Short name T452
Test name
Test status
Simulation time 72773515557 ps
CPU time 211.72 seconds
Started Aug 01 06:54:57 PM PDT 24
Finished Aug 01 06:58:29 PM PDT 24
Peak memory 201892 kb
Host smart-31307428-a998-4de4-938d-964bc04a173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808705651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.808705651
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2743554405
Short name T423
Test name
Test status
Simulation time 31381723118 ps
CPU time 26.94 seconds
Started Aug 01 06:54:57 PM PDT 24
Finished Aug 01 06:55:24 PM PDT 24
Peak memory 201380 kb
Host smart-7abc7c7c-cf90-4159-8ecc-a3db72a6b07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743554405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2743554405
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3582901394
Short name T193
Test name
Test status
Simulation time 3506051559 ps
CPU time 2.85 seconds
Started Aug 01 06:54:57 PM PDT 24
Finished Aug 01 06:55:00 PM PDT 24
Peak memory 201364 kb
Host smart-5d187977-3dcf-49d6-b1cd-a3fd4d79ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582901394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3582901394
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2761623622
Short name T102
Test name
Test status
Simulation time 5968087789 ps
CPU time 12.91 seconds
Started Aug 01 06:54:49 PM PDT 24
Finished Aug 01 06:55:02 PM PDT 24
Peak memory 201360 kb
Host smart-9f2f4b3c-b436-4ae1-9169-28ee60e54f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761623622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2761623622
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1865123492
Short name T693
Test name
Test status
Simulation time 205940134034 ps
CPU time 428.92 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 07:02:05 PM PDT 24
Peak memory 201436 kb
Host smart-43806cee-2c20-41b1-b116-b978e9fe2b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865123492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1865123492
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3102641580
Short name T240
Test name
Test status
Simulation time 94626825646 ps
CPU time 17.02 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 06:55:13 PM PDT 24
Peak memory 209760 kb
Host smart-0baf24c4-bb56-47dd-9ce0-27a5b652f378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102641580 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3102641580
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.121837066
Short name T454
Test name
Test status
Simulation time 436703270 ps
CPU time 1.58 seconds
Started Aug 01 06:55:10 PM PDT 24
Finished Aug 01 06:55:11 PM PDT 24
Peak memory 201220 kb
Host smart-943ab335-0264-4ee8-8f09-a3819febdb4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121837066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.121837066
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2686363149
Short name T765
Test name
Test status
Simulation time 581303129860 ps
CPU time 1097.33 seconds
Started Aug 01 06:55:12 PM PDT 24
Finished Aug 01 07:13:29 PM PDT 24
Peak memory 201500 kb
Host smart-3bdba478-b279-4e9a-b97a-c81fa0c4ed65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686363149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2686363149
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2175158825
Short name T296
Test name
Test status
Simulation time 327689731945 ps
CPU time 805.21 seconds
Started Aug 01 06:55:11 PM PDT 24
Finished Aug 01 07:08:36 PM PDT 24
Peak memory 201452 kb
Host smart-de080419-77c8-45fd-9e30-8ab361f2069c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175158825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2175158825
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.253255453
Short name T277
Test name
Test status
Simulation time 323199035749 ps
CPU time 409.01 seconds
Started Aug 01 06:54:57 PM PDT 24
Finished Aug 01 07:01:46 PM PDT 24
Peak memory 201476 kb
Host smart-54d415d3-60b9-4cca-9b66-e7a3f75164b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253255453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.253255453
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2075527533
Short name T734
Test name
Test status
Simulation time 166442836239 ps
CPU time 116.03 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 06:56:52 PM PDT 24
Peak memory 201444 kb
Host smart-f89b1827-0ecc-4fc1-8c21-4b5e1c9e0665
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075527533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2075527533
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1587440003
Short name T488
Test name
Test status
Simulation time 325358305274 ps
CPU time 676.51 seconds
Started Aug 01 06:54:58 PM PDT 24
Finished Aug 01 07:06:14 PM PDT 24
Peak memory 201436 kb
Host smart-54aeb2cb-da96-4367-9ed6-3731ac631e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587440003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1587440003
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2198505
Short name T644
Test name
Test status
Simulation time 491818945965 ps
CPU time 1078.59 seconds
Started Aug 01 06:54:57 PM PDT 24
Finished Aug 01 07:12:56 PM PDT 24
Peak memory 201452 kb
Host smart-a2098f1f-26af-4a6f-a5b7-d95175841400
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.2198505
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1622962790
Short name T14
Test name
Test status
Simulation time 184556042633 ps
CPU time 207.58 seconds
Started Aug 01 06:55:11 PM PDT 24
Finished Aug 01 06:58:38 PM PDT 24
Peak memory 201396 kb
Host smart-a7f950a0-5058-45fd-b06e-538f02be8944
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622962790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1622962790
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.248882601
Short name T483
Test name
Test status
Simulation time 203930989670 ps
CPU time 362.69 seconds
Started Aug 01 06:55:10 PM PDT 24
Finished Aug 01 07:01:12 PM PDT 24
Peak memory 201488 kb
Host smart-8f1f512b-7f23-4c2d-8307-44d85e04de10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248882601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.248882601
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2252878695
Short name T213
Test name
Test status
Simulation time 99562637998 ps
CPU time 373.46 seconds
Started Aug 01 06:55:09 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 201800 kb
Host smart-ee4a0eb5-9bd9-43ef-b195-fd73fb166d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252878695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2252878695
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1770618392
Short name T777
Test name
Test status
Simulation time 38521444588 ps
CPU time 22.84 seconds
Started Aug 01 06:55:10 PM PDT 24
Finished Aug 01 06:55:33 PM PDT 24
Peak memory 201544 kb
Host smart-7a7512a3-e1de-455e-a4a1-ca6b6aad203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770618392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1770618392
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2497023599
Short name T525
Test name
Test status
Simulation time 3283963452 ps
CPU time 7.01 seconds
Started Aug 01 06:55:09 PM PDT 24
Finished Aug 01 06:55:16 PM PDT 24
Peak memory 201352 kb
Host smart-e500b86c-c9c0-4035-ab78-1f0a7881c547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497023599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2497023599
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2989259998
Short name T665
Test name
Test status
Simulation time 5924273612 ps
CPU time 13.21 seconds
Started Aug 01 06:54:56 PM PDT 24
Finished Aug 01 06:55:09 PM PDT 24
Peak memory 201320 kb
Host smart-21c6a397-57b1-4db6-9962-c643b0f95465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989259998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2989259998
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3741587503
Short name T123
Test name
Test status
Simulation time 101895611818 ps
CPU time 184.96 seconds
Started Aug 01 06:55:11 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 210204 kb
Host smart-bed81fe7-2bc6-413d-9cc7-eb42b7e9650c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741587503 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3741587503
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1845019675
Short name T615
Test name
Test status
Simulation time 464372063 ps
CPU time 0.9 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:52:01 PM PDT 24
Peak memory 200692 kb
Host smart-b92e242d-66f5-42b5-aee5-1521a7ab8a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845019675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1845019675
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.275527498
Short name T659
Test name
Test status
Simulation time 164203080822 ps
CPU time 98.39 seconds
Started Aug 01 06:52:04 PM PDT 24
Finished Aug 01 06:53:43 PM PDT 24
Peak memory 201500 kb
Host smart-3babc852-d30a-48ea-bd0e-69000adb930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275527498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.275527498
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3042254699
Short name T382
Test name
Test status
Simulation time 490903323617 ps
CPU time 221.34 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:55:41 PM PDT 24
Peak memory 201420 kb
Host smart-64721655-c202-4924-bc5c-2eefdd548a31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042254699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3042254699
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2119181615
Short name T766
Test name
Test status
Simulation time 167299487415 ps
CPU time 349.21 seconds
Started Aug 01 06:51:53 PM PDT 24
Finished Aug 01 06:57:43 PM PDT 24
Peak memory 201460 kb
Host smart-2d4b58bd-aab7-4fd7-8b8f-4079661fe60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119181615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2119181615
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.710520731
Short name T403
Test name
Test status
Simulation time 329879736461 ps
CPU time 230.1 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:55:52 PM PDT 24
Peak memory 201400 kb
Host smart-f97f2d62-ec15-4b82-b422-ee42103871ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=710520731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.710520731
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.343549500
Short name T602
Test name
Test status
Simulation time 204632586313 ps
CPU time 126.59 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:54:08 PM PDT 24
Peak memory 201432 kb
Host smart-663946c6-5a1f-4c82-8523-a5ff2f97641b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343549500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.343549500
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.565206890
Short name T533
Test name
Test status
Simulation time 35474072732 ps
CPU time 77.06 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:53:17 PM PDT 24
Peak memory 201348 kb
Host smart-bd80d9ee-3aad-4a4e-ae46-ab57f5999848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565206890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.565206890
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3748232984
Short name T380
Test name
Test status
Simulation time 4147994023 ps
CPU time 3.38 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:52:04 PM PDT 24
Peak memory 201312 kb
Host smart-2da38968-c868-4ba9-ba9e-779c1f7561fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748232984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3748232984
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.399106983
Short name T29
Test name
Test status
Simulation time 4243443151 ps
CPU time 3.42 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 06:52:01 PM PDT 24
Peak memory 217176 kb
Host smart-f0e5ec95-e953-4f26-adb3-8ebdd2ae21a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399106983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.399106983
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2783743218
Short name T351
Test name
Test status
Simulation time 5585602766 ps
CPU time 8.09 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:52:07 PM PDT 24
Peak memory 201368 kb
Host smart-b52be42a-128b-4b54-838f-cebdb09524a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783743218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2783743218
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3353527852
Short name T286
Test name
Test status
Simulation time 269162040491 ps
CPU time 713.23 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 07:03:56 PM PDT 24
Peak memory 212100 kb
Host smart-c3934945-dd09-48ee-8d9b-0f189ccf8b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353527852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3353527852
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.291070554
Short name T708
Test name
Test status
Simulation time 763613119579 ps
CPU time 391.09 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 217568 kb
Host smart-65a91c65-dbc8-4a6c-b4d9-4ee035bcf4b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291070554 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.291070554
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2613312892
Short name T617
Test name
Test status
Simulation time 393471995 ps
CPU time 1.51 seconds
Started Aug 01 06:55:18 PM PDT 24
Finished Aug 01 06:55:20 PM PDT 24
Peak memory 201212 kb
Host smart-b63dd916-9227-43e4-b619-cf8828eb69c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613312892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2613312892
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1360818733
Short name T271
Test name
Test status
Simulation time 182413779614 ps
CPU time 66.01 seconds
Started Aug 01 06:55:26 PM PDT 24
Finished Aug 01 06:56:33 PM PDT 24
Peak memory 201432 kb
Host smart-861c1858-a6c4-4f9e-9991-a9d229099687
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360818733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1360818733
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3618042997
Short name T156
Test name
Test status
Simulation time 195719153843 ps
CPU time 143.18 seconds
Started Aug 01 06:55:26 PM PDT 24
Finished Aug 01 06:57:50 PM PDT 24
Peak memory 201456 kb
Host smart-09402c12-b184-4a0d-9a55-5eb541a337cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618042997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3618042997
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1281820911
Short name T699
Test name
Test status
Simulation time 164491979031 ps
CPU time 392.69 seconds
Started Aug 01 06:55:10 PM PDT 24
Finished Aug 01 07:01:43 PM PDT 24
Peak memory 201564 kb
Host smart-6ae481a3-70b3-44c3-a938-154f804e246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281820911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1281820911
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3792595320
Short name T398
Test name
Test status
Simulation time 497815002781 ps
CPU time 1099.68 seconds
Started Aug 01 06:55:24 PM PDT 24
Finished Aug 01 07:13:44 PM PDT 24
Peak memory 201412 kb
Host smart-fe1aa4ad-3275-4ac8-ac5a-c3731ab2e538
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792595320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3792595320
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1412034052
Short name T147
Test name
Test status
Simulation time 490500804614 ps
CPU time 268.64 seconds
Started Aug 01 06:55:10 PM PDT 24
Finished Aug 01 06:59:39 PM PDT 24
Peak memory 201428 kb
Host smart-65b3b90b-ecff-4c80-953a-8b465a75c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412034052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1412034052
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3216130220
Short name T427
Test name
Test status
Simulation time 162597408852 ps
CPU time 98.05 seconds
Started Aug 01 06:55:08 PM PDT 24
Finished Aug 01 06:56:47 PM PDT 24
Peak memory 201412 kb
Host smart-f45a6b60-79ce-44fd-a32a-93e8145cc7b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216130220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3216130220
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.599456009
Short name T333
Test name
Test status
Simulation time 363848962215 ps
CPU time 819.58 seconds
Started Aug 01 06:55:27 PM PDT 24
Finished Aug 01 07:09:06 PM PDT 24
Peak memory 201448 kb
Host smart-e3513753-8eeb-4ca2-84f3-9eefe41169fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599456009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.599456009
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1635106015
Short name T622
Test name
Test status
Simulation time 608289232569 ps
CPU time 1420.61 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 07:19:00 PM PDT 24
Peak memory 201448 kb
Host smart-64290411-fc2d-477e-9b3f-5d05f7aa3f8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635106015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1635106015
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1068738549
Short name T738
Test name
Test status
Simulation time 96099909686 ps
CPU time 308.08 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 07:00:28 PM PDT 24
Peak memory 201788 kb
Host smart-c57e5f0b-c761-4db7-b1d8-c21015c9ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068738549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1068738549
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1806688627
Short name T764
Test name
Test status
Simulation time 43820160710 ps
CPU time 25.36 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 06:55:44 PM PDT 24
Peak memory 201380 kb
Host smart-1204788a-28c7-4136-aaa3-6d5d2e95d365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806688627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1806688627
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.108222388
Short name T42
Test name
Test status
Simulation time 4507348176 ps
CPU time 2.39 seconds
Started Aug 01 06:55:18 PM PDT 24
Finished Aug 01 06:55:21 PM PDT 24
Peak memory 201356 kb
Host smart-db4aa524-970a-46fb-ac1e-37ee387f8ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108222388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.108222388
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3958703578
Short name T354
Test name
Test status
Simulation time 5995313279 ps
CPU time 8.05 seconds
Started Aug 01 06:55:09 PM PDT 24
Finished Aug 01 06:55:17 PM PDT 24
Peak memory 201336 kb
Host smart-1f68ed70-e355-441c-a4d0-2684a4dfbbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958703578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3958703578
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2090584210
Short name T715
Test name
Test status
Simulation time 297487730252 ps
CPU time 412.64 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 07:02:12 PM PDT 24
Peak memory 210072 kb
Host smart-9abfc227-1367-44a0-95a0-61dacf757b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090584210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2090584210
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.587779328
Short name T308
Test name
Test status
Simulation time 77605317789 ps
CPU time 90.1 seconds
Started Aug 01 06:55:25 PM PDT 24
Finished Aug 01 06:56:55 PM PDT 24
Peak memory 209756 kb
Host smart-a02cb314-2828-4496-8731-5caec6a868f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587779328 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.587779328
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3650097681
Short name T570
Test name
Test status
Simulation time 307300818 ps
CPU time 0.95 seconds
Started Aug 01 06:55:31 PM PDT 24
Finished Aug 01 06:55:32 PM PDT 24
Peak memory 201248 kb
Host smart-46e5d2ec-fde9-4e88-99c3-20847de5c7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650097681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3650097681
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2990735667
Short name T268
Test name
Test status
Simulation time 505229461667 ps
CPU time 555.01 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 07:04:34 PM PDT 24
Peak memory 201420 kb
Host smart-36714e72-94e7-427b-bdfd-c9643a12044b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990735667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2990735667
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2613116718
Short name T629
Test name
Test status
Simulation time 193461403840 ps
CPU time 114.5 seconds
Started Aug 01 06:55:25 PM PDT 24
Finished Aug 01 06:57:19 PM PDT 24
Peak memory 201420 kb
Host smart-00e22557-2878-4b30-98ed-d773416a1e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613116718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2613116718
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2777302657
Short name T183
Test name
Test status
Simulation time 497026964680 ps
CPU time 304.58 seconds
Started Aug 01 06:55:21 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 201464 kb
Host smart-f268efdd-c281-47ef-a28d-0fdd2361886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777302657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2777302657
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2906757411
Short name T395
Test name
Test status
Simulation time 490585973239 ps
CPU time 577.29 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 07:04:56 PM PDT 24
Peak memory 201460 kb
Host smart-85c744b6-e5e6-44d2-84e5-09faa71f8341
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906757411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2906757411
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1010077360
Short name T204
Test name
Test status
Simulation time 329652918136 ps
CPU time 159.52 seconds
Started Aug 01 06:55:22 PM PDT 24
Finished Aug 01 06:58:02 PM PDT 24
Peak memory 201460 kb
Host smart-b96e18a1-ecfb-4cd5-b51b-12923490e9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010077360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1010077360
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3080418165
Short name T612
Test name
Test status
Simulation time 490675525626 ps
CPU time 290.99 seconds
Started Aug 01 06:55:20 PM PDT 24
Finished Aug 01 07:00:11 PM PDT 24
Peak memory 201424 kb
Host smart-9d40d2c8-39ca-4b87-86e0-c583fb697ae8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080418165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3080418165
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3360759614
Short name T179
Test name
Test status
Simulation time 343200274106 ps
CPU time 823.3 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 07:09:02 PM PDT 24
Peak memory 201420 kb
Host smart-e16ff2e0-109a-4a7d-b308-0bbdb361127e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360759614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3360759614
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3727535967
Short name T710
Test name
Test status
Simulation time 409637252057 ps
CPU time 245.86 seconds
Started Aug 01 06:55:26 PM PDT 24
Finished Aug 01 06:59:32 PM PDT 24
Peak memory 201432 kb
Host smart-66f16cbf-7e69-44dd-a765-1a90d8dc5dc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727535967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3727535967
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.643285107
Short name T517
Test name
Test status
Simulation time 79399006040 ps
CPU time 417.05 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 07:02:16 PM PDT 24
Peak memory 201824 kb
Host smart-c0e5c801-e5ee-4b05-8e55-0b5063053c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643285107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.643285107
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.225105499
Short name T359
Test name
Test status
Simulation time 47716783747 ps
CPU time 103.67 seconds
Started Aug 01 06:55:19 PM PDT 24
Finished Aug 01 06:57:02 PM PDT 24
Peak memory 201348 kb
Host smart-c87fdf5e-9e1c-43a6-9392-7bcae575e32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225105499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.225105499
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1078837283
Short name T353
Test name
Test status
Simulation time 3847438534 ps
CPU time 2.89 seconds
Started Aug 01 06:55:25 PM PDT 24
Finished Aug 01 06:55:28 PM PDT 24
Peak memory 201360 kb
Host smart-e2fab7a2-7fc8-4e71-b32a-e76b16df5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078837283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1078837283
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1462772160
Short name T571
Test name
Test status
Simulation time 6022956496 ps
CPU time 15.01 seconds
Started Aug 01 06:55:20 PM PDT 24
Finished Aug 01 06:55:35 PM PDT 24
Peak memory 201352 kb
Host smart-893e997b-a9db-4926-8277-69f17f4270fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462772160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1462772160
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3122033773
Short name T613
Test name
Test status
Simulation time 302218161169 ps
CPU time 122.9 seconds
Started Aug 01 06:55:31 PM PDT 24
Finished Aug 01 06:57:34 PM PDT 24
Peak memory 209752 kb
Host smart-87b16d59-f7d6-4139-8ee8-5d158e812c55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122033773 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3122033773
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.209058178
Short name T724
Test name
Test status
Simulation time 413490490 ps
CPU time 1.49 seconds
Started Aug 01 06:55:42 PM PDT 24
Finished Aug 01 06:55:43 PM PDT 24
Peak memory 201260 kb
Host smart-89adfde9-fc23-4732-a433-0bbb0d66984f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209058178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.209058178
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3060893262
Short name T315
Test name
Test status
Simulation time 179235839354 ps
CPU time 4.83 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 06:55:35 PM PDT 24
Peak memory 201404 kb
Host smart-b679397b-7804-47dd-ac9a-50a45b802752
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060893262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3060893262
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3233545623
Short name T59
Test name
Test status
Simulation time 171024706489 ps
CPU time 211.9 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 06:59:02 PM PDT 24
Peak memory 201452 kb
Host smart-91dce1e8-4961-4193-ac23-99dd21958802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233545623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3233545623
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2984214375
Short name T355
Test name
Test status
Simulation time 327067740537 ps
CPU time 241.15 seconds
Started Aug 01 06:55:32 PM PDT 24
Finished Aug 01 06:59:33 PM PDT 24
Peak memory 201480 kb
Host smart-3daf49af-1a93-4f3c-bc27-a9c6fe339a3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984214375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2984214375
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1655441569
Short name T158
Test name
Test status
Simulation time 319507083181 ps
CPU time 703.74 seconds
Started Aug 01 06:55:29 PM PDT 24
Finished Aug 01 07:07:13 PM PDT 24
Peak memory 201384 kb
Host smart-d7a6fef9-6e2d-4651-96e9-1b9cbdb882e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655441569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1655441569
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3177236017
Short name T499
Test name
Test status
Simulation time 490872115452 ps
CPU time 1025.1 seconds
Started Aug 01 06:55:31 PM PDT 24
Finished Aug 01 07:12:36 PM PDT 24
Peak memory 201448 kb
Host smart-6426e5e6-bab0-497b-afa8-31859f130b9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177236017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3177236017
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1951152923
Short name T328
Test name
Test status
Simulation time 391695993222 ps
CPU time 874.72 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 07:10:05 PM PDT 24
Peak memory 201424 kb
Host smart-0936b43d-8193-4edd-b7bb-4b1ab77b64a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951152923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1951152923
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1859787123
Short name T212
Test name
Test status
Simulation time 88683445305 ps
CPU time 464.04 seconds
Started Aug 01 06:55:29 PM PDT 24
Finished Aug 01 07:03:13 PM PDT 24
Peak memory 201808 kb
Host smart-374f3b3a-32f5-4ed1-a125-deeb80425829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859787123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1859787123
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.57184850
Short name T392
Test name
Test status
Simulation time 27513925812 ps
CPU time 65.21 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 06:56:35 PM PDT 24
Peak memory 201300 kb
Host smart-a7662677-7e9b-4cd3-af13-1223bda10173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57184850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.57184850
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2317728638
Short name T538
Test name
Test status
Simulation time 4293165038 ps
CPU time 4.22 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 06:55:35 PM PDT 24
Peak memory 201352 kb
Host smart-5744d305-a8c7-4060-a226-f9bbb7246e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317728638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2317728638
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2774415765
Short name T643
Test name
Test status
Simulation time 5812504202 ps
CPU time 4.27 seconds
Started Aug 01 06:55:30 PM PDT 24
Finished Aug 01 06:55:35 PM PDT 24
Peak memory 201376 kb
Host smart-0dede333-54f8-45b6-953e-e2bfa6f1343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774415765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2774415765
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.961970734
Short name T694
Test name
Test status
Simulation time 268705997491 ps
CPU time 412.86 seconds
Started Aug 01 06:55:40 PM PDT 24
Finished Aug 01 07:02:33 PM PDT 24
Peak memory 210028 kb
Host smart-a8ca7951-950d-4b5f-8e74-5c216af82f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961970734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
961970734
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.4012461638
Short name T305
Test name
Test status
Simulation time 263670648929 ps
CPU time 87.4 seconds
Started Aug 01 06:55:40 PM PDT 24
Finished Aug 01 06:57:07 PM PDT 24
Peak memory 209776 kb
Host smart-f0d3c38f-b361-44bf-8461-47b0793ae7ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012461638 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.4012461638
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2982889786
Short name T112
Test name
Test status
Simulation time 552919341 ps
CPU time 0.95 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 06:55:42 PM PDT 24
Peak memory 201244 kb
Host smart-33090f43-fc01-45a9-b22e-44dff246dd5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982889786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2982889786
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1330209267
Short name T675
Test name
Test status
Simulation time 330651520358 ps
CPU time 35.1 seconds
Started Aug 01 06:55:43 PM PDT 24
Finished Aug 01 06:56:19 PM PDT 24
Peak memory 201548 kb
Host smart-1f48024e-57cb-4ff3-8a33-7d58829f04f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330209267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1330209267
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3791328654
Short name T487
Test name
Test status
Simulation time 505009704973 ps
CPU time 284.23 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 201500 kb
Host smart-7866d98a-9f2c-4a9f-ba26-01b399649b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791328654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3791328654
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.4276034574
Short name T177
Test name
Test status
Simulation time 327474358693 ps
CPU time 212.03 seconds
Started Aug 01 06:55:42 PM PDT 24
Finished Aug 01 06:59:15 PM PDT 24
Peak memory 201524 kb
Host smart-e802ba6e-aa46-4450-ad1f-81bf32e2a739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276034574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4276034574
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1765238604
Short name T464
Test name
Test status
Simulation time 327159565466 ps
CPU time 112.07 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 06:57:33 PM PDT 24
Peak memory 201452 kb
Host smart-768d238c-b513-4b9b-855b-200fe4ba1459
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765238604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1765238604
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.305207860
Short name T330
Test name
Test status
Simulation time 332689513135 ps
CPU time 114.14 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 06:57:35 PM PDT 24
Peak memory 201412 kb
Host smart-b1397e39-1047-4aeb-bf0a-04d2e6bcfc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305207860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.305207860
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1436281144
Short name T478
Test name
Test status
Simulation time 487097687130 ps
CPU time 1163.58 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 07:15:05 PM PDT 24
Peak memory 201428 kb
Host smart-b8e3f460-a14f-4d6c-916d-b97b3b556c56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436281144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1436281144
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.796840377
Short name T784
Test name
Test status
Simulation time 547774194383 ps
CPU time 1128.48 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 07:14:29 PM PDT 24
Peak memory 201436 kb
Host smart-7399723a-6cb2-4904-813e-1f6d991492eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796840377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.796840377
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2091559012
Short name T389
Test name
Test status
Simulation time 594124106593 ps
CPU time 1304.47 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 07:17:26 PM PDT 24
Peak memory 201424 kb
Host smart-ffdb2051-6670-4702-b132-3100b969addd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091559012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2091559012
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.887295999
Short name T698
Test name
Test status
Simulation time 133263277528 ps
CPU time 422.21 seconds
Started Aug 01 06:55:40 PM PDT 24
Finished Aug 01 07:02:43 PM PDT 24
Peak memory 201840 kb
Host smart-c2c0ac77-a7ad-4bf5-95e8-fca51db6fbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887295999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.887295999
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4132022883
Short name T709
Test name
Test status
Simulation time 29122088608 ps
CPU time 67.89 seconds
Started Aug 01 06:55:40 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 201356 kb
Host smart-4a5612ec-b06e-42b2-9458-535850a626cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132022883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4132022883
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1199035553
Short name T10
Test name
Test status
Simulation time 5506487479 ps
CPU time 3.75 seconds
Started Aug 01 06:55:42 PM PDT 24
Finished Aug 01 06:55:46 PM PDT 24
Peak memory 201348 kb
Host smart-47769d5e-a16f-457a-8d8e-913f943ee2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199035553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1199035553
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3096419065
Short name T564
Test name
Test status
Simulation time 6036200636 ps
CPU time 13.62 seconds
Started Aug 01 06:55:40 PM PDT 24
Finished Aug 01 06:55:54 PM PDT 24
Peak memory 201336 kb
Host smart-f81d1843-b02b-46ae-901c-3ef5f8b8b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096419065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3096419065
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3236207502
Short name T94
Test name
Test status
Simulation time 315635846 ps
CPU time 0.79 seconds
Started Aug 01 06:55:54 PM PDT 24
Finished Aug 01 06:55:55 PM PDT 24
Peak memory 201220 kb
Host smart-b62e3387-387b-43d6-9c5c-87e47b33605a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236207502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3236207502
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2473285898
Short name T775
Test name
Test status
Simulation time 342525196401 ps
CPU time 394.66 seconds
Started Aug 01 06:55:56 PM PDT 24
Finished Aug 01 07:02:31 PM PDT 24
Peak memory 201424 kb
Host smart-be0e09b5-daf5-44a4-ac75-24374cc7e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473285898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2473285898
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.272065166
Short name T735
Test name
Test status
Simulation time 490992268935 ps
CPU time 516.75 seconds
Started Aug 01 06:55:43 PM PDT 24
Finished Aug 01 07:04:20 PM PDT 24
Peak memory 201452 kb
Host smart-6807a134-ac19-4485-bcc9-f82e9e12fbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272065166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.272065166
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1455469889
Short name T107
Test name
Test status
Simulation time 328017388798 ps
CPU time 52.11 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 06:56:33 PM PDT 24
Peak memory 201456 kb
Host smart-8cbbe809-3307-4e36-8636-79e26c3508a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455469889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1455469889
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1807640255
Short name T707
Test name
Test status
Simulation time 498820750789 ps
CPU time 651.36 seconds
Started Aug 01 06:55:40 PM PDT 24
Finished Aug 01 07:06:32 PM PDT 24
Peak memory 201452 kb
Host smart-a0d35501-5e3d-4067-886b-1b6172ccb76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807640255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1807640255
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.146754947
Short name T671
Test name
Test status
Simulation time 164592940143 ps
CPU time 360.77 seconds
Started Aug 01 06:55:43 PM PDT 24
Finished Aug 01 07:01:44 PM PDT 24
Peak memory 201464 kb
Host smart-400739c3-e3f1-4764-8fa7-5fe47ef84935
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=146754947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.146754947
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.483881019
Short name T257
Test name
Test status
Simulation time 365686267044 ps
CPU time 185.13 seconds
Started Aug 01 06:55:42 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 201432 kb
Host smart-6a693686-3461-48d6-8a04-7efcd5cb7f37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483881019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.483881019
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2992425060
Short name T410
Test name
Test status
Simulation time 615983156647 ps
CPU time 362.24 seconds
Started Aug 01 06:55:54 PM PDT 24
Finished Aug 01 07:01:57 PM PDT 24
Peak memory 201356 kb
Host smart-f4a987c9-5be0-479a-8fa1-9635490c6303
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992425060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2992425060
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1033047976
Short name T421
Test name
Test status
Simulation time 74813281483 ps
CPU time 324.83 seconds
Started Aug 01 06:55:56 PM PDT 24
Finished Aug 01 07:01:22 PM PDT 24
Peak memory 201812 kb
Host smart-96fe9bbb-e978-4445-85eb-a3b13659bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033047976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1033047976
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3021074707
Short name T687
Test name
Test status
Simulation time 44438904639 ps
CPU time 75.49 seconds
Started Aug 01 06:55:54 PM PDT 24
Finished Aug 01 06:57:10 PM PDT 24
Peak memory 201360 kb
Host smart-71c7390c-d9db-4769-8cbe-c2c34ef2c3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021074707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3021074707
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2312969432
Short name T364
Test name
Test status
Simulation time 3335280948 ps
CPU time 4.47 seconds
Started Aug 01 06:55:56 PM PDT 24
Finished Aug 01 06:56:00 PM PDT 24
Peak memory 201364 kb
Host smart-8487047f-309d-4e18-be16-57a88eb2c8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312969432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2312969432
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3106103680
Short name T717
Test name
Test status
Simulation time 5882344011 ps
CPU time 14.36 seconds
Started Aug 01 06:55:41 PM PDT 24
Finished Aug 01 06:55:56 PM PDT 24
Peak memory 201368 kb
Host smart-a70ff115-9257-44a4-a2e4-122b0c57c143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106103680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3106103680
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.908555366
Short name T495
Test name
Test status
Simulation time 170377946350 ps
CPU time 147.68 seconds
Started Aug 01 06:55:57 PM PDT 24
Finished Aug 01 06:58:24 PM PDT 24
Peak memory 201432 kb
Host smart-b0d1b4a2-b814-46f3-b6c8-2141a73e2f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908555366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
908555366
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.765506097
Short name T790
Test name
Test status
Simulation time 505361301 ps
CPU time 1.18 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 06:56:06 PM PDT 24
Peak memory 201216 kb
Host smart-c8261bdb-2a5b-47a3-b3c8-a21b3668a221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765506097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.765506097
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1114702811
Short name T688
Test name
Test status
Simulation time 331519349968 ps
CPU time 164.41 seconds
Started Aug 01 06:55:55 PM PDT 24
Finished Aug 01 06:58:39 PM PDT 24
Peak memory 201388 kb
Host smart-1345d699-dd1c-4106-9365-f9bd8f95652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114702811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1114702811
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1452588417
Short name T178
Test name
Test status
Simulation time 163404316084 ps
CPU time 64.12 seconds
Started Aug 01 06:55:57 PM PDT 24
Finished Aug 01 06:57:01 PM PDT 24
Peak memory 201444 kb
Host smart-ad69d4c0-0f40-4c94-a195-d801ca5342e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452588417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1452588417
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.377947569
Short name T40
Test name
Test status
Simulation time 167814359726 ps
CPU time 215.89 seconds
Started Aug 01 06:55:58 PM PDT 24
Finished Aug 01 06:59:34 PM PDT 24
Peak memory 201444 kb
Host smart-f87be320-15a2-4871-81e7-503f20120e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377947569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.377947569
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.29519528
Short name T683
Test name
Test status
Simulation time 162099232545 ps
CPU time 367.38 seconds
Started Aug 01 06:55:55 PM PDT 24
Finished Aug 01 07:02:03 PM PDT 24
Peak memory 201432 kb
Host smart-51288d89-3591-469a-a0c7-10b0cc0efad1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=29519528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed
.29519528
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.431178971
Short name T199
Test name
Test status
Simulation time 362958609182 ps
CPU time 309.43 seconds
Started Aug 01 06:55:55 PM PDT 24
Finished Aug 01 07:01:04 PM PDT 24
Peak memory 201416 kb
Host smart-060c62d6-d0ab-41fa-b921-0dcd189d5834
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431178971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.431178971
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3614342145
Short name T596
Test name
Test status
Simulation time 203913047340 ps
CPU time 441.08 seconds
Started Aug 01 06:55:55 PM PDT 24
Finished Aug 01 07:03:16 PM PDT 24
Peak memory 201436 kb
Host smart-85b32cc2-7b3e-43e3-8c56-1ec58ad1c28c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614342145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3614342145
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.129445130
Short name T215
Test name
Test status
Simulation time 119229487910 ps
CPU time 636.46 seconds
Started Aug 01 06:56:06 PM PDT 24
Finished Aug 01 07:06:42 PM PDT 24
Peak memory 201840 kb
Host smart-3ffcc72c-0969-46d3-adf2-26ea2a03ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129445130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.129445130
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2490901446
Short name T455
Test name
Test status
Simulation time 23290665750 ps
CPU time 27.11 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 06:56:32 PM PDT 24
Peak memory 201348 kb
Host smart-dd650248-0b4e-49da-810b-d4d11f4bd509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490901446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2490901446
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3619610040
Short name T630
Test name
Test status
Simulation time 3109909976 ps
CPU time 4.28 seconds
Started Aug 01 06:55:56 PM PDT 24
Finished Aug 01 06:56:01 PM PDT 24
Peak memory 201348 kb
Host smart-ad43543b-0886-403f-84af-bff77aab217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619610040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3619610040
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2805700542
Short name T743
Test name
Test status
Simulation time 5831277073 ps
CPU time 13.36 seconds
Started Aug 01 06:55:57 PM PDT 24
Finished Aug 01 06:56:11 PM PDT 24
Peak memory 201380 kb
Host smart-314d13e2-ae0b-46af-8b6d-d58cf79e5768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805700542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2805700542
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3680871816
Short name T69
Test name
Test status
Simulation time 260219346608 ps
CPU time 429.79 seconds
Started Aug 01 06:56:04 PM PDT 24
Finished Aug 01 07:03:14 PM PDT 24
Peak memory 209980 kb
Host smart-a6dede24-c9be-4012-9bb0-864dd7d382ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680871816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3680871816
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3817344111
Short name T37
Test name
Test status
Simulation time 103989633515 ps
CPU time 116.75 seconds
Started Aug 01 06:56:06 PM PDT 24
Finished Aug 01 06:58:03 PM PDT 24
Peak memory 209816 kb
Host smart-4871e7e7-9eb2-45a2-89d0-375a61c7f1a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817344111 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3817344111
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2767806307
Short name T787
Test name
Test status
Simulation time 296741922 ps
CPU time 0.9 seconds
Started Aug 01 06:56:07 PM PDT 24
Finished Aug 01 06:56:08 PM PDT 24
Peak memory 201212 kb
Host smart-4fc1f301-1e17-4ec5-96f7-9638669f23fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767806307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2767806307
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.278122617
Short name T312
Test name
Test status
Simulation time 168089668953 ps
CPU time 105.67 seconds
Started Aug 01 06:56:07 PM PDT 24
Finished Aug 01 06:57:53 PM PDT 24
Peak memory 201392 kb
Host smart-121f8f47-d80f-4d1f-bba6-41387e0f7a82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278122617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.278122617
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4191314770
Short name T750
Test name
Test status
Simulation time 360832569740 ps
CPU time 221.31 seconds
Started Aug 01 06:56:06 PM PDT 24
Finished Aug 01 06:59:47 PM PDT 24
Peak memory 201440 kb
Host smart-115e1da5-09c8-45c3-9ad2-3924f25d3a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191314770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4191314770
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4084269531
Short name T252
Test name
Test status
Simulation time 167559603151 ps
CPU time 190.83 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 06:59:15 PM PDT 24
Peak memory 201404 kb
Host smart-0151b9d4-9521-4aba-92d7-64bd1e33a294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084269531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4084269531
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.447230196
Short name T593
Test name
Test status
Simulation time 165639957113 ps
CPU time 102.59 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 06:57:48 PM PDT 24
Peak memory 201492 kb
Host smart-88607728-a931-4f79-8a11-ca4ab797a59f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=447230196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.447230196
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1890534723
Short name T614
Test name
Test status
Simulation time 488555690663 ps
CPU time 562.58 seconds
Started Aug 01 06:56:07 PM PDT 24
Finished Aug 01 07:05:30 PM PDT 24
Peak memory 201412 kb
Host smart-8413af73-fae3-494e-912c-b60d0d438343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890534723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1890534723
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1925250646
Short name T100
Test name
Test status
Simulation time 331945245704 ps
CPU time 774.46 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 07:09:00 PM PDT 24
Peak memory 201604 kb
Host smart-b33c049b-77a7-4e14-a241-3081bdb8d43d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925250646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1925250646
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1334074607
Short name T260
Test name
Test status
Simulation time 468333776471 ps
CPU time 1016.04 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 07:13:01 PM PDT 24
Peak memory 201452 kb
Host smart-b84e0b7d-dc27-461b-8caf-402d5e3f4662
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334074607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1334074607
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3417801756
Short name T721
Test name
Test status
Simulation time 395961553623 ps
CPU time 240.92 seconds
Started Aug 01 06:56:06 PM PDT 24
Finished Aug 01 07:00:07 PM PDT 24
Peak memory 201476 kb
Host smart-37532a32-12c2-4bc8-9b59-3ce3733de23e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417801756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3417801756
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1872863352
Short name T534
Test name
Test status
Simulation time 105827400272 ps
CPU time 611.08 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 07:06:16 PM PDT 24
Peak memory 201856 kb
Host smart-200418ab-993c-413d-a62c-692d7fff4ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872863352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1872863352
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2294798392
Short name T713
Test name
Test status
Simulation time 37609816985 ps
CPU time 64.12 seconds
Started Aug 01 06:56:07 PM PDT 24
Finished Aug 01 06:57:11 PM PDT 24
Peak memory 201376 kb
Host smart-77cf75e6-f4e6-4162-83d2-52621753e353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294798392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2294798392
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2249824574
Short name T6
Test name
Test status
Simulation time 3934921105 ps
CPU time 10.12 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 06:56:15 PM PDT 24
Peak memory 201324 kb
Host smart-11a26c54-d306-401d-9572-c195d2d78333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249824574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2249824574
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.734320955
Short name T780
Test name
Test status
Simulation time 5654114053 ps
CPU time 7.38 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 06:56:13 PM PDT 24
Peak memory 201360 kb
Host smart-2e1239ff-1a85-4420-a7d4-a8be84a1d97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734320955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.734320955
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1795788877
Short name T502
Test name
Test status
Simulation time 76011043492 ps
CPU time 200.71 seconds
Started Aug 01 06:56:05 PM PDT 24
Finished Aug 01 06:59:26 PM PDT 24
Peak memory 217424 kb
Host smart-464f424a-cc19-4a22-8746-8c9068e04c0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795788877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1795788877
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2967809567
Short name T432
Test name
Test status
Simulation time 446268879 ps
CPU time 0.9 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:56:18 PM PDT 24
Peak memory 201260 kb
Host smart-4af44d14-314f-4d97-8240-7cbd096665e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967809567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2967809567
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1557975084
Short name T770
Test name
Test status
Simulation time 506571791650 ps
CPU time 97.87 seconds
Started Aug 01 06:56:15 PM PDT 24
Finished Aug 01 06:57:53 PM PDT 24
Peak memory 201504 kb
Host smart-33abd7ed-c5b6-4e15-bc26-1595f0da4500
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557975084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1557975084
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.25452949
Short name T426
Test name
Test status
Simulation time 494939224507 ps
CPU time 74.68 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:57:32 PM PDT 24
Peak memory 201432 kb
Host smart-ff30e67f-7d6a-42ce-833a-55375b8e6032
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=25452949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt
_fixed.25452949
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3987951618
Short name T588
Test name
Test status
Simulation time 339762608327 ps
CPU time 118.51 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 201392 kb
Host smart-5786b2ee-6e7e-4150-8024-8f86f44da901
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987951618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3987951618
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.419544893
Short name T160
Test name
Test status
Simulation time 177161433875 ps
CPU time 42.85 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:57:00 PM PDT 24
Peak memory 201420 kb
Host smart-407b86b1-c9b1-4cdd-976c-e3f6a9be3818
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419544893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.419544893
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2716137303
Short name T636
Test name
Test status
Simulation time 595539168780 ps
CPU time 1424.04 seconds
Started Aug 01 06:56:16 PM PDT 24
Finished Aug 01 07:20:01 PM PDT 24
Peak memory 201360 kb
Host smart-42ce6541-8864-4711-875c-626687ed7ba0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716137303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2716137303
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.899917896
Short name T737
Test name
Test status
Simulation time 68705774314 ps
CPU time 247.6 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 07:00:25 PM PDT 24
Peak memory 201944 kb
Host smart-57cf6bdd-b696-49e3-b0ef-e2f0f56a81f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899917896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.899917896
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4037032400
Short name T645
Test name
Test status
Simulation time 35365772919 ps
CPU time 21.55 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:56:39 PM PDT 24
Peak memory 201376 kb
Host smart-1381b92f-f29d-446b-90da-33b550d22297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037032400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.4037032400
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1528958818
Short name T385
Test name
Test status
Simulation time 3548552519 ps
CPU time 9.62 seconds
Started Aug 01 06:56:16 PM PDT 24
Finished Aug 01 06:56:26 PM PDT 24
Peak memory 201344 kb
Host smart-2271fded-42fa-4ecd-b954-3b672654d998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528958818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1528958818
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3847469749
Short name T677
Test name
Test status
Simulation time 5891894026 ps
CPU time 5.64 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:56:23 PM PDT 24
Peak memory 201364 kb
Host smart-ce7b0d1d-ba62-4a0a-8f03-e8ec980cf63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847469749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3847469749
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4077294722
Short name T19
Test name
Test status
Simulation time 10663062062 ps
CPU time 26.52 seconds
Started Aug 01 06:56:18 PM PDT 24
Finished Aug 01 06:56:45 PM PDT 24
Peak memory 209864 kb
Host smart-2c6dff2f-5b26-424c-aae2-7bcb929bfdeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077294722 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.4077294722
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2746622986
Short name T497
Test name
Test status
Simulation time 472789966 ps
CPU time 1.35 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:37 PM PDT 24
Peak memory 201240 kb
Host smart-734179c6-091b-4101-9ab5-bc31cca5ce82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746622986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2746622986
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.703364774
Short name T185
Test name
Test status
Simulation time 343411333645 ps
CPU time 206.95 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:59:44 PM PDT 24
Peak memory 201432 kb
Host smart-a635a742-a41f-41f6-88f3-aacb0a08ae51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703364774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.703364774
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.193084235
Short name T300
Test name
Test status
Simulation time 494447757850 ps
CPU time 1090.83 seconds
Started Aug 01 06:56:16 PM PDT 24
Finished Aug 01 07:14:27 PM PDT 24
Peak memory 201452 kb
Host smart-92ba9d1f-0766-40d9-ae04-d470264b77b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193084235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.193084235
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3645363566
Short name T547
Test name
Test status
Simulation time 323369659933 ps
CPU time 116.89 seconds
Started Aug 01 06:56:16 PM PDT 24
Finished Aug 01 06:58:13 PM PDT 24
Peak memory 201516 kb
Host smart-ed05742e-2774-47a2-8189-807fc384a418
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645363566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3645363566
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3867641101
Short name T99
Test name
Test status
Simulation time 165216422418 ps
CPU time 354.78 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 07:02:12 PM PDT 24
Peak memory 201448 kb
Host smart-382c887b-a99b-487b-816f-efbb7606ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867641101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3867641101
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3712236261
Short name T718
Test name
Test status
Simulation time 334352876260 ps
CPU time 174.74 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:59:12 PM PDT 24
Peak memory 201468 kb
Host smart-4a232b28-86d5-4a62-9454-f8bb3d72f999
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712236261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3712236261
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3639865659
Short name T273
Test name
Test status
Simulation time 372632589017 ps
CPU time 146.21 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 201460 kb
Host smart-435582f0-66aa-436b-a26a-880aa83bf31d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639865659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3639865659
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2237780059
Short name T163
Test name
Test status
Simulation time 645207533488 ps
CPU time 376.62 seconds
Started Aug 01 06:56:18 PM PDT 24
Finished Aug 01 07:02:34 PM PDT 24
Peak memory 201416 kb
Host smart-72679c37-223f-4210-bcf6-4beafb4e77b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237780059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2237780059
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.341729108
Short name T345
Test name
Test status
Simulation time 97720974186 ps
CPU time 355.42 seconds
Started Aug 01 06:56:27 PM PDT 24
Finished Aug 01 07:02:22 PM PDT 24
Peak memory 201884 kb
Host smart-a0b524aa-c20f-4447-9d69-31637b793d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341729108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.341729108
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.862324561
Short name T558
Test name
Test status
Simulation time 24926578121 ps
CPU time 9.62 seconds
Started Aug 01 06:56:31 PM PDT 24
Finished Aug 01 06:56:41 PM PDT 24
Peak memory 201388 kb
Host smart-676b6098-6f24-4625-8aee-0aed43e2e5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862324561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.862324561
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.21742332
Short name T716
Test name
Test status
Simulation time 4795735091 ps
CPU time 12.47 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 201368 kb
Host smart-50f8a28e-c265-495c-9d73-4330f0b3a7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21742332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.21742332
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1434043712
Short name T485
Test name
Test status
Simulation time 5932993363 ps
CPU time 7.51 seconds
Started Aug 01 06:56:17 PM PDT 24
Finished Aug 01 06:56:25 PM PDT 24
Peak memory 201368 kb
Host smart-7464c0f2-4157-4f5b-a47b-f5a41b83887a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434043712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1434043712
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1160520924
Short name T481
Test name
Test status
Simulation time 297984358175 ps
CPU time 1051.84 seconds
Started Aug 01 06:56:29 PM PDT 24
Finished Aug 01 07:14:01 PM PDT 24
Peak memory 211772 kb
Host smart-9af09dc6-1f39-4c3b-923a-318220b13b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160520924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1160520924
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2999631457
Short name T49
Test name
Test status
Simulation time 119517067926 ps
CPU time 212.38 seconds
Started Aug 01 06:56:30 PM PDT 24
Finished Aug 01 07:00:02 PM PDT 24
Peak memory 210224 kb
Host smart-d853ffbf-e400-4024-9efb-b3c69257a6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999631457 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2999631457
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3873115803
Short name T690
Test name
Test status
Simulation time 345781696 ps
CPU time 1.42 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:38 PM PDT 24
Peak memory 201292 kb
Host smart-cc679330-ee01-448e-98b4-0a25a754ef5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873115803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3873115803
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3467507642
Short name T245
Test name
Test status
Simulation time 168489901470 ps
CPU time 28.26 seconds
Started Aug 01 06:56:32 PM PDT 24
Finished Aug 01 06:57:00 PM PDT 24
Peak memory 201512 kb
Host smart-d78fea9e-cd81-4ae2-9681-71f78e9ebdf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467507642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3467507642
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1246539277
Short name T336
Test name
Test status
Simulation time 520958139686 ps
CPU time 324.71 seconds
Started Aug 01 06:56:30 PM PDT 24
Finished Aug 01 07:01:55 PM PDT 24
Peak memory 201512 kb
Host smart-40625dcc-4bea-4894-9e67-627fbaf589fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246539277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1246539277
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1186933340
Short name T243
Test name
Test status
Simulation time 319646397138 ps
CPU time 762.25 seconds
Started Aug 01 06:56:37 PM PDT 24
Finished Aug 01 07:09:19 PM PDT 24
Peak memory 201464 kb
Host smart-d3edfbbf-5f2c-4c60-88a4-44b5c2548bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186933340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1186933340
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1514720389
Short name T460
Test name
Test status
Simulation time 164172811168 ps
CPU time 69.04 seconds
Started Aug 01 06:56:32 PM PDT 24
Finished Aug 01 06:57:41 PM PDT 24
Peak memory 201448 kb
Host smart-96424424-ee90-48b2-ba34-c0bb312258ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514720389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1514720389
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1820451809
Short name T150
Test name
Test status
Simulation time 500998421077 ps
CPU time 491.66 seconds
Started Aug 01 06:56:30 PM PDT 24
Finished Aug 01 07:04:42 PM PDT 24
Peak memory 201400 kb
Host smart-1c5edb75-0812-4584-ba9e-c72e182e0747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820451809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1820451809
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1108520748
Short name T372
Test name
Test status
Simulation time 328077796042 ps
CPU time 346.65 seconds
Started Aug 01 06:56:28 PM PDT 24
Finished Aug 01 07:02:15 PM PDT 24
Peak memory 201428 kb
Host smart-078eb6f0-be20-4739-9bd1-08de2a48f41d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108520748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1108520748
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3865293891
Short name T26
Test name
Test status
Simulation time 360846512741 ps
CPU time 231.86 seconds
Started Aug 01 06:56:29 PM PDT 24
Finished Aug 01 07:00:21 PM PDT 24
Peak memory 201408 kb
Host smart-3dbc6631-17fe-41b1-881c-a92ebe3a9c3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865293891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3865293891
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3335089253
Short name T415
Test name
Test status
Simulation time 408498379239 ps
CPU time 219.21 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 07:00:16 PM PDT 24
Peak memory 201440 kb
Host smart-c6bca6d4-d943-4129-a238-d9f77dd8a471
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335089253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3335089253
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3737061245
Short name T422
Test name
Test status
Simulation time 80373716728 ps
CPU time 400.44 seconds
Started Aug 01 06:56:37 PM PDT 24
Finished Aug 01 07:03:17 PM PDT 24
Peak memory 201836 kb
Host smart-b15c782b-dff5-4d2f-9706-d6cad5ee52b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737061245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3737061245
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3726553603
Short name T414
Test name
Test status
Simulation time 38726417206 ps
CPU time 84.66 seconds
Started Aug 01 06:56:31 PM PDT 24
Finished Aug 01 06:57:56 PM PDT 24
Peak memory 201384 kb
Host smart-e11fca43-f86f-4f1d-8234-959e6e86100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726553603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3726553603
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1537240510
Short name T506
Test name
Test status
Simulation time 4742339836 ps
CPU time 11.39 seconds
Started Aug 01 06:56:36 PM PDT 24
Finished Aug 01 06:56:48 PM PDT 24
Peak memory 201372 kb
Host smart-d3672aee-031a-4ea9-ac88-4a7b09df54b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537240510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1537240510
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.313247862
Short name T4
Test name
Test status
Simulation time 5774712552 ps
CPU time 14.51 seconds
Started Aug 01 06:56:26 PM PDT 24
Finished Aug 01 06:56:41 PM PDT 24
Peak memory 201544 kb
Host smart-62d5a7e1-df1d-48a7-9bb7-dade088cdeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313247862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.313247862
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.847940950
Short name T594
Test name
Test status
Simulation time 8986406187 ps
CPU time 22.18 seconds
Started Aug 01 06:56:37 PM PDT 24
Finished Aug 01 06:56:59 PM PDT 24
Peak memory 201320 kb
Host smart-5437093d-cde1-4797-b831-9dda0ddc46e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847940950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
847940950
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3219188355
Short name T749
Test name
Test status
Simulation time 527293576 ps
CPU time 1.85 seconds
Started Aug 01 06:52:04 PM PDT 24
Finished Aug 01 06:52:06 PM PDT 24
Peak memory 201248 kb
Host smart-9998a429-ee53-42e7-b630-fbdf08c5b609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219188355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3219188355
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.509026197
Short name T611
Test name
Test status
Simulation time 355686046617 ps
CPU time 204.72 seconds
Started Aug 01 06:51:57 PM PDT 24
Finished Aug 01 06:55:22 PM PDT 24
Peak memory 201452 kb
Host smart-40f23fc2-c709-490c-9a04-c69615cd6365
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509026197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.509026197
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3768883568
Short name T313
Test name
Test status
Simulation time 331917052593 ps
CPU time 165.07 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:54:44 PM PDT 24
Peak memory 201428 kb
Host smart-3cc5a2a1-6910-4cb8-975d-b9fa2662d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768883568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3768883568
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4155014717
Short name T57
Test name
Test status
Simulation time 320136960213 ps
CPU time 208.62 seconds
Started Aug 01 06:51:57 PM PDT 24
Finished Aug 01 06:55:26 PM PDT 24
Peak memory 201468 kb
Host smart-fe3620de-f9bb-4a74-b3b8-3428e81e3360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155014717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4155014717
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2850658886
Short name T583
Test name
Test status
Simulation time 481159516446 ps
CPU time 1028.11 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 07:09:06 PM PDT 24
Peak memory 201496 kb
Host smart-a8f9320f-9a46-4ab6-b0b8-605242690eea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850658886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2850658886
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3214126776
Short name T461
Test name
Test status
Simulation time 320817960775 ps
CPU time 184.24 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:55:06 PM PDT 24
Peak memory 201476 kb
Host smart-61ac9912-f3d8-4684-8a59-0ebbf3991fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214126776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3214126776
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.196908227
Short name T730
Test name
Test status
Simulation time 493690970772 ps
CPU time 114.61 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:53:55 PM PDT 24
Peak memory 201460 kb
Host smart-47407943-96b8-439e-9ffe-26bf4e514a14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=196908227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.196908227
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2339329009
Short name T194
Test name
Test status
Simulation time 200319225835 ps
CPU time 25.3 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:52:25 PM PDT 24
Peak memory 200964 kb
Host smart-ac39857e-938f-49b2-82bf-5f07e79a05cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339329009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2339329009
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3397227218
Short name T173
Test name
Test status
Simulation time 70798824461 ps
CPU time 360.73 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:58:03 PM PDT 24
Peak memory 201912 kb
Host smart-7e8695a8-141c-45b4-b5f4-bbbfbc80eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397227218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3397227218
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.621937940
Short name T616
Test name
Test status
Simulation time 27577498838 ps
CPU time 16.9 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:52:16 PM PDT 24
Peak memory 201352 kb
Host smart-1151f938-6166-4ceb-adb1-b4192c2ab07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621937940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.621937940
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1645870919
Short name T610
Test name
Test status
Simulation time 2997947672 ps
CPU time 2.22 seconds
Started Aug 01 06:52:04 PM PDT 24
Finished Aug 01 06:52:07 PM PDT 24
Peak memory 201224 kb
Host smart-3c383ad5-321d-4f55-a3d9-d73f9b603658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645870919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1645870919
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2901067180
Short name T381
Test name
Test status
Simulation time 6141705007 ps
CPU time 14.51 seconds
Started Aug 01 06:51:55 PM PDT 24
Finished Aug 01 06:52:10 PM PDT 24
Peak memory 201376 kb
Host smart-ab77587c-4871-4cbd-afb9-9f6390cd603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901067180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2901067180
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2131418142
Short name T285
Test name
Test status
Simulation time 671331544228 ps
CPU time 1458.1 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 07:16:20 PM PDT 24
Peak memory 201424 kb
Host smart-db352bc7-3f1c-4ab0-a5dc-a0d1ffd67ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131418142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2131418142
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2111085435
Short name T23
Test name
Test status
Simulation time 59912894809 ps
CPU time 133.51 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:54:15 PM PDT 24
Peak memory 210204 kb
Host smart-fabed599-895b-42c5-90f8-a62cdfdd76ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111085435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2111085435
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3359059360
Short name T669
Test name
Test status
Simulation time 534835586 ps
CPU time 0.69 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 06:52:07 PM PDT 24
Peak memory 201248 kb
Host smart-6b23b0a6-1f74-448e-9a46-15eea0f5000b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359059360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3359059360
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1353218607
Short name T239
Test name
Test status
Simulation time 161983161872 ps
CPU time 260.47 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:56:22 PM PDT 24
Peak memory 201440 kb
Host smart-aee045ac-0c42-449f-a41b-4747619d2f96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353218607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1353218607
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3124578173
Short name T249
Test name
Test status
Simulation time 526661170569 ps
CPU time 410.9 seconds
Started Aug 01 06:52:04 PM PDT 24
Finished Aug 01 06:58:55 PM PDT 24
Peak memory 201436 kb
Host smart-56cebf1a-80ed-4830-bd1e-e0ffd9756f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124578173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3124578173
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1386782704
Short name T656
Test name
Test status
Simulation time 331597075756 ps
CPU time 741.84 seconds
Started Aug 01 06:51:55 PM PDT 24
Finished Aug 01 07:04:17 PM PDT 24
Peak memory 201512 kb
Host smart-3902f6e3-adce-4937-a303-212ea44c42b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386782704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1386782704
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2031665235
Short name T572
Test name
Test status
Simulation time 493945761745 ps
CPU time 299.36 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:57:01 PM PDT 24
Peak memory 201428 kb
Host smart-4e734602-fc45-420a-b1e3-310f843f845c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031665235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2031665235
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3610624628
Short name T341
Test name
Test status
Simulation time 160050427126 ps
CPU time 96.1 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:53:41 PM PDT 24
Peak memory 201448 kb
Host smart-1e372dd4-a358-4bbd-a3bb-90d6b24b0db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610624628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3610624628
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1658760489
Short name T651
Test name
Test status
Simulation time 326451612034 ps
CPU time 729.84 seconds
Started Aug 01 06:51:55 PM PDT 24
Finished Aug 01 07:04:05 PM PDT 24
Peak memory 201420 kb
Host smart-b3e5a6f3-59b6-4a3e-94dd-233553c18a4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658760489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1658760489
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.415289039
Short name T619
Test name
Test status
Simulation time 202385513330 ps
CPU time 63.12 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:53:09 PM PDT 24
Peak memory 200764 kb
Host smart-3e944310-ef86-4aed-874d-2be4e90cfd1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415289039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.415289039
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3584014802
Short name T409
Test name
Test status
Simulation time 197819251568 ps
CPU time 470.01 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:59:49 PM PDT 24
Peak memory 201452 kb
Host smart-bbebc683-77e9-4c41-89bb-e4fcdaec1617
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584014802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3584014802
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1242547564
Short name T374
Test name
Test status
Simulation time 103130462014 ps
CPU time 370.6 seconds
Started Aug 01 06:52:07 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 201880 kb
Host smart-a4a6b9b7-16b1-4292-a7dc-5edcd76b0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242547564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1242547564
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2910033121
Short name T745
Test name
Test status
Simulation time 24038900752 ps
CPU time 15.01 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:52:20 PM PDT 24
Peak memory 201344 kb
Host smart-1f56f06a-cf19-43e6-913e-a8696f2320fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910033121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2910033121
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1723812649
Short name T463
Test name
Test status
Simulation time 3714453651 ps
CPU time 2.08 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 06:52:05 PM PDT 24
Peak memory 201336 kb
Host smart-5087aa7e-913f-4b78-bb97-5ce2b5893a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723812649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1723812649
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3297367001
Short name T575
Test name
Test status
Simulation time 6193234479 ps
CPU time 15.04 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 06:52:11 PM PDT 24
Peak memory 201368 kb
Host smart-112bd51b-b1aa-4431-813f-6c0efbc86ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297367001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3297367001
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.509005584
Short name T278
Test name
Test status
Simulation time 528497113224 ps
CPU time 402.15 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:58:48 PM PDT 24
Peak memory 201464 kb
Host smart-9a4dca8e-32e4-4d0d-9ec7-f8b23cdc55b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509005584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.509005584
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3775380213
Short name T12
Test name
Test status
Simulation time 466843670299 ps
CPU time 523.7 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 07:00:47 PM PDT 24
Peak memory 210148 kb
Host smart-dc29207d-8a3e-4b00-bd23-22bccad80516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775380213 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3775380213
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2350649914
Short name T778
Test name
Test status
Simulation time 521973296 ps
CPU time 1.22 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:52:07 PM PDT 24
Peak memory 201240 kb
Host smart-63cf93d7-4b82-4fe9-b613-f1ba6866aeae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350649914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2350649914
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3030253732
Short name T226
Test name
Test status
Simulation time 505935712696 ps
CPU time 418.86 seconds
Started Aug 01 06:51:57 PM PDT 24
Finished Aug 01 06:58:56 PM PDT 24
Peak memory 201460 kb
Host smart-801f8d39-c2f1-4ac3-8b12-9a5a4ff40c71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030253732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3030253732
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2292496456
Short name T103
Test name
Test status
Simulation time 553685572185 ps
CPU time 706.6 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:04:01 PM PDT 24
Peak memory 201464 kb
Host smart-0e05d794-7ee1-4676-98d6-fd34c71271ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292496456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2292496456
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.471727325
Short name T633
Test name
Test status
Simulation time 165595476018 ps
CPU time 212.11 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 06:55:38 PM PDT 24
Peak memory 201448 kb
Host smart-2d283b1f-ab0e-4b92-a0cf-e5c4b2cb085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471727325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.471727325
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2660889666
Short name T386
Test name
Test status
Simulation time 493687643843 ps
CPU time 1173.6 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 07:11:40 PM PDT 24
Peak memory 201452 kb
Host smart-f4e247c4-28ac-468c-bd61-6760b2275146
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660889666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2660889666
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2387880133
Short name T446
Test name
Test status
Simulation time 158076518513 ps
CPU time 182.1 seconds
Started Aug 01 06:51:59 PM PDT 24
Finished Aug 01 06:55:01 PM PDT 24
Peak memory 201500 kb
Host smart-e04ee90a-6df6-49a0-a4ed-2da15dda06f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387880133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2387880133
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3367536846
Short name T292
Test name
Test status
Simulation time 359959238449 ps
CPU time 782.79 seconds
Started Aug 01 06:52:11 PM PDT 24
Finished Aug 01 07:05:14 PM PDT 24
Peak memory 201424 kb
Host smart-8d597dd6-a329-44d6-8d8f-0650c13405b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367536846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3367536846
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3586482438
Short name T471
Test name
Test status
Simulation time 610532090565 ps
CPU time 1405.68 seconds
Started Aug 01 06:52:24 PM PDT 24
Finished Aug 01 07:15:50 PM PDT 24
Peak memory 201504 kb
Host smart-e9716e90-2815-4c4c-953b-a09e010f0a47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586482438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3586482438
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.388686199
Short name T399
Test name
Test status
Simulation time 101503000498 ps
CPU time 593.57 seconds
Started Aug 01 06:52:17 PM PDT 24
Finished Aug 01 07:02:10 PM PDT 24
Peak memory 201836 kb
Host smart-1adf9d49-131b-4269-8767-328cdd861378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388686199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.388686199
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3421422874
Short name T731
Test name
Test status
Simulation time 36749191365 ps
CPU time 19.79 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:52:25 PM PDT 24
Peak memory 200656 kb
Host smart-6d4b3b51-72be-4105-ad20-a9ae23b79bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421422874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3421422874
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1998009909
Short name T783
Test name
Test status
Simulation time 3127470480 ps
CPU time 7.42 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:52:07 PM PDT 24
Peak memory 201332 kb
Host smart-d0656658-1b26-4971-91a3-b39ffd55e833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998009909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1998009909
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1310471144
Short name T391
Test name
Test status
Simulation time 5894054276 ps
CPU time 13.66 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:52:15 PM PDT 24
Peak memory 201360 kb
Host smart-db15e700-0c46-4834-9661-c62f77e659b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310471144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1310471144
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2121597799
Short name T27
Test name
Test status
Simulation time 396092636 ps
CPU time 1.58 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 06:52:00 PM PDT 24
Peak memory 201252 kb
Host smart-5985f650-c3f7-4ad4-bb5a-ccca483d4234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121597799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2121597799
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3531086389
Short name T295
Test name
Test status
Simulation time 552089034571 ps
CPU time 919.32 seconds
Started Aug 01 06:52:11 PM PDT 24
Finished Aug 01 07:07:31 PM PDT 24
Peak memory 201408 kb
Host smart-8c11eff0-e201-4d30-880a-6c6bfc2eb4a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531086389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3531086389
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4232421809
Short name T184
Test name
Test status
Simulation time 324510280751 ps
CPU time 706.22 seconds
Started Aug 01 06:52:09 PM PDT 24
Finished Aug 01 07:03:55 PM PDT 24
Peak memory 201400 kb
Host smart-fcc8b0aa-0f4e-4604-a2ae-0421f1b3dd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232421809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4232421809
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2958039982
Short name T736
Test name
Test status
Simulation time 174909472555 ps
CPU time 193.26 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 06:55:19 PM PDT 24
Peak memory 201448 kb
Host smart-7cf0cf55-7194-4b01-82a9-abcecf63dba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958039982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2958039982
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4100916058
Short name T723
Test name
Test status
Simulation time 160924367124 ps
CPU time 84.77 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 06:53:31 PM PDT 24
Peak memory 201452 kb
Host smart-9dc41ee8-0f24-4a67-b8d2-36499a675a86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100916058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.4100916058
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.551648906
Short name T545
Test name
Test status
Simulation time 166495175115 ps
CPU time 347.64 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 06:58:02 PM PDT 24
Peak memory 201440 kb
Host smart-050a0be6-f545-4c4c-a4e9-214260b444c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551648906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.551648906
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1821055116
Short name T473
Test name
Test status
Simulation time 164071585541 ps
CPU time 101.63 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:53:43 PM PDT 24
Peak memory 201424 kb
Host smart-41e23a81-e6e5-465f-aaa2-79141a8a197b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821055116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1821055116
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3165586045
Short name T668
Test name
Test status
Simulation time 509207900291 ps
CPU time 621.85 seconds
Started Aug 01 06:52:20 PM PDT 24
Finished Aug 01 07:02:42 PM PDT 24
Peak memory 201392 kb
Host smart-45f469a1-6ed8-4aa6-9773-7e6543846a85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165586045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3165586045
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1755352300
Short name T742
Test name
Test status
Simulation time 601869357147 ps
CPU time 1422.65 seconds
Started Aug 01 06:51:56 PM PDT 24
Finished Aug 01 07:15:39 PM PDT 24
Peak memory 201424 kb
Host smart-f2a8444f-d544-4c18-985e-93d12a599f0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755352300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1755352300
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4051511623
Short name T207
Test name
Test status
Simulation time 112395880232 ps
CPU time 507.28 seconds
Started Aug 01 06:52:14 PM PDT 24
Finished Aug 01 07:00:41 PM PDT 24
Peak memory 201860 kb
Host smart-3bd3dcfb-4272-41b1-9bc1-748cc0154d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051511623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4051511623
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2621427031
Short name T419
Test name
Test status
Simulation time 42462437762 ps
CPU time 97.23 seconds
Started Aug 01 06:52:11 PM PDT 24
Finished Aug 01 06:53:48 PM PDT 24
Peak memory 201332 kb
Host smart-b71746b8-e8fe-4c7e-9a42-e4de2ec645bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621427031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2621427031
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.387910332
Short name T727
Test name
Test status
Simulation time 5004004503 ps
CPU time 7.38 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:52:08 PM PDT 24
Peak memory 201344 kb
Host smart-2edc920f-2aa4-4329-95ea-55f24e05187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387910332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.387910332
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1386697827
Short name T592
Test name
Test status
Simulation time 5633833876 ps
CPU time 12.22 seconds
Started Aug 01 06:52:00 PM PDT 24
Finished Aug 01 06:52:12 PM PDT 24
Peak memory 201332 kb
Host smart-cd0071cc-d127-4231-94b1-6bd9a5ed6676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386697827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1386697827
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2338312420
Short name T209
Test name
Test status
Simulation time 123592870025 ps
CPU time 460.83 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:59:43 PM PDT 24
Peak memory 200780 kb
Host smart-bf39ab6a-54bc-470a-b484-94cb2da2b02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338312420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2338312420
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3196124392
Short name T317
Test name
Test status
Simulation time 217712859115 ps
CPU time 115.14 seconds
Started Aug 01 06:52:11 PM PDT 24
Finished Aug 01 06:54:06 PM PDT 24
Peak memory 210124 kb
Host smart-639186c0-5ecd-40ff-816f-9a2fdbb428e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196124392 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3196124392
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3699562763
Short name T367
Test name
Test status
Simulation time 340086524 ps
CPU time 1.05 seconds
Started Aug 01 06:52:19 PM PDT 24
Finished Aug 01 06:52:20 PM PDT 24
Peak memory 201236 kb
Host smart-e987c484-da62-48bb-ad70-943a5b78651f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699562763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3699562763
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.631814747
Short name T756
Test name
Test status
Simulation time 165692163461 ps
CPU time 41.86 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:52:47 PM PDT 24
Peak memory 201364 kb
Host smart-b3655d73-a0a7-4baf-90fd-e2092d27e96e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631814747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.631814747
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1170290917
Short name T701
Test name
Test status
Simulation time 165731956975 ps
CPU time 403.82 seconds
Started Aug 01 06:52:03 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 200464 kb
Host smart-194c5b5b-b458-4411-97db-d1d4e679402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170290917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1170290917
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.494841241
Short name T270
Test name
Test status
Simulation time 320231849695 ps
CPU time 575.79 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 201424 kb
Host smart-99f13c5d-f082-4413-b633-4470f658081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494841241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.494841241
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3473819658
Short name T254
Test name
Test status
Simulation time 328125259280 ps
CPU time 656.31 seconds
Started Aug 01 06:52:08 PM PDT 24
Finished Aug 01 07:03:05 PM PDT 24
Peak memory 201372 kb
Host smart-5cd2757c-21de-4904-8f5c-6f7c0583e63d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473819658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3473819658
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2480078574
Short name T322
Test name
Test status
Simulation time 325133970306 ps
CPU time 773.95 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 07:04:52 PM PDT 24
Peak memory 201432 kb
Host smart-806e7c2b-3516-4a4f-9dba-cf6690092cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480078574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2480078574
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1429921235
Short name T557
Test name
Test status
Simulation time 327696711966 ps
CPU time 789.48 seconds
Started Aug 01 06:51:58 PM PDT 24
Finished Aug 01 07:05:07 PM PDT 24
Peak memory 201420 kb
Host smart-6ed3d444-2806-4dd6-a0ae-77ad58166915
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429921235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1429921235
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3816847935
Short name T728
Test name
Test status
Simulation time 598913477872 ps
CPU time 1406.1 seconds
Started Aug 01 06:52:12 PM PDT 24
Finished Aug 01 07:15:38 PM PDT 24
Peak memory 201356 kb
Host smart-4deea757-5f0b-466a-b32c-c82045b19d51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816847935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3816847935
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2273730634
Short name T691
Test name
Test status
Simulation time 97119084925 ps
CPU time 502.36 seconds
Started Aug 01 06:52:06 PM PDT 24
Finished Aug 01 07:00:29 PM PDT 24
Peak memory 201856 kb
Host smart-d3d0d7a2-02fe-4656-8e59-3756a1bd179a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273730634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2273730634
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3906798424
Short name T739
Test name
Test status
Simulation time 28036112784 ps
CPU time 31.97 seconds
Started Aug 01 06:52:05 PM PDT 24
Finished Aug 01 06:52:37 PM PDT 24
Peak memory 201376 kb
Host smart-5f9bd083-f118-4084-860a-f63e811bf6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906798424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3906798424
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1201527991
Short name T436
Test name
Test status
Simulation time 3112075206 ps
CPU time 7.7 seconds
Started Aug 01 06:52:08 PM PDT 24
Finished Aug 01 06:52:16 PM PDT 24
Peak memory 201336 kb
Host smart-ab7a667b-72d1-4730-87c8-04913e0f1cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201527991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1201527991
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.530744116
Short name T438
Test name
Test status
Simulation time 5822596491 ps
CPU time 6.69 seconds
Started Aug 01 06:52:01 PM PDT 24
Finished Aug 01 06:52:08 PM PDT 24
Peak memory 201360 kb
Host smart-5ebea2e4-e242-46ce-b14c-597340e4b80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530744116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.530744116
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1846196791
Short name T342
Test name
Test status
Simulation time 129895743093 ps
CPU time 122.05 seconds
Started Aug 01 06:52:02 PM PDT 24
Finished Aug 01 06:54:04 PM PDT 24
Peak memory 210176 kb
Host smart-1015d0e2-9517-4619-bc3e-8032d5a6f03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846196791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1846196791
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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