Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7011	1			T7	4		T8	99		T9	41
testmodes[AdcCtrlTestmodeNormal]	5642	1			T2	3		T3	1		T5	1
testmodes[AdcCtrlTestmodeLowpower]	6006	1			T1	2		T4	1		T8	71
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3735	1			T7	1		T8	48		T9	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1777	1			T7	3		T8	21		T9	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1387	1			T8	29		T9	19		T15	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1749	1			T7	2		T8	25		T9	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2084	1			T2	2		T6	1		T7	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1461	1			T8	21		T9	10		T15	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1422	1			T8	26		T9	17		T15	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1435	1			T8	24		T9	13		T15	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2910	1			T1	1		T8	21		T9	9