Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23342

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3340

1

T4

1

T6

1

T149

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20817

1

T3

1

T5

9

T7

14

auto[1]

5865

1

T1

25

T2

24

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	20	1			T27	8		T39	6		T147	3
values[1]	781	1			T4	1		T6	1		T149	1
values[2]	641	1			T180	22		T55	4		T145	31
values[3]	679	1			T13	1		T149	1		T15	9
values[4]	653	1			T47	17		T150	1		T156	13
values[5]	2799	1			T1	25		T2	24		T5	9
values[6]	639	1			T25	16		T47	20		T40	13
values[7]	729	1			T6	1		T164	7		T166	1
values[8]	790	1			T3	1		T149	1		T30	1
values[9]	1138	1			T15	11		T180	4		T146	13
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T4	1		T6	1		T149	1
values[1]	691	1			T30	1		T153	8		T180	6
values[2]	630	1			T13	1		T149	1		T15	9
values[3]	3018	1			T1	25		T2	24		T10	3
values[4]	460	1			T5	9		T11	2		T46	9
values[5]	772	1			T6	1		T25	16		T47	20
values[6]	660	1			T35	12		T166	1		T241	1
values[7]	719	1			T3	1		T149	1		T30	1
values[8]	773	1			T15	11		T180	4		T165	15
values[9]	300	1			T188	26		T242	10		T182	20
minimum	17821	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T149	1		T27	8		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	1		T6	1		T47	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T153	1		T180	1		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	1		T145	17		T146	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T35	13		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T149	1		T15	5		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T1	25		T2	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	17		T218	10		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	1		T11	1		T146	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T46	7		T164	16		T181	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T25	8		T164	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	20		T40	7		T36	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	3		T166	1		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T243	1		T244	1		T245	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	1		T154	1		T146	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T149	1		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T224	1		T170	15		T181	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T15	5		T180	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T246	1		T247	1		T248	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T188	14		T242	10		T182	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17660	1			T7	14		T8	229		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T39	1		T180	15		T36	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	6		T214	2		T89	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T153	7		T180	5		T55	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	14		T146	9		T158	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	8		T37	13		T249	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	4		T166	3		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T2	21		T44	15		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T86	6		T251	8		T252	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T5	8		T11	1		T146	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T46	2		T164	16		T181	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T25	8		T164	4		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	6		T36	12		T188	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	9		T224	15		T157	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T243	2		T244	1		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T146	11		T159	2		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T145	11		T250	8		T254	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T224	13		T181	18		T85	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	6		T180	3		T165	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T246	2		T248	1		T255	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T188	12		T182	8		T18	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	2		T15	9		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T27	8		T39	5		T147	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T256	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T149	1		T30	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	1		T6	1		T47	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T180	2		T55	3		T182	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	17		T146	14		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	1		T35	13		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T149	1		T15	5		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T156	1		T37	11		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T47	17		T150	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T1	25		T2	3		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	7		T164	16		T181	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T25	8		T41	4		T170	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T47	20		T40	7		T36	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	1		T164	3		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T244	1		T245	12		T258	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	1		T35	3		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T149	1		T30	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T146	2		T224	1		T170	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T15	5		T180	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T39	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T36	10		T158	3		T17	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T16	6		T214	2		T252	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T180	20		T55	1		T182	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T145	14		T146	9		T158	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	8		T153	7		T249	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T15	4		T166	3		T251	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T156	12		T37	13		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T250	9		T86	6		T259	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T2	21		T5	8		T11	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T46	2		T164	16		T181	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T25	8		T41	2		T243	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	6		T36	12		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T164	4		T224	15		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T244	1		T245	10		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	9		T157	15		T181	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T145	11		T250	8		T254	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	11		T224	13		T85	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T15	6		T180	3		T165	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T149	1		T27	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T4	1		T6	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T153	8		T180	6		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	1		T145	15		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T35	9		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T149	1		T15	8		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T1	2		T2	24		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	1		T218	1		T86	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	9		T11	2		T146	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	3		T164	17		T181	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	1		T25	9		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	1		T40	12		T36	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	10		T166	1		T241	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T243	3		T244	2		T245	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T154	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T149	1		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T224	14		T170	1		T181	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	10		T180	4		T165	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T246	3		T247	1		T248	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T188	13		T242	1		T182	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17818	1			T7	14		T8	231		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	7		T39	2		T17	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T47	13		T214	9		T218	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T55	2		T182	9		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	16		T146	13		T260	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	12		T155	12		T37	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T15	1		T166	11		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T1	23		T12	26		T261	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T47	16		T218	9		T251	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T146	18		T170	6		T159	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	6		T164	15		T181	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T25	7		T164	2		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	19		T40	1		T36	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T35	2		T157	12		T181	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T245	11		T246	8		T114	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T146	1		T159	6		T262	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T145	11		T218	7		T254	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T170	14		T181	15		T85	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	1		T263	6		T157	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T248	3		T255	15		T264	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T188	13		T242	9		T182	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T184	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T27	1		T39	4		T147	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T149	1		T30	1		T36	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	1		T6	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T180	22		T55	2		T182	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T145	15		T146	10		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T35	9		T153	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T149	1		T15	8		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T156	13		T37	14		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	1		T150	1		T250	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T1	2		T2	24		T5	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	3		T164	17		T181	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	9		T41	4		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T47	1		T40	12		T36	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	1		T164	5		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T244	2		T245	11		T258	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	1		T35	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T149	1		T30	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T146	12		T224	14		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T15	10		T180	4		T165	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T27	7		T39	2		T147	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	5		T85	12		T244	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T47	13		T214	9		T218	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T55	2		T182	9		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T145	16		T146	13		T260	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	12		T155	12		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	1		T166	11		T170	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	10		T42	1		T242	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	16		T218	9		T259	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T1	23		T12	26		T261	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	6		T164	15		T181	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T25	7		T41	2		T170	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T47	19		T40	1		T36	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T164	2		T181	7		T152	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T245	11		T246	8		T114	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T35	2		T157	12		T181	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T145	11		T218	7		T254	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T146	1		T170	14		T85	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T15	1		T263	6		T188	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23102

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3580

1

T5

9

T6

2

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20654

1

T7

14

T8

231

T9

120

auto[1]

6028

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T155	13		T220	11		-	-
values[0]	50	1			T188	27		T162	9		T183	1
values[1]	807	1			T6	1		T46	9		T35	21
values[2]	520	1			T5	9		T39	6		T265	12
values[3]	681	1			T15	9		T30	1		T164	7
values[4]	804	1			T4	1		T149	3		T30	1
values[5]	500	1			T6	1		T11	2		T13	1
values[6]	592	1			T166	15		T36	11		T156	13
values[7]	825	1			T3	1		T47	17		T35	12
values[8]	675	1			T27	8		T30	1		T47	20
values[9]	3391	1			T1	25		T2	24		T10	3
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	946	1			T6	1		T39	6		T46	9
values[1]	520	1			T5	9		T15	9		T145	23
values[2]	729	1			T149	1		T30	1		T164	7
values[3]	779	1			T4	1		T13	1		T149	2
values[4]	499	1			T11	2		T180	16		T150	1
values[5]	656	1			T6	1		T166	16		T36	11
values[6]	3095	1			T1	25		T2	24		T3	1
values[7]	674	1			T30	1		T151	1		T169	1
values[8]	802	1			T15	11		T25	16		T47	14
values[9]	141	1			T153	8		T180	4		T55	4
minimum	17841	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T39	5		T46	7		T35	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T6	1		T265	1		T37	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	5		T165	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T145	12		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	1		T164	3		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T149	1		T154	1		T157	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	1		T149	1		T180	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T13	1		T149	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	1		T180	1		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T150	1		T188	14		T45	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T166	12		T170	7		T242	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T166	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T1	25		T2	3		T3	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T27	8		T47	20		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T169	1		T152	14		T266	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T30	1		T151	1		T88	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T15	5		T250	1		T242	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T25	8		T47	14		T155	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T153	1		T55	3		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T180	1		T17	2		T267	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T224	1		T268	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	1		T46	2		T35	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T265	11		T37	13		T157	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T15	4		T165	14		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	8		T145	11		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T164	4		T224	15		T181	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T157	9		T266	11		T269	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T180	5		T18	6		T85	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T146	11		T181	6		T159	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T11	1		T180	15		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T188	12		T45	2		T260	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T166	3		T177	10		T251	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	10		T156	12		T181	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T2	21		T44	15		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	9		T164	16		T263	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T152	14		T266	14		T269	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T245	10		T270	12		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	6		T250	8		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T25	8		T182	8		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T153	7		T55	1		T271	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T180	3		T272	9		T187	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T224	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T155	13		T220	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T188	13		T162	9		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T46	7		T35	13		T40	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	1		T224	1		T37	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T39	5		T165	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T265	1		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	5		T30	1		T164	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T157	11		T159	7		T273	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T149	1		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T149	2		T30	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	1		T180	1		T242	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	1		T13	1		T146	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T166	12		T170	7		T85	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T36	1		T156	1		T181	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T47	17		T146	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T35	3		T166	1		T263	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	2		T152	14		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	8		T30	1		T47	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1767	1			T1	25		T2	3		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T25	8		T47	14		T180	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T188	14		T274	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T46	2		T35	8		T40	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T224	13		T37	13		T157	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T39	1		T165	14		T243	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	8		T265	11		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	4		T164	4		T181	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T157	9		T159	2		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T180	5		T224	15		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T181	6		T85	9		T260	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	1		T180	15		T158	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T146	11		T188	12		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T166	3		T85	11		T251	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T36	10		T156	12		T181	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T146	9		T36	12		T159	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	9		T263	6		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	6		T152	14		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T164	16		T250	9		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T2	21		T44	15		T15	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T25	8		T180	3		T182	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2