Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23390

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3292

1

T4

1

T6

1

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20679

1

T3

1

T5

9

T7

14

auto[1]

6003

1

T1

25

T2

24

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T15	11		T182	20		T160	10
values[0]	5	1			T147	3		T256	2		-	-
values[1]	743	1			T4	1		T6	1		T149	1
values[2]	685	1			T30	1		T153	8		T180	22
values[3]	680	1			T13	1		T149	1		T15	9
values[4]	667	1			T265	12		T47	17		T150	1
values[5]	2773	1			T1	25		T2	24		T5	9
values[6]	659	1			T25	16		T47	20		T40	13
values[7]	784	1			T6	1		T35	12		T164	7
values[8]	645	1			T3	1		T149	1		T30	1
values[9]	979	1			T180	4		T146	13		T165	15
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T6	1		T149	1		T27	8
values[1]	677	1			T30	1		T153	8		T180	22
values[2]	708	1			T13	1		T149	1		T15	9
values[3]	2952	1			T1	25		T2	24		T10	3
values[4]	480	1			T5	9		T11	2		T46	9
values[5]	766	1			T6	1		T25	16		T47	20
values[6]	618	1			T35	12		T166	1		T241	1
values[7]	720	1			T3	1		T149	1		T30	1
values[8]	871	1			T15	11		T180	4		T146	13
values[9]	216	1			T188	26		T242	10		T182	20
minimum	18014	1			T4	1		T7	14		T8	231

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T149	1		T27	8		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	1		T16	2		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T153	1		T180	2		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	1		T145	17		T146	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T35	13		T155	13		T37	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	1		T149	1		T15	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T1	25		T2	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T47	17		T156	1		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	1		T11	1		T164	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	7		T181	9		T273	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T25	8		T164	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T47	20		T40	7		T36	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T35	3		T241	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T166	1		T157	13		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T154	1		T159	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T149	1		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T146	2		T165	1		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T15	5		T180	1		T263	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T247	1		T248	4		T323	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T188	14		T242	10		T182	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17697	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T4	1		T47	14		T214	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T36	10		T158	3		T85	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	6		T17	4		T89	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T153	7		T180	20		T55	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T145	14		T146	9		T158	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T35	8		T37	13		T152	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	4		T166	3		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T2	21		T44	15		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T156	12		T42	1		T86	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	8		T11	1		T164	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T46	2		T181	6		T177	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T25	8		T164	4		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	6		T36	12		T188	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	9		T224	15		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T157	15		T244	1		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T159	2		T253	11		T324	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T145	11		T250	8		T271	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T146	11		T165	14		T224	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	6		T180	3		T263	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T248	1		T264	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T188	12		T182	8		T160	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	2		T15	9		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T214	2		T252	16		T293	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T325	1		T326	1		T327	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	5		T182	12		T160	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T147	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T256	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T149	1		T27	8		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T6	1		T47	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T153	1		T180	2		T55	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	1		T145	17		T146	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T35	13		T155	13		T37	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	1		T149	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T265	1		T242	9		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T47	17		T150	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T1	25		T2	3		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	7		T42	3		T181	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T25	8		T146	19		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T47	20		T40	7		T36	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	1		T35	3		T164	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T166	1		T157	13		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T154	1		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T149	1		T30	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T146	2		T165	1		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T180	1		T263	7		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T327	9		T328	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T15	6		T182	8		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T39	1		T36	10		T158	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	6		T214	2		T17	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	7		T180	20		T55	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T145	14		T146	9		T158	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	8		T37	13		T152	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	4		T166	3		T251	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T265	11		T89	15		T289	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T156	12		T250	9		T86	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T2	21		T5	8		T11	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T46	2		T42	1		T181	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T25	8		T146	15		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	6		T36	12		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T35	9		T164	4		T224	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T157	15		T244	1		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T159	2		T253	11		T117	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	11		T250	8		T271	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T146	11		T165	14		T224	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T180	3		T263	6		T188	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T149	1		T27	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T16	8		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T153	8		T180	22		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	1		T145	15		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T35	9		T155	1		T37	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	1		T149	1		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	2		T2	24		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	1		T156	13		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	9		T11	2		T164	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T46	3		T181	7		T273	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	1		T25	9		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T47	1		T40	12		T36	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	10		T241	1		T224	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T166	1		T157	16		T244	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T154	1		T159	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T149	1		T30	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T146	12		T165	15		T224	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	10		T180	4		T263	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	1		T248	2		T323	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T188	13		T242	1		T182	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17855	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T4	1		T47	1		T214	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T27	7		T85	12		T244	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T17	5		T277	2		T269	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	2		T182	9		T260	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T145	16		T146	13		T179	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T35	12		T155	12		T37	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T15	1		T166	11		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T1	23		T12	26		T261	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	16		T42	1		T218	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T164	15		T146	18		T170	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T46	6		T181	8		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T25	7		T164	2		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T47	19		T40	1		T36	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T35	2		T181	7		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T157	12		T245	11		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T159	6		T262	2		T306	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T145	11		T218	7		T162	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	1		T170	14		T181	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	1		T263	6		T157	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T248	3		T323	21		T264	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T188	13		T242	9		T182	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T39	2		T147	1		T184	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T47	13		T214	9		T218	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T325	1		T326	1		T327	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	10		T182	9		T160	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T147	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T149	1		T27	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	1		T6	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T153	8		T180	22		T55	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	1		T145	15		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T35	9		T155	1		T37	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	1		T149	1		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T265	12		T242	2		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T47	1		T150	1		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T1	2		T2	24		T5	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T46	3		T42	3		T181	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T25	9		T146	16		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	1		T40	12		T36	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T6	1		T35	10		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T166	1		T157	16		T244	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T154	1		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T149	1		T30	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T146	12		T165	15		T224	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T180	4		T263	7		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T327	10		T328	3		T323	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T15	1		T182	11		T277	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T147	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T27	7		T39	2		T85	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T47	13		T214	9		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	2		T182	9		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T145	16		T146	13		T179	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	12		T155	12		T37	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	1		T166	11		T170	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T242	7		T275	8		T278	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	16		T218	9		T259	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T1	23		T12	26		T164	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	6		T42	1		T181	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T25	7		T146	18		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	19		T40	1		T36	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T35	2		T164	2		T181	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T157	12		T245	11		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T159	6		T306	4		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T145	11		T218	7		T162	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T146	1		T170	14		T181	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T263	6		T188	13		T157	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2