Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23014

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3668

1

T4

1

T6

1

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20966

1

T4

1

T5

9

T6

1

auto[1]

5716

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T263	13		T329	7		T59	3
values[0]	71	1			T42	1		T315	10		T279	28
values[1]	542	1			T265	12		T164	32		T146	13
values[2]	751	1			T15	9		T30	1		T39	6
values[3]	669	1			T149	2		T46	9		T47	17
values[4]	703	1			T6	1		T13	1		T154	1
values[5]	2799	1			T1	25		T2	24		T10	3
values[6]	600	1			T3	1		T5	9		T149	1
values[7]	606	1			T164	7		T150	1		T250	10
values[8]	859	1			T6	1		T11	2		T25	16
values[9]	1246	1			T4	1		T15	11		T27	8
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	692	1			T15	9		T265	12		T47	20
values[1]	779	1			T39	6		T47	31		T35	21
values[2]	778	1			T13	1		T149	2		T30	1
values[3]	2855	1			T1	25		T2	24		T6	1
values[4]	463	1			T180	16		T224	14		T219	1
values[5]	672	1			T3	1		T5	9		T149	1
values[6]	712	1			T25	16		T165	15		T150	1
values[7]	755	1			T6	1		T11	2		T180	4
values[8]	815	1			T4	1		T15	11		T27	8
values[9]	305	1			T35	12		T156	5		T170	7
minimum	17856	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	20		T42	1		T214	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	5		T265	1		T164	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T166	12		T157	13		T242	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T39	5		T47	31		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T153	1		T180	1		T146	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	1		T149	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T1	25		T2	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T30	1		T155	13		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T180	1		T224	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T249	1		T43	1		T45	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T5	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T164	3		T36	1		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T25	8		T165	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T150	1		T85	13		T270	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T180	1		T36	15		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T11	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	5		T27	8		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T4	1		T40	7		T145	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T170	7		T330	1		T246	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T35	3		T156	1		T242	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17657	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T331	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T214	2		T258	2		T160	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	4		T265	11		T164	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T166	3		T157	15		T85	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	1		T35	8		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T153	7		T180	5		T146	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T46	2		T16	6		T157	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T2	21		T44	15		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T224	15		T266	14		T332	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T180	15		T224	13		T205	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T249	2		T45	2		T245	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	8		T250	8		T260	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T164	4		T36	10		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T25	8		T165	14		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T85	11		T270	2		T304	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T180	3		T36	12		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T145	11		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	6		T55	1		T181	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	6		T145	14		T263	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T246	2		T298	5		T333	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T35	9		T156	4		T251	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T331	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T329	7		T59	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T263	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T42	1		T279	16		T334	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T315	5		T333	1		T335	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T258	3		T336	1		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T265	1		T164	16		T146	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	20		T166	12		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T15	5		T30	1		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T153	1		T180	1		T146	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T149	2		T46	7		T47	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T146	14		T170	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	1		T154	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T1	25		T2	3		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	1		T257	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	1		T5	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	1		T249	1		T85	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T250	1		T182	10		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T164	3		T150	1		T42	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T25	8		T165	1		T36	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T6	1		T11	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T15	5		T27	8		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	415	1			T4	1		T35	3		T40	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T263	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T279	12		T337	2		T338	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T315	5		T333	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T258	2		T316	17		T203	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T265	11		T164	16		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T166	3		T157	15		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	4		T39	1		T35	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T153	7		T180	5		T146	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T46	2		T157	9		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T146	9		T17	4		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T224	15		T16	6		T152	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T2	21		T44	15		T29	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	2		T270	2		T332	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	8		T180	15		T250	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	10		T249	2		T85	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T250	9		T182	9		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T164	4		T42	1		T290	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	8		T165	14		T36	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T145	11		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T15	6		T180	3		T55	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T35	9		T40	6		T145	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T47	1		T42	1		T214	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	8		T265	12		T164	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T166	4		T157	16		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T39	4		T47	2		T35	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T153	8		T180	6		T146	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T149	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T1	2		T2	24		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	1		T155	1		T224	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T180	16		T224	14		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T249	3		T43	1		T45	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T5	9		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T164	5		T36	11		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T25	9		T165	15		T250	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T150	1		T85	12		T270	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T180	4		T36	13		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	1		T11	2		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	10		T27	1		T55	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	1		T40	12		T145	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T170	1		T330	1		T246	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	10		T156	5		T242	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17825	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T331	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	19		T214	9		T258	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	1		T164	15		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T166	11		T157	12		T242	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T39	2		T47	29		T35	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	18		T17	5		T159	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T46	6		T157	10		T152	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T1	23		T12	26		T261	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T155	12		T332	10		T281	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T205	7		T99	13		T339	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T245	11		T315	15		T307	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T218	16		T260	5		T259	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T164	2		T42	1		T177	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	7		T182	9		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T85	12		T304	1		T162	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T36	14		T188	13		T242	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	11		T41	2		T37	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T27	7		T55	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T40	1		T145	16		T263	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T170	6		T246	8		T317	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T35	2		T242	3		T251	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T331	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T329	1		T59	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T263	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T42	1		T279	13		T334	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T315	6		T333	15		T335	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T258	4		T336	1		T316	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T265	12		T164	17		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T47	1		T166	4		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T15	8		T30	1		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T153	8		T180	6		T146	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T149	2		T46	3		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	1		T146	10		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	1		T154	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T1	2		T2	24		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	1		T257	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	1		T5	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T36	11		T249	3		T85	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T250	10		T182	10		T158	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T164	5		T150	1		T42	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T25	9		T165	15		T36	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T11	2		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T15	10		T27	1		T180	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T4	1		T35	10		T40	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T329	6		T59	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T263	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T279	15		T338	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T315	4		T340	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T258	1		T121	1		T327	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T164	15		T146	1		T309	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T47	19		T166	11		T157	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	1		T39	2		T47	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	18		T159	15		T147	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	6		T47	16		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T146	13		T170	14		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T152	13		T244	13		T293	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T1	23		T12	26		T261	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T332	10		T291	20		T315	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T218	16		T260	5		T162	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T85	12		T177	16		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T182	9		T177	11		T260	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T164	2		T42	1		T87	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T25	7		T36	14		T188	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T145	11		T41	2		T51	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	1		T27	7		T55	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T35	2		T40	1		T145	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2